2 * Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <fsl_esdhc.h>
33 #include <asm/cache.h>
36 DECLARE_GLOBAL_DATA_PTR;
46 char buf1[32], buf2[32];
47 #ifdef CONFIG_DDR_CLK_FREQ
48 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
49 #ifdef CONFIG_FSL_CORENET
50 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
51 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
53 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
54 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
57 #ifdef CONFIG_FSL_CORENET
62 #endif /* CONFIG_DDR_CLK_FREQ */
68 major &= 0x7; /* the msb of this nibble is a mfg code */
72 if (cpu_numcores() > 1) {
74 puts("Unicore software on multiprocessor system!!\n"
75 "To enable mutlticore build define CONFIG_MP\n");
77 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
78 printf("CPU%d: ", pic->whoami);
86 if (IS_E_PROCESSOR(svr))
89 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
99 case PVR_FAM(PVR_85xx):
107 if (PVR_MEM(pvr) == 0x03)
110 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
112 get_sys_info(&sysinfo);
114 puts("Clock Configuration:");
115 for (i = 0; i < cpu_numcores(); i++) {
118 printf("CPU%d:%-4s MHz, ",
119 i,strmhz(buf1, sysinfo.freqProcessor[i]));
121 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
123 #ifdef CONFIG_FSL_CORENET
125 printf(" DDR:%-4s MHz (%s MT/s data rate) "
127 strmhz(buf1, sysinfo.freqDDRBus/2),
128 strmhz(buf2, sysinfo.freqDDRBus));
130 printf(" DDR:%-4s MHz (%s MT/s data rate) "
132 strmhz(buf1, sysinfo.freqDDRBus/2),
133 strmhz(buf2, sysinfo.freqDDRBus));
138 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
139 strmhz(buf1, sysinfo.freqDDRBus/2),
140 strmhz(buf2, sysinfo.freqDDRBus));
143 printf(" DDR:%-4s MHz (%s MT/s data rate) "
145 strmhz(buf1, sysinfo.freqDDRBus/2),
146 strmhz(buf2, sysinfo.freqDDRBus));
149 printf(" DDR:%-4s MHz (%s MT/s data rate) "
151 strmhz(buf1, sysinfo.freqDDRBus/2),
152 strmhz(buf2, sysinfo.freqDDRBus));
157 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
158 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
160 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
161 sysinfo.freqLocalBus);
165 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
169 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
172 #ifdef CONFIG_SYS_DPAA_FMAN
173 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
174 printf(" FMAN%d: %s MHz\n", i,
175 strmhz(buf1, sysinfo.freqFMan[i]));
179 #ifdef CONFIG_SYS_DPAA_PME
180 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
183 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
189 /* ------------------------------------------------------------------------- */
191 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
193 /* Everything after the first generation of PQ3 parts has RSTCR */
194 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
195 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
196 unsigned long val, msr;
199 * Initiate hard reset in debug control register DBCR0
200 * Make sure MSR[DE] = 1. This only resets the core.
210 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
211 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */
220 * Get timebase clock frequency
222 unsigned long get_tbclk (void)
224 #ifdef CONFIG_FSL_CORENET
225 return (gd->bus_clk + 8) / 16;
227 return (gd->bus_clk + 4UL)/8UL;
232 #if defined(CONFIG_WATCHDOG)
236 int re_enable = disable_interrupts();
237 reset_85xx_watchdog();
238 if (re_enable) enable_interrupts();
242 reset_85xx_watchdog(void)
245 * Clear TSR(WIS) bit by writing 1
248 val = mfspr(SPRN_TSR);
250 mtspr(SPRN_TSR, val);
252 #endif /* CONFIG_WATCHDOG */
255 * Configures a UPM. The function requires the respective MxMR to be set
256 * before calling this function. "size" is the number or entries, not a sizeof.
258 void upmconfig (uint upm, uint * table, uint size)
260 int i, mdr, mad, old_mad = 0;
262 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
263 volatile u32 *brp,*orp;
264 volatile u8* dummy = NULL;
270 upmmask = BR_MS_UPMA;
274 upmmask = BR_MS_UPMB;
278 upmmask = BR_MS_UPMC;
281 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
285 /* Find the address for the dummy write transaction */
286 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
287 i++, brp += 2, orp += 2) {
289 /* Look for a valid BR with selected UPM */
290 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
291 dummy = (volatile u8*)(in_be32(brp) & BR_BA);
297 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
301 for (i = 0; i < size; i++) {
303 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
305 out_be32(&lbc->mdr, table[i]);
307 mdr = in_be32(&lbc->mdr);
309 *(volatile u8 *)dummy = 0;
312 mad = in_be32(mxmr) & MxMR_MAD_MSK;
313 } while (mad <= old_mad && !(!mad && i == (size-1)));
316 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
320 * Initializes on-chip MMC controllers.
321 * to override, implement board_mmc_init()
323 int cpu_mmc_init(bd_t *bis)
325 #ifdef CONFIG_FSL_ESDHC
326 return fsl_esdhc_mmc_init(bis);