2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * SPDX-License-Identifier: GPL-2.0+
16 #include <fsl_esdhc.h>
17 #include <asm/cache.h>
21 #include <asm/fsl_law.h>
22 #include <asm/fsl_lbc.h>
24 #include <asm/processor.h>
25 #include <fsl_ddr_sdram.h>
27 DECLARE_GLOBAL_DATA_PTR;
30 * Default board reset function
37 void board_reset(void) __attribute__((weak, alias("__board_reset")));
46 char buf1[32], buf2[32];
47 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
48 ccsr_gur_t __iomem *gur =
49 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
53 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
54 * mode. Previous platform use ddr ratio to do the same. This
55 * information is only for display here.
57 #ifdef CONFIG_FSL_CORENET
58 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
59 u32 ddr_sync = 0; /* only async mode is supported */
61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
63 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
64 #else /* CONFIG_FSL_CORENET */
65 #ifdef CONFIG_DDR_CLK_FREQ
66 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
67 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
70 #endif /* CONFIG_DDR_CLK_FREQ */
71 #endif /* CONFIG_FSL_CORENET */
73 unsigned int i, core, nr_cores = cpu_numcores();
74 u32 mask = cpu_mask();
80 if (cpu_numcores() > 1) {
82 puts("Unicore software on multiprocessor system!!\n"
83 "To enable mutlticore build define CONFIG_MP\n");
85 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
86 printf("CPU%d: ", pic->whoami);
94 if (IS_E_PROCESSOR(svr))
97 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
101 major = PVR_MAJ(pvr);
102 minor = PVR_MIN(pvr);
106 case PVR_VER_E500_V1:
107 case PVR_VER_E500_V2:
124 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
126 if (nr_cores > CONFIG_MAX_CPUS) {
127 panic("\nUnexpected number of cores: %d, max is %d\n",
128 nr_cores, CONFIG_MAX_CPUS);
131 get_sys_info(&sysinfo);
133 puts("Clock Configuration:");
134 for_each_cpu(i, core, nr_cores, mask) {
137 printf("CPU%d:%-4s MHz, ", core,
138 strmhz(buf1, sysinfo.freq_processor[core]));
140 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
143 #ifdef CONFIG_FSL_CORENET
145 printf(" DDR:%-4s MHz (%s MT/s data rate) "
147 strmhz(buf1, sysinfo.freq_ddrbus/2),
148 strmhz(buf2, sysinfo.freq_ddrbus));
150 printf(" DDR:%-4s MHz (%s MT/s data rate) "
152 strmhz(buf1, sysinfo.freq_ddrbus/2),
153 strmhz(buf2, sysinfo.freq_ddrbus));
158 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
159 strmhz(buf1, sysinfo.freq_ddrbus/2),
160 strmhz(buf2, sysinfo.freq_ddrbus));
163 printf(" DDR:%-4s MHz (%s MT/s data rate) "
165 strmhz(buf1, sysinfo.freq_ddrbus/2),
166 strmhz(buf2, sysinfo.freq_ddrbus));
169 printf(" DDR:%-4s MHz (%s MT/s data rate) "
171 strmhz(buf1, sysinfo.freq_ddrbus/2),
172 strmhz(buf2, sysinfo.freq_ddrbus));
177 #if defined(CONFIG_FSL_LBC)
178 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
179 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
181 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
182 sysinfo.freq_localbus);
186 #if defined(CONFIG_FSL_IFC)
187 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
191 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
195 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
198 #ifdef CONFIG_SYS_DPAA_FMAN
199 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
200 printf(" FMAN%d: %s MHz\n", i + 1,
201 strmhz(buf1, sysinfo.freq_fman[i]));
205 #ifdef CONFIG_SYS_DPAA_QBMAN
206 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
209 #ifdef CONFIG_SYS_DPAA_PME
210 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
213 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
215 #ifdef CONFIG_FSL_CORENET
216 /* Display the RCW, so that no one gets confused as to what RCW
217 * we're actually using for this boot.
219 puts("Reset Configuration Word (RCW):");
220 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
221 u32 rcw = in_be32(&gur->rcwsr[i]);
224 printf("\n %08x:", i * 4);
225 printf(" %08x", rcw);
234 /* ------------------------------------------------------------------------- */
236 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
238 /* Everything after the first generation of PQ3 parts has RSTCR */
239 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
240 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
241 unsigned long val, msr;
244 * Initiate hard reset in debug control register DBCR0
245 * Make sure MSR[DE] = 1. This only resets the core.
255 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
257 /* Attempt board-specific reset */
260 /* Next try asserting HRESET_REQ */
261 out_be32(&gur->rstcr, 0x2);
270 * Get timebase clock frequency
272 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
273 #define CONFIG_SYS_FSL_TBCLK_DIV 8
275 unsigned long get_tbclk (void)
277 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
279 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
283 #if defined(CONFIG_WATCHDOG)
285 reset_85xx_watchdog(void)
288 * Clear TSR(WIS) bit by writing 1
290 mtspr(SPRN_TSR, TSR_WIS);
296 int re_enable = disable_interrupts();
298 reset_85xx_watchdog();
302 #endif /* CONFIG_WATCHDOG */
305 * Initializes on-chip MMC controllers.
306 * to override, implement board_mmc_init()
308 int cpu_mmc_init(bd_t *bis)
310 #ifdef CONFIG_FSL_ESDHC
311 return fsl_esdhc_mmc_init(bis);
318 * Print out the state of various machine registers.
319 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
320 * parameters for IFC and TLBs
322 void mpc85xx_reginfo(void)
326 #if defined(CONFIG_FSL_LBC)
329 #ifdef CONFIG_FSL_IFC
335 /* Common ddr init for non-corenet fsl 85xx platforms */
336 #ifndef CONFIG_FSL_CORENET
337 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
338 !defined(CONFIG_SYS_INIT_L2_ADDR)
339 phys_size_t initdram(int board_type)
341 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
342 return fsl_ddr_sdram_size();
344 return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
347 #else /* CONFIG_SYS_RAMBOOT */
348 phys_size_t initdram(int board_type)
350 phys_size_t dram_size = 0;
352 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
354 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
359 * Work around to stabilize DDR DLL
361 out_be32(&gur->ddrdllcr, 0x81000000);
362 asm("sync;isync;msync");
364 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
365 setbits_be32(&gur->devdisr, 0x00010000);
366 for (i = 0; i < x; i++)
368 clrbits_be32(&gur->devdisr, 0x00010000);
374 #if defined(CONFIG_SPD_EEPROM) || \
375 defined(CONFIG_DDR_SPD) || \
376 defined(CONFIG_SYS_DDR_RAW_TIMING)
377 dram_size = fsl_ddr_sdram();
379 dram_size = fixed_sdram();
381 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
382 dram_size *= 0x100000;
384 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
386 * Initialize and enable DDR ECC.
388 ddr_enable_ecc(dram_size);
391 #if defined(CONFIG_FSL_LBC)
392 /* Some boards also have sdram on the lbc */
399 #endif /* CONFIG_SYS_RAMBOOT */
402 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
404 /* Board-specific functions defined in each board's ddr.c */
405 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
406 unsigned int ctrl_num);
407 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
410 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
412 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
414 static void dump_spd_ddr_reg(void)
419 struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
421 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
423 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
424 fsl_ddr_get_spd(spd[i], i);
426 puts("SPD data of all dimms (zero vaule is omitted)...\n");
429 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
430 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
431 printf("Dimm%d ", k++);
434 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
436 printf("%3d (0x%02x) ", k, k);
437 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
438 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
439 p_8 = (u8 *) &spd[i][j];
441 printf("0x%02x ", p_8[k]);
453 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
456 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
458 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
460 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
463 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
465 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
468 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
470 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
474 printf("%s unexpected controller number = %u\n",
479 printf("DDR registers dump for all controllers "
480 "(zero vaule is omitted)...\n");
481 puts("Offset (hex) ");
482 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
483 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
485 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
487 printf("%6d (0x%04x)", k * 4, k * 4);
488 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
489 p_32 = (u32 *) ddr[i];
491 printf(" 0x%08x", p_32[k]);
504 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
505 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
507 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
509 u32 tsize, valid, ptr;
512 clear_ddr_tlbs_phys(p_addr, size>>20);
514 /* Setup new tlb to cover the physical address */
515 setup_ddr_tlbs_phys(p_addr, size>>20);
518 ddr_esel = find_tlb_idx((void *)ptr, 1);
519 if (ddr_esel != -1) {
520 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
522 printf("TLB error in function %s\n", __func__);
530 * slide the testing window up to test another area
531 * for 32_bit system, the maximum testable memory is limited to
532 * CONFIG_MAX_MEM_MAPPED
534 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
536 phys_addr_t test_cap, p_addr;
537 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
539 #if !defined(CONFIG_PHYS_64BIT) || \
540 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
541 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
544 test_cap = gd->ram_size;
546 p_addr = (*vstart) + (*size) + (*phys_offset);
547 if (p_addr < test_cap - 1) {
548 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
549 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
551 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
552 *size = (u32) p_size;
553 printf("Testing 0x%08llx - 0x%08llx\n",
554 (u64)(*vstart) + (*phys_offset),
555 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
562 /* initialization for testing area */
563 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
565 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
567 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
568 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
571 #if !defined(CONFIG_PHYS_64BIT) || \
572 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
573 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
574 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
575 puts("Cannot test more than ");
576 print_size(CONFIG_MAX_MEM_MAPPED,
577 " without proper 36BIT support.\n");
580 printf("Testing 0x%08llx - 0x%08llx\n",
581 (u64)(*vstart) + (*phys_offset),
582 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
587 /* invalid TLBs for DDR and remap as normal after testing */
588 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
591 u32 tsize, valid, ptr;
595 /* disable the TLBs for this testing */
598 while (ptr < (*vstart) + (*size)) {
599 ddr_esel = find_tlb_idx((void *)ptr, 1);
600 if (ddr_esel != -1) {
601 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
602 disable_tlb(ddr_esel);
604 ptr += TSIZE_TO_BYTES(tsize);
608 setup_ddr_tlbs(gd->ram_size>>20);
614 void arch_memory_failure_handle(void)