1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2002, 2003 Motorola Inc.
5 * Xianghua Xiao (X.Xiao@motorola.com)
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
18 #include <fsl_esdhc.h>
19 #include <asm/cache.h>
23 #include <asm/fsl_law.h>
24 #include <asm/fsl_lbc.h>
26 #include <asm/processor.h>
27 #include <fsl_ddr_sdram.h>
30 DECLARE_GLOBAL_DATA_PTR;
33 * Default board reset function
40 void board_reset(void) __attribute__((weak, alias("__board_reset")));
49 char buf1[32], buf2[32];
50 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
51 ccsr_gur_t __iomem *gur =
52 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
56 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
57 * mode. Previous platform use ddr ratio to do the same. This
58 * information is only for display here.
60 #ifdef CONFIG_FSL_CORENET
61 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
62 u32 ddr_sync = 0; /* only async mode is supported */
64 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
65 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
66 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
67 #else /* CONFIG_FSL_CORENET */
68 #ifdef CONFIG_DDR_CLK_FREQ
69 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
70 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
73 #endif /* CONFIG_DDR_CLK_FREQ */
74 #endif /* CONFIG_FSL_CORENET */
76 unsigned int i, core, nr_cores = cpu_numcores();
77 u32 mask = cpu_mask();
79 #ifdef CONFIG_HETROGENOUS_CLUSTERS
80 unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
81 u32 dsp_mask = cpu_dsp_mask();
88 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
89 if (SVR_SOC_VER(svr) == SVR_T4080) {
91 (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
93 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
94 FSL_CORENET_DEVDISR2_DTSEC1_9);
95 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
96 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
98 /* It needs SW to disable core4~7 as HW design sake on T4080 */
99 for (i = 4; i < 8; i++)
102 /* request core4~7 into PH20 state, prior to entering PCL10
103 * state, all cores in cluster should be placed in PH20 state.
105 setbits_be32(&rcpm->pcph20setr, 0xf0);
107 /* put the 2nd cluster into PCL10 state */
108 setbits_be32(&rcpm->clpcl10setr, 1 << 1);
112 if (cpu_numcores() > 1) {
114 puts("Unicore software on multiprocessor system!!\n"
115 "To enable mutlticore build define CONFIG_MP\n");
117 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
118 printf("CPU%d: ", pic->whoami);
126 if (IS_E_PROCESSOR(svr))
129 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
133 major = PVR_MAJ(pvr);
134 minor = PVR_MIN(pvr);
138 case PVR_VER_E500_V1:
139 case PVR_VER_E500_V2:
156 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
158 if (nr_cores > CONFIG_MAX_CPUS) {
159 panic("\nUnexpected number of cores: %d, max is %d\n",
160 nr_cores, CONFIG_MAX_CPUS);
163 get_sys_info(&sysinfo);
165 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
166 if (sysinfo.diff_sysclk == 1)
167 puts("Single Source Clock Configuration\n");
170 puts("Clock Configuration:");
171 for_each_cpu(i, core, nr_cores, mask) {
174 printf("CPU%d:%-4s MHz, ", core,
175 strmhz(buf1, sysinfo.freq_processor[core]));
178 #ifdef CONFIG_HETROGENOUS_CLUSTERS
179 for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
182 printf("DSP CPU%d:%-4s MHz, ", j,
183 strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
187 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
190 #ifdef CONFIG_FSL_CORENET
192 printf(" DDR:%-4s MHz (%s MT/s data rate) "
194 strmhz(buf1, sysinfo.freq_ddrbus/2),
195 strmhz(buf2, sysinfo.freq_ddrbus));
197 printf(" DDR:%-4s MHz (%s MT/s data rate) "
199 strmhz(buf1, sysinfo.freq_ddrbus/2),
200 strmhz(buf2, sysinfo.freq_ddrbus));
205 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
206 strmhz(buf1, sysinfo.freq_ddrbus/2),
207 strmhz(buf2, sysinfo.freq_ddrbus));
210 printf(" DDR:%-4s MHz (%s MT/s data rate) "
212 strmhz(buf1, sysinfo.freq_ddrbus/2),
213 strmhz(buf2, sysinfo.freq_ddrbus));
216 printf(" DDR:%-4s MHz (%s MT/s data rate) "
218 strmhz(buf1, sysinfo.freq_ddrbus/2),
219 strmhz(buf2, sysinfo.freq_ddrbus));
224 #if defined(CONFIG_FSL_LBC)
225 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
226 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
228 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
229 sysinfo.freq_localbus);
233 #if defined(CONFIG_FSL_IFC)
234 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
238 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
242 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
245 #if defined(CONFIG_SYS_CPRI)
247 printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
250 #if defined(CONFIG_SYS_MAPLE)
252 printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
253 printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
254 printf("MAPLE-eTVPE:%-4s MHz\n",
255 strmhz(buf1, sysinfo.freq_maple_etvpe));
258 #ifdef CONFIG_SYS_DPAA_FMAN
259 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
260 printf(" FMAN%d: %s MHz\n", i + 1,
261 strmhz(buf1, sysinfo.freq_fman[i]));
265 #ifdef CONFIG_SYS_DPAA_QBMAN
266 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
269 #ifdef CONFIG_SYS_DPAA_PME
270 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
273 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
275 #ifdef CONFIG_FSL_CORENET
276 /* Display the RCW, so that no one gets confused as to what RCW
277 * we're actually using for this boot.
279 puts("Reset Configuration Word (RCW):");
280 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
281 u32 rcw = in_be32(&gur->rcwsr[i]);
284 printf("\n %08x:", i * 4);
285 printf(" %08x", rcw);
294 /* ------------------------------------------------------------------------- */
296 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
298 /* Everything after the first generation of PQ3 parts has RSTCR */
299 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
300 defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
301 unsigned long val, msr;
304 * Initiate hard reset in debug control register DBCR0
305 * Make sure MSR[DE] = 1. This only resets the core.
315 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
317 /* Attempt board-specific reset */
320 /* Next try asserting HRESET_REQ */
321 out_be32(&gur->rstcr, 0x2);
330 * Get timebase clock frequency
332 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
333 #define CONFIG_SYS_FSL_TBCLK_DIV 8
335 __weak unsigned long get_tbclk (void)
337 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
339 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
343 #if defined(CONFIG_WATCHDOG)
344 #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
346 init_85xx_watchdog(void)
348 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
349 TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
353 reset_85xx_watchdog(void)
356 * Clear TSR(WIS) bit by writing 1
358 mtspr(SPRN_TSR, TSR_WIS);
364 int re_enable = disable_interrupts();
366 reset_85xx_watchdog();
370 #endif /* CONFIG_WATCHDOG */
373 * Initializes on-chip MMC controllers.
374 * to override, implement board_mmc_init()
376 int cpu_mmc_init(bd_t *bis)
378 #ifdef CONFIG_FSL_ESDHC
379 return fsl_esdhc_mmc_init(bis);
386 * Print out the state of various machine registers.
387 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
388 * parameters for IFC and TLBs
390 void print_reginfo(void)
394 #if defined(CONFIG_FSL_LBC)
397 #ifdef CONFIG_FSL_IFC
403 /* Common ddr init for non-corenet fsl 85xx platforms */
404 #ifndef CONFIG_FSL_CORENET
405 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
406 !defined(CONFIG_SYS_INIT_L2_ADDR)
409 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
410 defined(CONFIG_ARCH_QEMU_E500)
411 gd->ram_size = fsl_ddr_sdram_size();
413 gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
418 #else /* CONFIG_SYS_RAMBOOT */
421 phys_size_t dram_size = 0;
423 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
425 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
430 * Work around to stabilize DDR DLL
432 out_be32(&gur->ddrdllcr, 0x81000000);
433 asm("sync;isync;msync");
435 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
436 setbits_be32(&gur->devdisr, 0x00010000);
437 for (i = 0; i < x; i++)
439 clrbits_be32(&gur->devdisr, 0x00010000);
445 #if defined(CONFIG_SPD_EEPROM) || \
446 defined(CONFIG_DDR_SPD) || \
447 defined(CONFIG_SYS_DDR_RAW_TIMING)
448 dram_size = fsl_ddr_sdram();
450 dram_size = fixed_sdram();
452 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
453 dram_size *= 0x100000;
455 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
457 * Initialize and enable DDR ECC.
459 ddr_enable_ecc(dram_size);
462 #if defined(CONFIG_FSL_LBC)
463 /* Some boards also have sdram on the lbc */
468 gd->ram_size = dram_size;
472 #endif /* CONFIG_SYS_RAMBOOT */
475 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
477 /* Board-specific functions defined in each board's ddr.c */
478 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
479 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
480 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
483 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
485 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
487 static void dump_spd_ddr_reg(void)
492 struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
494 spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
496 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
497 fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
499 puts("SPD data of all dimms (zero value is omitted)...\n");
502 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
503 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
504 printf("Dimm%d ", k++);
507 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
509 printf("%3d (0x%02x) ", k, k);
510 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
511 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
512 p_8 = (u8 *) &spd[i][j];
514 printf("0x%02x ", p_8[k]);
526 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
529 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
531 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
533 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
536 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
538 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
541 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
543 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
547 printf("%s unexpected controller number = %u\n",
552 printf("DDR registers dump for all controllers "
553 "(zero value is omitted)...\n");
554 puts("Offset (hex) ");
555 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
556 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
558 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
560 printf("%6d (0x%04x)", k * 4, k * 4);
561 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
562 p_32 = (u32 *) ddr[i];
564 printf(" 0x%08x", p_32[k]);
577 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
578 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
580 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
582 u32 tsize, valid, ptr;
585 clear_ddr_tlbs_phys(p_addr, size>>20);
587 /* Setup new tlb to cover the physical address */
588 setup_ddr_tlbs_phys(p_addr, size>>20);
591 ddr_esel = find_tlb_idx((void *)ptr, 1);
592 if (ddr_esel != -1) {
593 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
595 printf("TLB error in function %s\n", __func__);
603 * slide the testing window up to test another area
604 * for 32_bit system, the maximum testable memory is limited to
605 * CONFIG_MAX_MEM_MAPPED
607 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
609 phys_addr_t test_cap, p_addr;
610 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
612 #if !defined(CONFIG_PHYS_64BIT) || \
613 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
614 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
617 test_cap = gd->ram_size;
619 p_addr = (*vstart) + (*size) + (*phys_offset);
620 if (p_addr < test_cap - 1) {
621 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
622 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
624 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
625 *size = (u32) p_size;
626 printf("Testing 0x%08llx - 0x%08llx\n",
627 (u64)(*vstart) + (*phys_offset),
628 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
635 /* initialization for testing area */
636 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
638 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
640 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
641 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
644 #if !defined(CONFIG_PHYS_64BIT) || \
645 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
646 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
647 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
648 puts("Cannot test more than ");
649 print_size(CONFIG_MAX_MEM_MAPPED,
650 " without proper 36BIT support.\n");
653 printf("Testing 0x%08llx - 0x%08llx\n",
654 (u64)(*vstart) + (*phys_offset),
655 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
660 /* invalid TLBs for DDR and remap as normal after testing */
661 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
664 u32 tsize, valid, ptr;
668 /* disable the TLBs for this testing */
671 while (ptr < (*vstart) + (*size)) {
672 ddr_esel = find_tlb_idx((void *)ptr, 1);
673 if (ddr_esel != -1) {
674 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
675 disable_tlb(ddr_esel);
677 ptr += TSIZE_TO_BYTES(tsize);
681 setup_ddr_tlbs(gd->ram_size>>20);
687 void arch_memory_failure_handle(void)