2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/immap_85xx.h>
11 #include <asm/fsl_serdes.h>
13 #define SRDS1_MAX_LANES 4
15 static u32 serdes1_prtcl_map;
17 struct serdes_config {
19 u8 lanes[SRDS1_MAX_LANES];
22 static const struct serdes_config serdes1_cfg_tbl[] = {
24 {1, {PCIE1, PCIE1, PCIE1, PCIE1} },
25 {2, {PCIE1, PCIE1, PCIE1, PCIE1} },
26 {3, {PCIE1, PCIE1, NONE, NONE} },
27 {4, {PCIE1, PCIE1, NONE, NONE} },
28 {5, {PCIE1, NONE, NONE, NONE} },
29 {6, {PCIE1, NONE, NONE, NONE} },
33 int is_serdes_configured(enum srds_prtcl device)
35 return (1 << device) & serdes1_prtcl_map;
38 void fsl_serdes_init(void)
40 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
41 u32 pordevsr = in_be32(&gur->pordevsr);
42 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
43 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
44 const struct serdes_config *ptr;
47 debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
49 if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
50 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
54 ptr = &serdes1_cfg_tbl[srds_cfg];
58 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
59 enum srds_prtcl lane_prtcl = ptr->lanes[lane];
60 serdes1_prtcl_map |= (1 << lane_prtcl);