12 bool "Support sbc8548"
15 config TARGET_SOCRATES
16 bool "Support socrates"
19 config TARGET_B4420QDS
20 bool "Support B4420QDS"
25 config TARGET_B4860QDS
26 bool "Support B4860QDS"
28 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 config TARGET_BSC9131RDB
33 bool "Support BSC9131RDB"
36 select BOARD_EARLY_INIT_F
38 config TARGET_BSC9132QDS
39 bool "Support BSC9132QDS"
41 select BOARD_LATE_INIT if CHAIN_OF_TRUST
43 select BOARD_EARLY_INIT_F
45 config TARGET_C29XPCIE
46 bool "Support C29XPCIE"
48 select BOARD_LATE_INIT if CHAIN_OF_TRUST
54 bool "Support P3041DS"
57 select BOARD_LATE_INIT if CHAIN_OF_TRUST
60 bool "Support P4080DS"
63 select BOARD_LATE_INIT if CHAIN_OF_TRUST
66 bool "Support P5020DS"
69 select BOARD_LATE_INIT if CHAIN_OF_TRUST
72 bool "Support P5040DS"
75 select BOARD_LATE_INIT if CHAIN_OF_TRUST
77 config TARGET_MPC8536DS
78 bool "Support MPC8536DS"
80 # Use DDR3 controller with DDR2 DIMMs on this board
81 select SYS_FSL_DDRC_GEN3
83 config TARGET_MPC8540ADS
84 bool "Support MPC8540ADS"
87 config TARGET_MPC8541CDS
88 bool "Support MPC8541CDS"
91 config TARGET_MPC8544DS
92 bool "Support MPC8544DS"
95 config TARGET_MPC8548CDS
96 bool "Support MPC8548CDS"
99 config TARGET_MPC8555CDS
100 bool "Support MPC8555CDS"
103 config TARGET_MPC8560ADS
104 bool "Support MPC8560ADS"
107 config TARGET_MPC8568MDS
108 bool "Support MPC8568MDS"
111 config TARGET_MPC8569MDS
112 bool "Support MPC8569MDS"
115 config TARGET_MPC8572DS
116 bool "Support MPC8572DS"
118 # Use DDR3 controller with DDR2 DIMMs on this board
119 select SYS_FSL_DDRC_GEN3
121 config TARGET_P1010RDB_PA
122 bool "Support P1010RDB_PA"
124 select BOARD_LATE_INIT if CHAIN_OF_TRUST
128 config TARGET_P1010RDB_PB
129 bool "Support P1010RDB_PB"
131 select BOARD_LATE_INIT if CHAIN_OF_TRUST
135 config TARGET_P1022DS
136 bool "Support P1022DS"
141 config TARGET_P1023RDB
142 bool "Support P1023RDB"
145 config TARGET_P1020MBG
146 bool "Support P1020MBG-PC"
151 config TARGET_P1020RDB_PC
152 bool "Support P1020RDB-PC"
157 config TARGET_P1020RDB_PD
158 bool "Support P1020RDB-PD"
163 config TARGET_P1020UTM
164 bool "Support P1020UTM"
169 config TARGET_P1021RDB
170 bool "Support P1021RDB"
175 config TARGET_P1024RDB
176 bool "Support P1024RDB"
181 config TARGET_P1025RDB
182 bool "Support P1025RDB"
187 config TARGET_P2020RDB
188 bool "Support P2020RDB-PC"
194 bool "Support p1_twr"
197 config TARGET_P2041RDB
198 bool "Support P2041RDB"
200 select BOARD_LATE_INIT if CHAIN_OF_TRUST
203 config TARGET_QEMU_PPCE500
204 bool "Support qemu-ppce500"
205 select ARCH_QEMU_E500
208 config TARGET_T1024QDS
209 bool "Support T1024QDS"
211 select BOARD_LATE_INIT if CHAIN_OF_TRUST
215 config TARGET_T1023RDB
216 bool "Support T1023RDB"
218 select BOARD_LATE_INIT if CHAIN_OF_TRUST
222 config TARGET_T1024RDB
223 bool "Support T1024RDB"
225 select BOARD_LATE_INIT if CHAIN_OF_TRUST
229 config TARGET_T1040QDS
230 bool "Support T1040QDS"
232 select BOARD_LATE_INIT if CHAIN_OF_TRUST
235 config TARGET_T1040RDB
236 bool "Support T1040RDB"
238 select BOARD_LATE_INIT if CHAIN_OF_TRUST
242 config TARGET_T1040D4RDB
243 bool "Support T1040D4RDB"
245 select BOARD_LATE_INIT if CHAIN_OF_TRUST
249 config TARGET_T1042RDB
250 bool "Support T1042RDB"
252 select BOARD_LATE_INIT if CHAIN_OF_TRUST
256 config TARGET_T1042D4RDB
257 bool "Support T1042D4RDB"
259 select BOARD_LATE_INIT if CHAIN_OF_TRUST
263 config TARGET_T1042RDB_PI
264 bool "Support T1042RDB_PI"
266 select BOARD_LATE_INIT if CHAIN_OF_TRUST
270 config TARGET_T2080QDS
271 bool "Support T2080QDS"
273 select BOARD_LATE_INIT if CHAIN_OF_TRUST
277 config TARGET_T2080RDB
278 bool "Support T2080RDB"
280 select BOARD_LATE_INIT if CHAIN_OF_TRUST
284 config TARGET_T2081QDS
285 bool "Support T2081QDS"
290 config TARGET_T4160QDS
291 bool "Support T4160QDS"
293 select BOARD_LATE_INIT if CHAIN_OF_TRUST
297 config TARGET_T4160RDB
298 bool "Support T4160RDB"
303 config TARGET_T4240QDS
304 bool "Support T4240QDS"
306 select BOARD_LATE_INIT if CHAIN_OF_TRUST
310 config TARGET_T4240RDB
311 bool "Support T4240RDB"
316 config TARGET_CONTROLCENTERD
317 bool "Support controlcenterd"
320 config TARGET_KMP204X
321 bool "Support kmp204x"
325 config TARGET_XPEDITE520X
326 bool "Support xpedite520x"
329 config TARGET_XPEDITE537X
330 bool "Support xpedite537x"
332 # Use DDR3 controller with DDR2 DIMMs on this board
333 select SYS_FSL_DDRC_GEN3
335 config TARGET_XPEDITE550X
336 bool "Support xpedite550x"
339 config TARGET_UCP1020
340 bool "Support uCP1020"
343 config TARGET_CYRUS_P5020
344 bool "Support Varisys Cyrus P5020"
348 config TARGET_CYRUS_P5040
349 bool "Support Varisys Cyrus P5040"
360 select SYS_FSL_DDR_VER_47
361 select SYS_FSL_ERRATUM_A004477
362 select SYS_FSL_ERRATUM_A005871
363 select SYS_FSL_ERRATUM_A006379
364 select SYS_FSL_ERRATUM_A006384
365 select SYS_FSL_ERRATUM_A006475
366 select SYS_FSL_ERRATUM_A006593
367 select SYS_FSL_ERRATUM_A007075
368 select SYS_FSL_ERRATUM_A007186
369 select SYS_FSL_ERRATUM_A007212
370 select SYS_FSL_ERRATUM_A009942
371 select SYS_FSL_HAS_DDR3
372 select SYS_FSL_HAS_SEC
373 select SYS_FSL_QORIQ_CHASSIS2
374 select SYS_FSL_SEC_BE
375 select SYS_FSL_SEC_COMPAT_4
383 select SYS_FSL_DDR_VER_47
384 select SYS_FSL_ERRATUM_A004477
385 select SYS_FSL_ERRATUM_A005871
386 select SYS_FSL_ERRATUM_A006379
387 select SYS_FSL_ERRATUM_A006384
388 select SYS_FSL_ERRATUM_A006475
389 select SYS_FSL_ERRATUM_A006593
390 select SYS_FSL_ERRATUM_A007075
391 select SYS_FSL_ERRATUM_A007186
392 select SYS_FSL_ERRATUM_A007212
393 select SYS_FSL_ERRATUM_A009942
394 select SYS_FSL_HAS_DDR3
395 select SYS_FSL_HAS_SEC
396 select SYS_FSL_QORIQ_CHASSIS2
397 select SYS_FSL_SEC_BE
398 select SYS_FSL_SEC_COMPAT_4
404 select SYS_FSL_DDR_VER_44
405 select SYS_FSL_ERRATUM_A004477
406 select SYS_FSL_ERRATUM_A005125
407 select SYS_FSL_ERRATUM_ESDHC111
408 select SYS_FSL_HAS_DDR3
409 select SYS_FSL_HAS_SEC
410 select SYS_FSL_SEC_BE
411 select SYS_FSL_SEC_COMPAT_4
416 select SYS_FSL_DDR_VER_46
417 select SYS_FSL_ERRATUM_A004477
418 select SYS_FSL_ERRATUM_A005125
419 select SYS_FSL_ERRATUM_A005434
420 select SYS_FSL_ERRATUM_ESDHC111
421 select SYS_FSL_ERRATUM_I2C_A004447
422 select SYS_FSL_ERRATUM_IFC_A002769
423 select SYS_FSL_HAS_DDR3
424 select SYS_FSL_HAS_SEC
425 select SYS_FSL_SEC_BE
426 select SYS_FSL_SEC_COMPAT_4
427 select SYS_PPC_E500_USE_DEBUG_TLB
432 select SYS_FSL_DDR_VER_46
433 select SYS_FSL_ERRATUM_A005125
434 select SYS_FSL_ERRATUM_ESDHC111
435 select SYS_FSL_HAS_DDR3
436 select SYS_FSL_HAS_SEC
437 select SYS_FSL_SEC_BE
438 select SYS_FSL_SEC_COMPAT_6
439 select SYS_PPC_E500_USE_DEBUG_TLB
444 select SYS_FSL_ERRATUM_A004508
445 select SYS_FSL_ERRATUM_A005125
446 select SYS_FSL_HAS_DDR2
447 select SYS_FSL_HAS_DDR3
448 select SYS_FSL_HAS_SEC
449 select SYS_FSL_SEC_BE
450 select SYS_FSL_SEC_COMPAT_2
451 select SYS_PPC_E500_USE_DEBUG_TLB
456 select SYS_FSL_HAS_DDR1
461 select SYS_FSL_HAS_DDR1
462 select SYS_FSL_HAS_SEC
463 select SYS_FSL_SEC_BE
464 select SYS_FSL_SEC_COMPAT_2
469 select SYS_FSL_ERRATUM_A005125
470 select SYS_FSL_HAS_DDR2
471 select SYS_FSL_HAS_SEC
472 select SYS_FSL_SEC_BE
473 select SYS_FSL_SEC_COMPAT_2
474 select SYS_PPC_E500_USE_DEBUG_TLB
479 select SYS_FSL_ERRATUM_A005125
480 select SYS_FSL_ERRATUM_NMG_DDR120
481 select SYS_FSL_ERRATUM_NMG_LBC103
482 select SYS_FSL_ERRATUM_NMG_ETSEC129
483 select SYS_FSL_ERRATUM_I2C_A004447
484 select SYS_FSL_HAS_DDR2
485 select SYS_FSL_HAS_DDR1
486 select SYS_FSL_HAS_SEC
487 select SYS_FSL_SEC_BE
488 select SYS_FSL_SEC_COMPAT_2
489 select SYS_PPC_E500_USE_DEBUG_TLB
494 select SYS_FSL_HAS_DDR1
495 select SYS_FSL_HAS_SEC
496 select SYS_FSL_SEC_BE
497 select SYS_FSL_SEC_COMPAT_2
502 select SYS_FSL_HAS_DDR1
507 select SYS_FSL_HAS_DDR2
508 select SYS_FSL_HAS_SEC
509 select SYS_FSL_SEC_BE
510 select SYS_FSL_SEC_COMPAT_2
515 select SYS_FSL_ERRATUM_A004508
516 select SYS_FSL_ERRATUM_A005125
517 select SYS_FSL_HAS_DDR3
518 select SYS_FSL_HAS_SEC
519 select SYS_FSL_SEC_BE
520 select SYS_FSL_SEC_COMPAT_2
525 select SYS_FSL_ERRATUM_A004508
526 select SYS_FSL_ERRATUM_A005125
527 select SYS_FSL_ERRATUM_DDR_115
528 select SYS_FSL_ERRATUM_DDR111_DDR134
529 select SYS_FSL_HAS_DDR2
530 select SYS_FSL_HAS_DDR3
531 select SYS_FSL_HAS_SEC
532 select SYS_FSL_SEC_BE
533 select SYS_FSL_SEC_COMPAT_2
534 select SYS_PPC_E500_USE_DEBUG_TLB
539 select SYS_FSL_ERRATUM_A004477
540 select SYS_FSL_ERRATUM_A004508
541 select SYS_FSL_ERRATUM_A005125
542 select SYS_FSL_ERRATUM_A006261
543 select SYS_FSL_ERRATUM_A007075
544 select SYS_FSL_ERRATUM_ESDHC111
545 select SYS_FSL_ERRATUM_I2C_A004447
546 select SYS_FSL_ERRATUM_IFC_A002769
547 select SYS_FSL_ERRATUM_P1010_A003549
548 select SYS_FSL_ERRATUM_SEC_A003571
549 select SYS_FSL_ERRATUM_IFC_A003399
550 select SYS_FSL_HAS_DDR3
551 select SYS_FSL_HAS_SEC
552 select SYS_FSL_SEC_BE
553 select SYS_FSL_SEC_COMPAT_4
554 select SYS_PPC_E500_USE_DEBUG_TLB
559 select SYS_FSL_ERRATUM_A004508
560 select SYS_FSL_ERRATUM_A005125
561 select SYS_FSL_ERRATUM_ELBC_A001
562 select SYS_FSL_ERRATUM_ESDHC111
563 select SYS_FSL_HAS_DDR3
564 select SYS_FSL_HAS_SEC
565 select SYS_FSL_SEC_BE
566 select SYS_FSL_SEC_COMPAT_2
567 select SYS_PPC_E500_USE_DEBUG_TLB
572 select SYS_FSL_ERRATUM_A004508
573 select SYS_FSL_ERRATUM_A005125
574 select SYS_FSL_ERRATUM_ELBC_A001
575 select SYS_FSL_ERRATUM_ESDHC111
576 select SYS_FSL_HAS_DDR3
577 select SYS_FSL_HAS_SEC
578 select SYS_FSL_SEC_BE
579 select SYS_FSL_SEC_COMPAT_2
580 select SYS_PPC_E500_USE_DEBUG_TLB
585 select SYS_FSL_ERRATUM_A004508
586 select SYS_FSL_ERRATUM_A005125
587 select SYS_FSL_ERRATUM_ELBC_A001
588 select SYS_FSL_ERRATUM_ESDHC111
589 select SYS_FSL_HAS_DDR3
590 select SYS_FSL_HAS_SEC
591 select SYS_FSL_SEC_BE
592 select SYS_FSL_SEC_COMPAT_2
593 select SYS_PPC_E500_USE_DEBUG_TLB
598 select SYS_FSL_ERRATUM_A004477
599 select SYS_FSL_ERRATUM_A004508
600 select SYS_FSL_ERRATUM_A005125
601 select SYS_FSL_ERRATUM_ELBC_A001
602 select SYS_FSL_ERRATUM_ESDHC111
603 select SYS_FSL_ERRATUM_SATA_A001
604 select SYS_FSL_HAS_DDR3
605 select SYS_FSL_HAS_SEC
606 select SYS_FSL_SEC_BE
607 select SYS_FSL_SEC_COMPAT_2
608 select SYS_PPC_E500_USE_DEBUG_TLB
613 select SYS_FSL_ERRATUM_A004508
614 select SYS_FSL_ERRATUM_A005125
615 select SYS_FSL_ERRATUM_I2C_A004447
616 select SYS_FSL_HAS_DDR3
617 select SYS_FSL_HAS_SEC
618 select SYS_FSL_SEC_BE
619 select SYS_FSL_SEC_COMPAT_4
624 select SYS_FSL_ERRATUM_A004508
625 select SYS_FSL_ERRATUM_A005125
626 select SYS_FSL_ERRATUM_ELBC_A001
627 select SYS_FSL_ERRATUM_ESDHC111
628 select SYS_FSL_HAS_DDR3
629 select SYS_FSL_HAS_SEC
630 select SYS_FSL_SEC_BE
631 select SYS_FSL_SEC_COMPAT_2
632 select SYS_PPC_E500_USE_DEBUG_TLB
637 select SYS_FSL_ERRATUM_A004508
638 select SYS_FSL_ERRATUM_A005125
639 select SYS_FSL_ERRATUM_ELBC_A001
640 select SYS_FSL_ERRATUM_ESDHC111
641 select SYS_FSL_HAS_DDR3
642 select SYS_FSL_HAS_SEC
643 select SYS_FSL_SEC_BE
644 select SYS_FSL_SEC_COMPAT_2
645 select SYS_PPC_E500_USE_DEBUG_TLB
650 select SYS_FSL_ERRATUM_A004477
651 select SYS_FSL_ERRATUM_A004508
652 select SYS_FSL_ERRATUM_A005125
653 select SYS_FSL_ERRATUM_ESDHC111
654 select SYS_FSL_ERRATUM_ESDHC_A001
655 select SYS_FSL_HAS_DDR3
656 select SYS_FSL_HAS_SEC
657 select SYS_FSL_SEC_BE
658 select SYS_FSL_SEC_COMPAT_2
659 select SYS_PPC_E500_USE_DEBUG_TLB
665 select SYS_FSL_ERRATUM_A004510
666 select SYS_FSL_ERRATUM_A004849
667 select SYS_FSL_ERRATUM_A006261
668 select SYS_FSL_ERRATUM_CPU_A003999
669 select SYS_FSL_ERRATUM_DDR_A003
670 select SYS_FSL_ERRATUM_DDR_A003474
671 select SYS_FSL_ERRATUM_ESDHC111
672 select SYS_FSL_ERRATUM_I2C_A004447
673 select SYS_FSL_ERRATUM_NMG_CPU_A011
674 select SYS_FSL_ERRATUM_SRIO_A004034
675 select SYS_FSL_ERRATUM_USB14
676 select SYS_FSL_HAS_DDR3
677 select SYS_FSL_HAS_SEC
678 select SYS_FSL_QORIQ_CHASSIS1
679 select SYS_FSL_SEC_BE
680 select SYS_FSL_SEC_COMPAT_4
686 select SYS_FSL_DDR_VER_44
687 select SYS_FSL_ERRATUM_A004510
688 select SYS_FSL_ERRATUM_A004849
689 select SYS_FSL_ERRATUM_A005812
690 select SYS_FSL_ERRATUM_A006261
691 select SYS_FSL_ERRATUM_CPU_A003999
692 select SYS_FSL_ERRATUM_DDR_A003
693 select SYS_FSL_ERRATUM_DDR_A003474
694 select SYS_FSL_ERRATUM_ESDHC111
695 select SYS_FSL_ERRATUM_I2C_A004447
696 select SYS_FSL_ERRATUM_NMG_CPU_A011
697 select SYS_FSL_ERRATUM_SRIO_A004034
698 select SYS_FSL_ERRATUM_USB14
699 select SYS_FSL_HAS_DDR3
700 select SYS_FSL_HAS_SEC
701 select SYS_FSL_QORIQ_CHASSIS1
702 select SYS_FSL_SEC_BE
703 select SYS_FSL_SEC_COMPAT_4
709 select SYS_FSL_DDR_VER_44
710 select SYS_FSL_ERRATUM_A004510
711 select SYS_FSL_ERRATUM_A004580
712 select SYS_FSL_ERRATUM_A004849
713 select SYS_FSL_ERRATUM_A005812
714 select SYS_FSL_ERRATUM_A007075
715 select SYS_FSL_ERRATUM_CPC_A002
716 select SYS_FSL_ERRATUM_CPC_A003
717 select SYS_FSL_ERRATUM_CPU_A003999
718 select SYS_FSL_ERRATUM_DDR_A003
719 select SYS_FSL_ERRATUM_DDR_A003474
720 select SYS_FSL_ERRATUM_ELBC_A001
721 select SYS_FSL_ERRATUM_ESDHC111
722 select SYS_FSL_ERRATUM_ESDHC13
723 select SYS_FSL_ERRATUM_ESDHC135
724 select SYS_FSL_ERRATUM_I2C_A004447
725 select SYS_FSL_ERRATUM_NMG_CPU_A011
726 select SYS_FSL_ERRATUM_SRIO_A004034
727 select SYS_P4080_ERRATUM_CPU22
728 select SYS_P4080_ERRATUM_PCIE_A003
729 select SYS_P4080_ERRATUM_SERDES8
730 select SYS_P4080_ERRATUM_SERDES9
731 select SYS_P4080_ERRATUM_SERDES_A001
732 select SYS_P4080_ERRATUM_SERDES_A005
733 select SYS_FSL_HAS_DDR3
734 select SYS_FSL_HAS_SEC
735 select SYS_FSL_QORIQ_CHASSIS1
736 select SYS_FSL_SEC_BE
737 select SYS_FSL_SEC_COMPAT_4
743 select SYS_FSL_DDR_VER_44
744 select SYS_FSL_ERRATUM_A004510
745 select SYS_FSL_ERRATUM_A006261
746 select SYS_FSL_ERRATUM_DDR_A003
747 select SYS_FSL_ERRATUM_DDR_A003474
748 select SYS_FSL_ERRATUM_ESDHC111
749 select SYS_FSL_ERRATUM_I2C_A004447
750 select SYS_FSL_ERRATUM_SRIO_A004034
751 select SYS_FSL_ERRATUM_USB14
752 select SYS_FSL_HAS_DDR3
753 select SYS_FSL_HAS_SEC
754 select SYS_FSL_QORIQ_CHASSIS1
755 select SYS_FSL_SEC_BE
756 select SYS_FSL_SEC_COMPAT_4
763 select SYS_FSL_DDR_VER_44
764 select SYS_FSL_ERRATUM_A004510
765 select SYS_FSL_ERRATUM_A004699
766 select SYS_FSL_ERRATUM_A005812
767 select SYS_FSL_ERRATUM_A006261
768 select SYS_FSL_ERRATUM_DDR_A003
769 select SYS_FSL_ERRATUM_DDR_A003474
770 select SYS_FSL_ERRATUM_ESDHC111
771 select SYS_FSL_ERRATUM_USB14
772 select SYS_FSL_HAS_DDR3
773 select SYS_FSL_HAS_SEC
774 select SYS_FSL_QORIQ_CHASSIS1
775 select SYS_FSL_SEC_BE
776 select SYS_FSL_SEC_COMPAT_4
779 config ARCH_QEMU_E500
786 select SYS_FSL_DDR_VER_50
787 select SYS_FSL_ERRATUM_A008378
788 select SYS_FSL_ERRATUM_A009663
789 select SYS_FSL_ERRATUM_A009942
790 select SYS_FSL_ERRATUM_ESDHC111
791 select SYS_FSL_HAS_DDR3
792 select SYS_FSL_HAS_DDR4
793 select SYS_FSL_HAS_SEC
794 select SYS_FSL_QORIQ_CHASSIS2
795 select SYS_FSL_SEC_BE
796 select SYS_FSL_SEC_COMPAT_5
802 select SYS_FSL_DDR_VER_50
803 select SYS_FSL_ERRATUM_A008378
804 select SYS_FSL_ERRATUM_A009663
805 select SYS_FSL_ERRATUM_A009942
806 select SYS_FSL_ERRATUM_ESDHC111
807 select SYS_FSL_HAS_DDR3
808 select SYS_FSL_HAS_DDR4
809 select SYS_FSL_HAS_SEC
810 select SYS_FSL_QORIQ_CHASSIS2
811 select SYS_FSL_SEC_BE
812 select SYS_FSL_SEC_COMPAT_5
818 select SYS_FSL_DDR_VER_50
819 select SYS_FSL_ERRATUM_A008044
820 select SYS_FSL_ERRATUM_A008378
821 select SYS_FSL_ERRATUM_A009663
822 select SYS_FSL_ERRATUM_A009942
823 select SYS_FSL_ERRATUM_ESDHC111
824 select SYS_FSL_HAS_DDR3
825 select SYS_FSL_HAS_DDR4
826 select SYS_FSL_HAS_SEC
827 select SYS_FSL_QORIQ_CHASSIS2
828 select SYS_FSL_SEC_BE
829 select SYS_FSL_SEC_COMPAT_5
835 select SYS_FSL_DDR_VER_50
836 select SYS_FSL_ERRATUM_A008044
837 select SYS_FSL_ERRATUM_A008378
838 select SYS_FSL_ERRATUM_A009663
839 select SYS_FSL_ERRATUM_A009942
840 select SYS_FSL_ERRATUM_ESDHC111
841 select SYS_FSL_HAS_DDR3
842 select SYS_FSL_HAS_DDR4
843 select SYS_FSL_HAS_SEC
844 select SYS_FSL_QORIQ_CHASSIS2
845 select SYS_FSL_SEC_BE
846 select SYS_FSL_SEC_COMPAT_5
853 select SYS_FSL_DDR_VER_47
854 select SYS_FSL_ERRATUM_A006379
855 select SYS_FSL_ERRATUM_A006593
856 select SYS_FSL_ERRATUM_A007186
857 select SYS_FSL_ERRATUM_A007212
858 select SYS_FSL_ERRATUM_A009942
859 select SYS_FSL_ERRATUM_ESDHC111
860 select SYS_FSL_HAS_DDR3
861 select SYS_FSL_HAS_SEC
862 select SYS_FSL_QORIQ_CHASSIS2
863 select SYS_FSL_SEC_BE
864 select SYS_FSL_SEC_COMPAT_4
872 select SYS_FSL_DDR_VER_47
873 select SYS_FSL_ERRATUM_A006379
874 select SYS_FSL_ERRATUM_A006593
875 select SYS_FSL_ERRATUM_A007186
876 select SYS_FSL_ERRATUM_A007212
877 select SYS_FSL_ERRATUM_A009942
878 select SYS_FSL_ERRATUM_ESDHC111
879 select SYS_FSL_HAS_DDR3
880 select SYS_FSL_HAS_SEC
881 select SYS_FSL_QORIQ_CHASSIS2
882 select SYS_FSL_SEC_BE
883 select SYS_FSL_SEC_COMPAT_4
891 select SYS_FSL_DDR_VER_47
892 select SYS_FSL_ERRATUM_A004468
893 select SYS_FSL_ERRATUM_A005871
894 select SYS_FSL_ERRATUM_A006379
895 select SYS_FSL_ERRATUM_A006593
896 select SYS_FSL_ERRATUM_A007186
897 select SYS_FSL_ERRATUM_A007798
898 select SYS_FSL_ERRATUM_A009942
899 select SYS_FSL_HAS_DDR3
900 select SYS_FSL_HAS_SEC
901 select SYS_FSL_QORIQ_CHASSIS2
902 select SYS_FSL_SEC_BE
903 select SYS_FSL_SEC_COMPAT_4
911 select SYS_FSL_DDR_VER_47
912 select SYS_FSL_ERRATUM_A004468
913 select SYS_FSL_ERRATUM_A005871
914 select SYS_FSL_ERRATUM_A006261
915 select SYS_FSL_ERRATUM_A006379
916 select SYS_FSL_ERRATUM_A006593
917 select SYS_FSL_ERRATUM_A007186
918 select SYS_FSL_ERRATUM_A007798
919 select SYS_FSL_ERRATUM_A009942
920 select SYS_FSL_HAS_DDR3
921 select SYS_FSL_HAS_SEC
922 select SYS_FSL_QORIQ_CHASSIS2
923 select SYS_FSL_SEC_BE
924 select SYS_FSL_SEC_COMPAT_4
935 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
940 Enble PowerPC E500MC core
945 Enable PowerPC E6500 core
950 Use Freescale common code for Local Access Window
955 Enable Freescale Secure Boot feature. Normally selected
956 by defconfig. If unsure, do not change.
959 int "Maximum number of CPUs permitted for MPC85xx"
960 default 12 if ARCH_T4240
961 default 8 if ARCH_P4080 || \
963 default 4 if ARCH_B4860 || \
971 default 2 if ARCH_B4420 || \
986 Set this number to the maximum number of possible CPUs in the SoC.
987 SoCs may have multiple clusters with each cluster may have multiple
988 ports. If some ports are reserved but higher ports are used for
989 cores, count the reserved ports. This will allocate enough memory
990 in spin table to properly handle all cores.
992 config SYS_CCSRBAR_DEFAULT
993 hex "Default CCSRBAR address"
994 default 0xff700000 if ARCH_BSC9131 || \
1015 default 0xff600000 if ARCH_P1023
1016 default 0xfe000000 if ARCH_B4420 || \
1031 default 0xe0000000 if ARCH_QEMU_E500
1033 Default value of CCSRBAR comes from power-on-reset. It
1034 is fixed on each SoC. Some SoCs can have different value
1035 if changed by pre-boot regime. The value here must match
1036 the current value in SoC. If not sure, do not change.
1038 config SYS_FSL_ERRATUM_A004468
1041 config SYS_FSL_ERRATUM_A004477
1044 config SYS_FSL_ERRATUM_A004508
1047 config SYS_FSL_ERRATUM_A004580
1050 config SYS_FSL_ERRATUM_A004699
1053 config SYS_FSL_ERRATUM_A004849
1056 config SYS_FSL_ERRATUM_A004510
1059 config SYS_FSL_ERRATUM_A004510_SVR_REV
1061 depends on SYS_FSL_ERRATUM_A004510
1062 default 0x20 if ARCH_P4080
1065 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1067 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1070 config SYS_FSL_ERRATUM_A005125
1073 config SYS_FSL_ERRATUM_A005434
1076 config SYS_FSL_ERRATUM_A005812
1079 config SYS_FSL_ERRATUM_A005871
1082 config SYS_FSL_ERRATUM_A006261
1085 config SYS_FSL_ERRATUM_A006379
1088 config SYS_FSL_ERRATUM_A006384
1091 config SYS_FSL_ERRATUM_A006475
1094 config SYS_FSL_ERRATUM_A006593
1097 config SYS_FSL_ERRATUM_A007075
1100 config SYS_FSL_ERRATUM_A007186
1103 config SYS_FSL_ERRATUM_A007212
1106 config SYS_FSL_ERRATUM_A007798
1109 config SYS_FSL_ERRATUM_A008044
1112 config SYS_FSL_ERRATUM_CPC_A002
1115 config SYS_FSL_ERRATUM_CPC_A003
1118 config SYS_FSL_ERRATUM_CPU_A003999
1121 config SYS_FSL_ERRATUM_ELBC_A001
1124 config SYS_FSL_ERRATUM_I2C_A004447
1127 config SYS_FSL_A004447_SVR_REV
1129 depends on SYS_FSL_ERRATUM_I2C_A004447
1130 default 0x00 if ARCH_MPC8548
1131 default 0x10 if ARCH_P1010
1132 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1133 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1135 config SYS_FSL_ERRATUM_IFC_A002769
1138 config SYS_FSL_ERRATUM_IFC_A003399
1141 config SYS_FSL_ERRATUM_NMG_CPU_A011
1144 config SYS_FSL_ERRATUM_NMG_ETSEC129
1147 config SYS_FSL_ERRATUM_NMG_LBC103
1150 config SYS_FSL_ERRATUM_P1010_A003549
1153 config SYS_FSL_ERRATUM_SATA_A001
1156 config SYS_FSL_ERRATUM_SEC_A003571
1159 config SYS_FSL_ERRATUM_SRIO_A004034
1162 config SYS_FSL_ERRATUM_USB14
1165 config SYS_P4080_ERRATUM_CPU22
1168 config SYS_P4080_ERRATUM_PCIE_A003
1171 config SYS_P4080_ERRATUM_SERDES8
1174 config SYS_P4080_ERRATUM_SERDES9
1177 config SYS_P4080_ERRATUM_SERDES_A001
1180 config SYS_P4080_ERRATUM_SERDES_A005
1183 config SYS_FSL_QORIQ_CHASSIS1
1186 config SYS_FSL_QORIQ_CHASSIS2
1189 config SYS_FSL_NUM_LAWS
1190 int "Number of local access windows"
1192 default 32 if ARCH_B4420 || \
1203 default 16 if ARCH_T1023 || \
1207 default 12 if ARCH_BSC9131 || \
1221 default 10 if ARCH_MPC8544 || \
1225 default 8 if ARCH_MPC8540 || \
1230 Number of local access windows. This is fixed per SoC.
1231 If not sure, do not change.
1233 config SYS_FSL_THREADS_PER_CORE
1238 config SYS_NUM_TLBCAMS
1239 int "Number of TLB CAM entries"
1240 default 64 if E500MC
1243 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1244 16 for other E500 SoCs.
1249 config SYS_PPC_E500_USE_DEBUG_TLB
1252 config SYS_PPC_E500_DEBUG_TLB
1253 int "Temporary TLB entry for external debugger"
1254 depends on SYS_PPC_E500_USE_DEBUG_TLB
1255 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1256 default 1 if ARCH_MPC8536
1257 default 2 if ARCH_MPC8572 || \
1265 default 3 if ARCH_P1010 || \
1269 Select a temporary TLB entry to be used during boot to work
1270 around limitations in e500v1 and e500v2 external debugger
1271 support. This reduces the portions of the boot code where
1272 breakpoints and single stepping do not work. The value of this
1273 symbol should be set to the TLB1 entry to be used for this
1274 purpose. If unsure, do not change.
1276 source "board/freescale/b4860qds/Kconfig"
1277 source "board/freescale/bsc9131rdb/Kconfig"
1278 source "board/freescale/bsc9132qds/Kconfig"
1279 source "board/freescale/c29xpcie/Kconfig"
1280 source "board/freescale/corenet_ds/Kconfig"
1281 source "board/freescale/mpc8536ds/Kconfig"
1282 source "board/freescale/mpc8540ads/Kconfig"
1283 source "board/freescale/mpc8541cds/Kconfig"
1284 source "board/freescale/mpc8544ds/Kconfig"
1285 source "board/freescale/mpc8548cds/Kconfig"
1286 source "board/freescale/mpc8555cds/Kconfig"
1287 source "board/freescale/mpc8560ads/Kconfig"
1288 source "board/freescale/mpc8568mds/Kconfig"
1289 source "board/freescale/mpc8569mds/Kconfig"
1290 source "board/freescale/mpc8572ds/Kconfig"
1291 source "board/freescale/p1010rdb/Kconfig"
1292 source "board/freescale/p1022ds/Kconfig"
1293 source "board/freescale/p1023rdb/Kconfig"
1294 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1295 source "board/freescale/p1_twr/Kconfig"
1296 source "board/freescale/p2041rdb/Kconfig"
1297 source "board/freescale/qemu-ppce500/Kconfig"
1298 source "board/freescale/t102xqds/Kconfig"
1299 source "board/freescale/t102xrdb/Kconfig"
1300 source "board/freescale/t1040qds/Kconfig"
1301 source "board/freescale/t104xrdb/Kconfig"
1302 source "board/freescale/t208xqds/Kconfig"
1303 source "board/freescale/t208xrdb/Kconfig"
1304 source "board/freescale/t4qds/Kconfig"
1305 source "board/freescale/t4rdb/Kconfig"
1306 source "board/gdsys/p1022/Kconfig"
1307 source "board/keymile/kmp204x/Kconfig"
1308 source "board/sbc8548/Kconfig"
1309 source "board/socrates/Kconfig"
1310 source "board/varisys/cyrus/Kconfig"
1311 source "board/xes/xpedite520x/Kconfig"
1312 source "board/xes/xpedite537x/Kconfig"
1313 source "board/xes/xpedite550x/Kconfig"
1314 source "board/Arcturus/ucp1020/Kconfig"