8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_B4420QDS
28 bool "Support B4420QDS"
33 config TARGET_B4860QDS
34 bool "Support B4860QDS"
36 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 config TARGET_BSC9131RDB
41 bool "Support BSC9131RDB"
44 select BOARD_EARLY_INIT_F
46 config TARGET_BSC9132QDS
47 bool "Support BSC9132QDS"
49 select BOARD_LATE_INIT if CHAIN_OF_TRUST
51 select BOARD_EARLY_INIT_F
53 config TARGET_C29XPCIE
54 bool "Support C29XPCIE"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
62 bool "Support P3041DS"
65 select BOARD_LATE_INIT if CHAIN_OF_TRUST
69 bool "Support P4080DS"
72 select BOARD_LATE_INIT if CHAIN_OF_TRUST
76 bool "Support P5020DS"
79 select BOARD_LATE_INIT if CHAIN_OF_TRUST
83 bool "Support P5040DS"
86 select BOARD_LATE_INIT if CHAIN_OF_TRUST
89 config TARGET_MPC8536DS
90 bool "Support MPC8536DS"
92 # Use DDR3 controller with DDR2 DIMMs on this board
93 select SYS_FSL_DDRC_GEN3
96 config TARGET_MPC8541CDS
97 bool "Support MPC8541CDS"
100 config TARGET_MPC8544DS
101 bool "Support MPC8544DS"
104 config TARGET_MPC8548CDS
105 bool "Support MPC8548CDS"
108 config TARGET_MPC8555CDS
109 bool "Support MPC8555CDS"
112 config TARGET_MPC8568MDS
113 bool "Support MPC8568MDS"
116 config TARGET_MPC8569MDS
117 bool "Support MPC8569MDS"
120 config TARGET_MPC8572DS
121 bool "Support MPC8572DS"
123 # Use DDR3 controller with DDR2 DIMMs on this board
124 select SYS_FSL_DDRC_GEN3
127 config TARGET_P1010RDB_PA
128 bool "Support P1010RDB_PA"
130 select BOARD_LATE_INIT if CHAIN_OF_TRUST
136 config TARGET_P1010RDB_PB
137 bool "Support P1010RDB_PB"
139 select BOARD_LATE_INIT if CHAIN_OF_TRUST
145 config TARGET_P1022DS
146 bool "Support P1022DS"
152 config TARGET_P1023RDB
153 bool "Support P1023RDB"
157 config TARGET_P1020MBG
158 bool "Support P1020MBG-PC"
165 config TARGET_P1020RDB_PC
166 bool "Support P1020RDB-PC"
173 config TARGET_P1020RDB_PD
174 bool "Support P1020RDB-PD"
181 config TARGET_P1020UTM
182 bool "Support P1020UTM"
189 config TARGET_P1021RDB
190 bool "Support P1021RDB"
197 config TARGET_P1024RDB
198 bool "Support P1024RDB"
205 config TARGET_P1025RDB
206 bool "Support P1025RDB"
213 config TARGET_P2020RDB
214 bool "Support P2020RDB-PC"
222 bool "Support p1_twr"
225 config TARGET_P2041RDB
226 bool "Support P2041RDB"
228 select BOARD_LATE_INIT if CHAIN_OF_TRUST
232 config TARGET_QEMU_PPCE500
233 bool "Support qemu-ppce500"
234 select ARCH_QEMU_E500
237 config TARGET_T1024QDS
238 bool "Support T1024QDS"
240 select BOARD_LATE_INIT if CHAIN_OF_TRUST
246 config TARGET_T1023RDB
247 bool "Support T1023RDB"
249 select BOARD_LATE_INIT if CHAIN_OF_TRUST
254 config TARGET_T1024RDB
255 bool "Support T1024RDB"
257 select BOARD_LATE_INIT if CHAIN_OF_TRUST
262 config TARGET_T1040QDS
263 bool "Support T1040QDS"
265 select BOARD_LATE_INIT if CHAIN_OF_TRUST
270 config TARGET_T1040RDB
271 bool "Support T1040RDB"
273 select BOARD_LATE_INIT if CHAIN_OF_TRUST
278 config TARGET_T1040D4RDB
279 bool "Support T1040D4RDB"
281 select BOARD_LATE_INIT if CHAIN_OF_TRUST
286 config TARGET_T1042RDB
287 bool "Support T1042RDB"
289 select BOARD_LATE_INIT if CHAIN_OF_TRUST
294 config TARGET_T1042D4RDB
295 bool "Support T1042D4RDB"
297 select BOARD_LATE_INIT if CHAIN_OF_TRUST
302 config TARGET_T1042RDB_PI
303 bool "Support T1042RDB_PI"
305 select BOARD_LATE_INIT if CHAIN_OF_TRUST
310 config TARGET_T2080QDS
311 bool "Support T2080QDS"
313 select BOARD_LATE_INIT if CHAIN_OF_TRUST
318 config TARGET_T2080RDB
319 bool "Support T2080RDB"
321 select BOARD_LATE_INIT if CHAIN_OF_TRUST
326 config TARGET_T2081QDS
327 bool "Support T2081QDS"
332 config TARGET_T4160QDS
333 bool "Support T4160QDS"
335 select BOARD_LATE_INIT if CHAIN_OF_TRUST
340 config TARGET_T4160RDB
341 bool "Support T4160RDB"
346 config TARGET_T4240QDS
347 bool "Support T4240QDS"
349 select BOARD_LATE_INIT if CHAIN_OF_TRUST
354 config TARGET_T4240RDB
355 bool "Support T4240RDB"
361 config TARGET_CONTROLCENTERD
362 bool "Support controlcenterd"
365 config TARGET_KMP204X
366 bool "Support kmp204x"
372 config TARGET_XPEDITE520X
373 bool "Support xpedite520x"
376 config TARGET_XPEDITE537X
377 bool "Support xpedite537x"
379 # Use DDR3 controller with DDR2 DIMMs on this board
380 select SYS_FSL_DDRC_GEN3
382 config TARGET_XPEDITE550X
383 bool "Support xpedite550x"
386 config TARGET_UCP1020
387 bool "Support uCP1020"
391 config TARGET_CYRUS_P5020
392 bool "Support Varisys Cyrus P5020"
396 config TARGET_CYRUS_P5040
397 bool "Support Varisys Cyrus P5040"
408 select SYS_FSL_DDR_VER_47
409 select SYS_FSL_ERRATUM_A004477
410 select SYS_FSL_ERRATUM_A005871
411 select SYS_FSL_ERRATUM_A006379
412 select SYS_FSL_ERRATUM_A006384
413 select SYS_FSL_ERRATUM_A006475
414 select SYS_FSL_ERRATUM_A006593
415 select SYS_FSL_ERRATUM_A007075
416 select SYS_FSL_ERRATUM_A007186
417 select SYS_FSL_ERRATUM_A007212
418 select SYS_FSL_ERRATUM_A009942
419 select SYS_FSL_HAS_DDR3
420 select SYS_FSL_HAS_SEC
421 select SYS_FSL_QORIQ_CHASSIS2
422 select SYS_FSL_SEC_BE
423 select SYS_FSL_SEC_COMPAT_4
433 select SYS_FSL_DDR_VER_47
434 select SYS_FSL_ERRATUM_A004477
435 select SYS_FSL_ERRATUM_A005871
436 select SYS_FSL_ERRATUM_A006379
437 select SYS_FSL_ERRATUM_A006384
438 select SYS_FSL_ERRATUM_A006475
439 select SYS_FSL_ERRATUM_A006593
440 select SYS_FSL_ERRATUM_A007075
441 select SYS_FSL_ERRATUM_A007186
442 select SYS_FSL_ERRATUM_A007212
443 select SYS_FSL_ERRATUM_A007907
444 select SYS_FSL_ERRATUM_A009942
445 select SYS_FSL_HAS_DDR3
446 select SYS_FSL_HAS_SEC
447 select SYS_FSL_QORIQ_CHASSIS2
448 select SYS_FSL_SEC_BE
449 select SYS_FSL_SEC_COMPAT_4
457 select SYS_FSL_DDR_VER_44
458 select SYS_FSL_ERRATUM_A004477
459 select SYS_FSL_ERRATUM_A005125
460 select SYS_FSL_ERRATUM_ESDHC111
461 select SYS_FSL_HAS_DDR3
462 select SYS_FSL_HAS_SEC
463 select SYS_FSL_SEC_BE
464 select SYS_FSL_SEC_COMPAT_4
471 select SYS_FSL_DDR_VER_46
472 select SYS_FSL_ERRATUM_A004477
473 select SYS_FSL_ERRATUM_A005125
474 select SYS_FSL_ERRATUM_A005434
475 select SYS_FSL_ERRATUM_ESDHC111
476 select SYS_FSL_ERRATUM_I2C_A004447
477 select SYS_FSL_ERRATUM_IFC_A002769
478 select SYS_FSL_HAS_DDR3
479 select SYS_FSL_HAS_SEC
480 select SYS_FSL_SEC_BE
481 select SYS_FSL_SEC_COMPAT_4
482 select SYS_PPC_E500_USE_DEBUG_TLB
489 select SYS_FSL_DDR_VER_46
490 select SYS_FSL_ERRATUM_A005125
491 select SYS_FSL_ERRATUM_ESDHC111
492 select SYS_FSL_HAS_DDR3
493 select SYS_FSL_HAS_SEC
494 select SYS_FSL_SEC_BE
495 select SYS_FSL_SEC_COMPAT_6
496 select SYS_PPC_E500_USE_DEBUG_TLB
502 select SYS_FSL_ERRATUM_A004508
503 select SYS_FSL_ERRATUM_A005125
504 select SYS_FSL_HAS_DDR2
505 select SYS_FSL_HAS_DDR3
506 select SYS_FSL_HAS_SEC
507 select SYS_FSL_SEC_BE
508 select SYS_FSL_SEC_COMPAT_2
509 select SYS_PPC_E500_USE_DEBUG_TLB
516 select SYS_FSL_HAS_DDR1
521 select SYS_FSL_HAS_DDR1
522 select SYS_FSL_HAS_SEC
523 select SYS_FSL_SEC_BE
524 select SYS_FSL_SEC_COMPAT_2
529 select SYS_FSL_ERRATUM_A005125
530 select SYS_FSL_HAS_DDR2
531 select SYS_FSL_HAS_SEC
532 select SYS_FSL_SEC_BE
533 select SYS_FSL_SEC_COMPAT_2
534 select SYS_PPC_E500_USE_DEBUG_TLB
540 select SYS_FSL_ERRATUM_A005125
541 select SYS_FSL_ERRATUM_NMG_DDR120
542 select SYS_FSL_ERRATUM_NMG_LBC103
543 select SYS_FSL_ERRATUM_NMG_ETSEC129
544 select SYS_FSL_ERRATUM_I2C_A004447
545 select SYS_FSL_HAS_DDR2
546 select SYS_FSL_HAS_DDR1
547 select SYS_FSL_HAS_SEC
548 select SYS_FSL_SEC_BE
549 select SYS_FSL_SEC_COMPAT_2
550 select SYS_PPC_E500_USE_DEBUG_TLB
555 select SYS_FSL_HAS_DDR1
556 select SYS_FSL_HAS_SEC
557 select SYS_FSL_SEC_BE
558 select SYS_FSL_SEC_COMPAT_2
563 select SYS_FSL_HAS_DDR1
568 select SYS_FSL_HAS_DDR2
569 select SYS_FSL_HAS_SEC
570 select SYS_FSL_SEC_BE
571 select SYS_FSL_SEC_COMPAT_2
576 select SYS_FSL_ERRATUM_A004508
577 select SYS_FSL_ERRATUM_A005125
578 select SYS_FSL_HAS_DDR3
579 select SYS_FSL_HAS_SEC
580 select SYS_FSL_SEC_BE
581 select SYS_FSL_SEC_COMPAT_2
587 select SYS_FSL_ERRATUM_A004508
588 select SYS_FSL_ERRATUM_A005125
589 select SYS_FSL_ERRATUM_DDR_115
590 select SYS_FSL_ERRATUM_DDR111_DDR134
591 select SYS_FSL_HAS_DDR2
592 select SYS_FSL_HAS_DDR3
593 select SYS_FSL_HAS_SEC
594 select SYS_FSL_SEC_BE
595 select SYS_FSL_SEC_COMPAT_2
596 select SYS_PPC_E500_USE_DEBUG_TLB
602 select SYS_FSL_ERRATUM_A004477
603 select SYS_FSL_ERRATUM_A004508
604 select SYS_FSL_ERRATUM_A005125
605 select SYS_FSL_ERRATUM_A006261
606 select SYS_FSL_ERRATUM_A007075
607 select SYS_FSL_ERRATUM_ESDHC111
608 select SYS_FSL_ERRATUM_I2C_A004447
609 select SYS_FSL_ERRATUM_IFC_A002769
610 select SYS_FSL_ERRATUM_P1010_A003549
611 select SYS_FSL_ERRATUM_SEC_A003571
612 select SYS_FSL_ERRATUM_IFC_A003399
613 select SYS_FSL_HAS_DDR3
614 select SYS_FSL_HAS_SEC
615 select SYS_FSL_SEC_BE
616 select SYS_FSL_SEC_COMPAT_4
617 select SYS_PPC_E500_USE_DEBUG_TLB
625 select SYS_FSL_ERRATUM_A004508
626 select SYS_FSL_ERRATUM_A005125
627 select SYS_FSL_ERRATUM_ELBC_A001
628 select SYS_FSL_ERRATUM_ESDHC111
629 select SYS_FSL_HAS_DDR3
630 select SYS_FSL_HAS_SEC
631 select SYS_FSL_SEC_BE
632 select SYS_FSL_SEC_COMPAT_2
633 select SYS_PPC_E500_USE_DEBUG_TLB
639 select SYS_FSL_ERRATUM_A004508
640 select SYS_FSL_ERRATUM_A005125
641 select SYS_FSL_ERRATUM_ELBC_A001
642 select SYS_FSL_ERRATUM_ESDHC111
643 select SYS_FSL_HAS_DDR3
644 select SYS_FSL_HAS_SEC
645 select SYS_FSL_SEC_BE
646 select SYS_FSL_SEC_COMPAT_2
647 select SYS_PPC_E500_USE_DEBUG_TLB
654 select SYS_FSL_ERRATUM_A004508
655 select SYS_FSL_ERRATUM_A005125
656 select SYS_FSL_ERRATUM_ELBC_A001
657 select SYS_FSL_ERRATUM_ESDHC111
658 select SYS_FSL_HAS_DDR3
659 select SYS_FSL_HAS_SEC
660 select SYS_FSL_SEC_BE
661 select SYS_FSL_SEC_COMPAT_2
662 select SYS_PPC_E500_USE_DEBUG_TLB
669 select SYS_FSL_ERRATUM_A004477
670 select SYS_FSL_ERRATUM_A004508
671 select SYS_FSL_ERRATUM_A005125
672 select SYS_FSL_ERRATUM_ELBC_A001
673 select SYS_FSL_ERRATUM_ESDHC111
674 select SYS_FSL_ERRATUM_SATA_A001
675 select SYS_FSL_HAS_DDR3
676 select SYS_FSL_HAS_SEC
677 select SYS_FSL_SEC_BE
678 select SYS_FSL_SEC_COMPAT_2
679 select SYS_PPC_E500_USE_DEBUG_TLB
685 select SYS_FSL_ERRATUM_A004508
686 select SYS_FSL_ERRATUM_A005125
687 select SYS_FSL_ERRATUM_I2C_A004447
688 select SYS_FSL_HAS_DDR3
689 select SYS_FSL_HAS_SEC
690 select SYS_FSL_SEC_BE
691 select SYS_FSL_SEC_COMPAT_4
697 select SYS_FSL_ERRATUM_A004508
698 select SYS_FSL_ERRATUM_A005125
699 select SYS_FSL_ERRATUM_ELBC_A001
700 select SYS_FSL_ERRATUM_ESDHC111
701 select SYS_FSL_HAS_DDR3
702 select SYS_FSL_HAS_SEC
703 select SYS_FSL_SEC_BE
704 select SYS_FSL_SEC_COMPAT_2
705 select SYS_PPC_E500_USE_DEBUG_TLB
713 select SYS_FSL_ERRATUM_A004508
714 select SYS_FSL_ERRATUM_A005125
715 select SYS_FSL_ERRATUM_ELBC_A001
716 select SYS_FSL_ERRATUM_ESDHC111
717 select SYS_FSL_HAS_DDR3
718 select SYS_FSL_HAS_SEC
719 select SYS_FSL_SEC_BE
720 select SYS_FSL_SEC_COMPAT_2
721 select SYS_PPC_E500_USE_DEBUG_TLB
728 select SYS_FSL_ERRATUM_A004477
729 select SYS_FSL_ERRATUM_A004508
730 select SYS_FSL_ERRATUM_A005125
731 select SYS_FSL_ERRATUM_ESDHC111
732 select SYS_FSL_ERRATUM_ESDHC_A001
733 select SYS_FSL_HAS_DDR3
734 select SYS_FSL_HAS_SEC
735 select SYS_FSL_SEC_BE
736 select SYS_FSL_SEC_COMPAT_2
737 select SYS_PPC_E500_USE_DEBUG_TLB
745 select SYS_FSL_ERRATUM_A004510
746 select SYS_FSL_ERRATUM_A004849
747 select SYS_FSL_ERRATUM_A006261
748 select SYS_FSL_ERRATUM_CPU_A003999
749 select SYS_FSL_ERRATUM_DDR_A003
750 select SYS_FSL_ERRATUM_DDR_A003474
751 select SYS_FSL_ERRATUM_ESDHC111
752 select SYS_FSL_ERRATUM_I2C_A004447
753 select SYS_FSL_ERRATUM_NMG_CPU_A011
754 select SYS_FSL_ERRATUM_SRIO_A004034
755 select SYS_FSL_ERRATUM_USB14
756 select SYS_FSL_HAS_DDR3
757 select SYS_FSL_HAS_SEC
758 select SYS_FSL_QORIQ_CHASSIS1
759 select SYS_FSL_SEC_BE
760 select SYS_FSL_SEC_COMPAT_4
767 select SYS_FSL_DDR_VER_44
768 select SYS_FSL_ERRATUM_A004510
769 select SYS_FSL_ERRATUM_A004849
770 select SYS_FSL_ERRATUM_A005812
771 select SYS_FSL_ERRATUM_A006261
772 select SYS_FSL_ERRATUM_CPU_A003999
773 select SYS_FSL_ERRATUM_DDR_A003
774 select SYS_FSL_ERRATUM_DDR_A003474
775 select SYS_FSL_ERRATUM_ESDHC111
776 select SYS_FSL_ERRATUM_I2C_A004447
777 select SYS_FSL_ERRATUM_NMG_CPU_A011
778 select SYS_FSL_ERRATUM_SRIO_A004034
779 select SYS_FSL_ERRATUM_USB14
780 select SYS_FSL_HAS_DDR3
781 select SYS_FSL_HAS_SEC
782 select SYS_FSL_QORIQ_CHASSIS1
783 select SYS_FSL_SEC_BE
784 select SYS_FSL_SEC_COMPAT_4
792 select SYS_FSL_DDR_VER_44
793 select SYS_FSL_ERRATUM_A004510
794 select SYS_FSL_ERRATUM_A004580
795 select SYS_FSL_ERRATUM_A004849
796 select SYS_FSL_ERRATUM_A005812
797 select SYS_FSL_ERRATUM_A007075
798 select SYS_FSL_ERRATUM_CPC_A002
799 select SYS_FSL_ERRATUM_CPC_A003
800 select SYS_FSL_ERRATUM_CPU_A003999
801 select SYS_FSL_ERRATUM_DDR_A003
802 select SYS_FSL_ERRATUM_DDR_A003474
803 select SYS_FSL_ERRATUM_ELBC_A001
804 select SYS_FSL_ERRATUM_ESDHC111
805 select SYS_FSL_ERRATUM_ESDHC13
806 select SYS_FSL_ERRATUM_ESDHC135
807 select SYS_FSL_ERRATUM_I2C_A004447
808 select SYS_FSL_ERRATUM_NMG_CPU_A011
809 select SYS_FSL_ERRATUM_SRIO_A004034
810 select SYS_P4080_ERRATUM_CPU22
811 select SYS_P4080_ERRATUM_PCIE_A003
812 select SYS_P4080_ERRATUM_SERDES8
813 select SYS_P4080_ERRATUM_SERDES9
814 select SYS_P4080_ERRATUM_SERDES_A001
815 select SYS_P4080_ERRATUM_SERDES_A005
816 select SYS_FSL_HAS_DDR3
817 select SYS_FSL_HAS_SEC
818 select SYS_FSL_QORIQ_CHASSIS1
819 select SYS_FSL_SEC_BE
820 select SYS_FSL_SEC_COMPAT_4
828 select SYS_FSL_DDR_VER_44
829 select SYS_FSL_ERRATUM_A004510
830 select SYS_FSL_ERRATUM_A006261
831 select SYS_FSL_ERRATUM_DDR_A003
832 select SYS_FSL_ERRATUM_DDR_A003474
833 select SYS_FSL_ERRATUM_ESDHC111
834 select SYS_FSL_ERRATUM_I2C_A004447
835 select SYS_FSL_ERRATUM_SRIO_A004034
836 select SYS_FSL_ERRATUM_USB14
837 select SYS_FSL_HAS_DDR3
838 select SYS_FSL_HAS_SEC
839 select SYS_FSL_QORIQ_CHASSIS1
840 select SYS_FSL_SEC_BE
841 select SYS_FSL_SEC_COMPAT_4
850 select SYS_FSL_DDR_VER_44
851 select SYS_FSL_ERRATUM_A004510
852 select SYS_FSL_ERRATUM_A004699
853 select SYS_FSL_ERRATUM_A005812
854 select SYS_FSL_ERRATUM_A006261
855 select SYS_FSL_ERRATUM_DDR_A003
856 select SYS_FSL_ERRATUM_DDR_A003474
857 select SYS_FSL_ERRATUM_ESDHC111
858 select SYS_FSL_ERRATUM_USB14
859 select SYS_FSL_HAS_DDR3
860 select SYS_FSL_HAS_SEC
861 select SYS_FSL_QORIQ_CHASSIS1
862 select SYS_FSL_SEC_BE
863 select SYS_FSL_SEC_COMPAT_4
868 config ARCH_QEMU_E500
875 select SYS_FSL_DDR_VER_50
876 select SYS_FSL_ERRATUM_A008378
877 select SYS_FSL_ERRATUM_A009663
878 select SYS_FSL_ERRATUM_A009942
879 select SYS_FSL_ERRATUM_ESDHC111
880 select SYS_FSL_HAS_DDR3
881 select SYS_FSL_HAS_DDR4
882 select SYS_FSL_HAS_SEC
883 select SYS_FSL_QORIQ_CHASSIS2
884 select SYS_FSL_SEC_BE
885 select SYS_FSL_SEC_COMPAT_5
893 select SYS_FSL_DDR_VER_50
894 select SYS_FSL_ERRATUM_A008378
895 select SYS_FSL_ERRATUM_A009663
896 select SYS_FSL_ERRATUM_A009942
897 select SYS_FSL_ERRATUM_ESDHC111
898 select SYS_FSL_HAS_DDR3
899 select SYS_FSL_HAS_DDR4
900 select SYS_FSL_HAS_SEC
901 select SYS_FSL_QORIQ_CHASSIS2
902 select SYS_FSL_SEC_BE
903 select SYS_FSL_SEC_COMPAT_5
911 select SYS_FSL_DDR_VER_50
912 select SYS_FSL_ERRATUM_A008044
913 select SYS_FSL_ERRATUM_A008378
914 select SYS_FSL_ERRATUM_A009663
915 select SYS_FSL_ERRATUM_A009942
916 select SYS_FSL_ERRATUM_ESDHC111
917 select SYS_FSL_HAS_DDR3
918 select SYS_FSL_HAS_DDR4
919 select SYS_FSL_HAS_SEC
920 select SYS_FSL_QORIQ_CHASSIS2
921 select SYS_FSL_SEC_BE
922 select SYS_FSL_SEC_COMPAT_5
930 select SYS_FSL_DDR_VER_50
931 select SYS_FSL_ERRATUM_A008044
932 select SYS_FSL_ERRATUM_A008378
933 select SYS_FSL_ERRATUM_A009663
934 select SYS_FSL_ERRATUM_A009942
935 select SYS_FSL_ERRATUM_ESDHC111
936 select SYS_FSL_HAS_DDR3
937 select SYS_FSL_HAS_DDR4
938 select SYS_FSL_HAS_SEC
939 select SYS_FSL_QORIQ_CHASSIS2
940 select SYS_FSL_SEC_BE
941 select SYS_FSL_SEC_COMPAT_5
950 select SYS_FSL_DDR_VER_47
951 select SYS_FSL_ERRATUM_A006379
952 select SYS_FSL_ERRATUM_A006593
953 select SYS_FSL_ERRATUM_A007186
954 select SYS_FSL_ERRATUM_A007212
955 select SYS_FSL_ERRATUM_A007815
956 select SYS_FSL_ERRATUM_A007907
957 select SYS_FSL_ERRATUM_A009942
958 select SYS_FSL_ERRATUM_ESDHC111
959 select SYS_FSL_HAS_DDR3
960 select SYS_FSL_HAS_SEC
961 select SYS_FSL_QORIQ_CHASSIS2
962 select SYS_FSL_SEC_BE
963 select SYS_FSL_SEC_COMPAT_4
973 select SYS_FSL_DDR_VER_47
974 select SYS_FSL_ERRATUM_A006379
975 select SYS_FSL_ERRATUM_A006593
976 select SYS_FSL_ERRATUM_A007186
977 select SYS_FSL_ERRATUM_A007212
978 select SYS_FSL_ERRATUM_A009942
979 select SYS_FSL_ERRATUM_ESDHC111
980 select SYS_FSL_HAS_DDR3
981 select SYS_FSL_HAS_SEC
982 select SYS_FSL_QORIQ_CHASSIS2
983 select SYS_FSL_SEC_BE
984 select SYS_FSL_SEC_COMPAT_4
993 select SYS_FSL_DDR_VER_47
994 select SYS_FSL_ERRATUM_A004468
995 select SYS_FSL_ERRATUM_A005871
996 select SYS_FSL_ERRATUM_A006379
997 select SYS_FSL_ERRATUM_A006593
998 select SYS_FSL_ERRATUM_A007186
999 select SYS_FSL_ERRATUM_A007798
1000 select SYS_FSL_ERRATUM_A009942
1001 select SYS_FSL_HAS_DDR3
1002 select SYS_FSL_HAS_SEC
1003 select SYS_FSL_QORIQ_CHASSIS2
1004 select SYS_FSL_SEC_BE
1005 select SYS_FSL_SEC_COMPAT_4
1015 select SYS_FSL_DDR_VER_47
1016 select SYS_FSL_ERRATUM_A004468
1017 select SYS_FSL_ERRATUM_A005871
1018 select SYS_FSL_ERRATUM_A006261
1019 select SYS_FSL_ERRATUM_A006379
1020 select SYS_FSL_ERRATUM_A006593
1021 select SYS_FSL_ERRATUM_A007186
1022 select SYS_FSL_ERRATUM_A007798
1023 select SYS_FSL_ERRATUM_A007815
1024 select SYS_FSL_ERRATUM_A007907
1025 select SYS_FSL_ERRATUM_A009942
1026 select SYS_FSL_HAS_DDR3
1027 select SYS_FSL_HAS_SEC
1028 select SYS_FSL_QORIQ_CHASSIS2
1029 select SYS_FSL_SEC_BE
1030 select SYS_FSL_SEC_COMPAT_4
1043 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1048 Enble PowerPC E500MC core
1053 Enable PowerPC E6500 core
1058 Use Freescale common code for Local Access Window
1063 Enable Freescale Secure Boot feature. Normally selected
1064 by defconfig. If unsure, do not change.
1067 int "Maximum number of CPUs permitted for MPC85xx"
1068 default 12 if ARCH_T4240
1069 default 8 if ARCH_P4080 || \
1071 default 4 if ARCH_B4860 || \
1079 default 2 if ARCH_B4420 || \
1094 Set this number to the maximum number of possible CPUs in the SoC.
1095 SoCs may have multiple clusters with each cluster may have multiple
1096 ports. If some ports are reserved but higher ports are used for
1097 cores, count the reserved ports. This will allocate enough memory
1098 in spin table to properly handle all cores.
1100 config SYS_CCSRBAR_DEFAULT
1101 hex "Default CCSRBAR address"
1102 default 0xff700000 if ARCH_BSC9131 || \
1123 default 0xff600000 if ARCH_P1023
1124 default 0xfe000000 if ARCH_B4420 || \
1139 default 0xe0000000 if ARCH_QEMU_E500
1141 Default value of CCSRBAR comes from power-on-reset. It
1142 is fixed on each SoC. Some SoCs can have different value
1143 if changed by pre-boot regime. The value here must match
1144 the current value in SoC. If not sure, do not change.
1146 config SYS_FSL_ERRATUM_A004468
1149 config SYS_FSL_ERRATUM_A004477
1152 config SYS_FSL_ERRATUM_A004508
1155 config SYS_FSL_ERRATUM_A004580
1158 config SYS_FSL_ERRATUM_A004699
1161 config SYS_FSL_ERRATUM_A004849
1164 config SYS_FSL_ERRATUM_A004510
1167 config SYS_FSL_ERRATUM_A004510_SVR_REV
1169 depends on SYS_FSL_ERRATUM_A004510
1170 default 0x20 if ARCH_P4080
1173 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1175 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1178 config SYS_FSL_ERRATUM_A005125
1181 config SYS_FSL_ERRATUM_A005434
1184 config SYS_FSL_ERRATUM_A005812
1187 config SYS_FSL_ERRATUM_A005871
1190 config SYS_FSL_ERRATUM_A006261
1193 config SYS_FSL_ERRATUM_A006379
1196 config SYS_FSL_ERRATUM_A006384
1199 config SYS_FSL_ERRATUM_A006475
1202 config SYS_FSL_ERRATUM_A006593
1205 config SYS_FSL_ERRATUM_A007075
1208 config SYS_FSL_ERRATUM_A007186
1211 config SYS_FSL_ERRATUM_A007212
1214 config SYS_FSL_ERRATUM_A007815
1217 config SYS_FSL_ERRATUM_A007798
1220 config SYS_FSL_ERRATUM_A007907
1223 config SYS_FSL_ERRATUM_A008044
1226 config SYS_FSL_ERRATUM_CPC_A002
1229 config SYS_FSL_ERRATUM_CPC_A003
1232 config SYS_FSL_ERRATUM_CPU_A003999
1235 config SYS_FSL_ERRATUM_ELBC_A001
1238 config SYS_FSL_ERRATUM_I2C_A004447
1241 config SYS_FSL_A004447_SVR_REV
1243 depends on SYS_FSL_ERRATUM_I2C_A004447
1244 default 0x00 if ARCH_MPC8548
1245 default 0x10 if ARCH_P1010
1246 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1247 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1249 config SYS_FSL_ERRATUM_IFC_A002769
1252 config SYS_FSL_ERRATUM_IFC_A003399
1255 config SYS_FSL_ERRATUM_NMG_CPU_A011
1258 config SYS_FSL_ERRATUM_NMG_ETSEC129
1261 config SYS_FSL_ERRATUM_NMG_LBC103
1264 config SYS_FSL_ERRATUM_P1010_A003549
1267 config SYS_FSL_ERRATUM_SATA_A001
1270 config SYS_FSL_ERRATUM_SEC_A003571
1273 config SYS_FSL_ERRATUM_SRIO_A004034
1276 config SYS_FSL_ERRATUM_USB14
1279 config SYS_P4080_ERRATUM_CPU22
1282 config SYS_P4080_ERRATUM_PCIE_A003
1285 config SYS_P4080_ERRATUM_SERDES8
1288 config SYS_P4080_ERRATUM_SERDES9
1291 config SYS_P4080_ERRATUM_SERDES_A001
1294 config SYS_P4080_ERRATUM_SERDES_A005
1297 config SYS_FSL_QORIQ_CHASSIS1
1300 config SYS_FSL_QORIQ_CHASSIS2
1303 config SYS_FSL_NUM_LAWS
1304 int "Number of local access windows"
1306 default 32 if ARCH_B4420 || \
1317 default 16 if ARCH_T1023 || \
1321 default 12 if ARCH_BSC9131 || \
1335 default 10 if ARCH_MPC8544 || \
1339 default 8 if ARCH_MPC8540 || \
1344 Number of local access windows. This is fixed per SoC.
1345 If not sure, do not change.
1347 config SYS_FSL_THREADS_PER_CORE
1352 config SYS_NUM_TLBCAMS
1353 int "Number of TLB CAM entries"
1354 default 64 if E500MC
1357 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1358 16 for other E500 SoCs.
1363 config SYS_PPC_E500_USE_DEBUG_TLB
1372 config SYS_PPC_E500_DEBUG_TLB
1373 int "Temporary TLB entry for external debugger"
1374 depends on SYS_PPC_E500_USE_DEBUG_TLB
1375 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1376 default 1 if ARCH_MPC8536
1377 default 2 if ARCH_MPC8572 || \
1385 default 3 if ARCH_P1010 || \
1389 Select a temporary TLB entry to be used during boot to work
1390 around limitations in e500v1 and e500v2 external debugger
1391 support. This reduces the portions of the boot code where
1392 breakpoints and single stepping do not work. The value of this
1393 symbol should be set to the TLB1 entry to be used for this
1394 purpose. If unsure, do not change.
1396 config SYS_FSL_IFC_CLK_DIV
1397 int "Divider of platform clock"
1399 default 2 if ARCH_B4420 || \
1409 Defines divider of platform clock(clock input to
1412 config SYS_FSL_LBC_CLK_DIV
1413 int "Divider of platform clock"
1414 depends on FSL_ELBC || ARCH_MPC8540 || \
1415 ARCH_MPC8548 || ARCH_MPC8541 || \
1416 ARCH_MPC8555 || ARCH_MPC8560 || \
1419 default 2 if ARCH_P2041 || \
1427 Defines divider of platform clock(clock input to
1430 source "board/freescale/b4860qds/Kconfig"
1431 source "board/freescale/bsc9131rdb/Kconfig"
1432 source "board/freescale/bsc9132qds/Kconfig"
1433 source "board/freescale/c29xpcie/Kconfig"
1434 source "board/freescale/corenet_ds/Kconfig"
1435 source "board/freescale/mpc8536ds/Kconfig"
1436 source "board/freescale/mpc8541cds/Kconfig"
1437 source "board/freescale/mpc8544ds/Kconfig"
1438 source "board/freescale/mpc8548cds/Kconfig"
1439 source "board/freescale/mpc8555cds/Kconfig"
1440 source "board/freescale/mpc8568mds/Kconfig"
1441 source "board/freescale/mpc8569mds/Kconfig"
1442 source "board/freescale/mpc8572ds/Kconfig"
1443 source "board/freescale/p1010rdb/Kconfig"
1444 source "board/freescale/p1022ds/Kconfig"
1445 source "board/freescale/p1023rdb/Kconfig"
1446 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1447 source "board/freescale/p1_twr/Kconfig"
1448 source "board/freescale/p2041rdb/Kconfig"
1449 source "board/freescale/qemu-ppce500/Kconfig"
1450 source "board/freescale/t102xqds/Kconfig"
1451 source "board/freescale/t102xrdb/Kconfig"
1452 source "board/freescale/t1040qds/Kconfig"
1453 source "board/freescale/t104xrdb/Kconfig"
1454 source "board/freescale/t208xqds/Kconfig"
1455 source "board/freescale/t208xrdb/Kconfig"
1456 source "board/freescale/t4qds/Kconfig"
1457 source "board/freescale/t4rdb/Kconfig"
1458 source "board/gdsys/p1022/Kconfig"
1459 source "board/keymile/kmp204x/Kconfig"
1460 source "board/sbc8548/Kconfig"
1461 source "board/socrates/Kconfig"
1462 source "board/varisys/cyrus/Kconfig"
1463 source "board/xes/xpedite520x/Kconfig"
1464 source "board/xes/xpedite537x/Kconfig"
1465 source "board/xes/xpedite550x/Kconfig"
1466 source "board/Arcturus/ucp1020/Kconfig"