8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
24 config TARGET_SOCRATES
25 bool "Support socrates"
28 config TARGET_B4420QDS
29 bool "Support B4420QDS"
34 config TARGET_B4860QDS
35 bool "Support B4860QDS"
37 select BOARD_LATE_INIT if CHAIN_OF_TRUST
41 config TARGET_BSC9131RDB
42 bool "Support BSC9131RDB"
45 select BOARD_EARLY_INIT_F
47 config TARGET_BSC9132QDS
48 bool "Support BSC9132QDS"
50 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 select BOARD_EARLY_INIT_F
54 config TARGET_C29XPCIE
55 bool "Support C29XPCIE"
57 select BOARD_LATE_INIT if CHAIN_OF_TRUST
63 bool "Support P3041DS"
66 select BOARD_LATE_INIT if CHAIN_OF_TRUST
70 bool "Support P4080DS"
73 select BOARD_LATE_INIT if CHAIN_OF_TRUST
77 bool "Support P5020DS"
80 select BOARD_LATE_INIT if CHAIN_OF_TRUST
84 bool "Support P5040DS"
87 select BOARD_LATE_INIT if CHAIN_OF_TRUST
90 config TARGET_MPC8536DS
91 bool "Support MPC8536DS"
93 # Use DDR3 controller with DDR2 DIMMs on this board
94 select SYS_FSL_DDRC_GEN3
97 config TARGET_MPC8541CDS
98 bool "Support MPC8541CDS"
101 config TARGET_MPC8544DS
102 bool "Support MPC8544DS"
105 config TARGET_MPC8548CDS
106 bool "Support MPC8548CDS"
108 imply ENV_IS_IN_FLASH
110 config TARGET_MPC8555CDS
111 bool "Support MPC8555CDS"
114 config TARGET_MPC8568MDS
115 bool "Support MPC8568MDS"
118 config TARGET_MPC8569MDS
119 bool "Support MPC8569MDS"
122 config TARGET_MPC8572DS
123 bool "Support MPC8572DS"
125 # Use DDR3 controller with DDR2 DIMMs on this board
126 select SYS_FSL_DDRC_GEN3
129 config TARGET_P1010RDB_PA
130 bool "Support P1010RDB_PA"
132 select BOARD_LATE_INIT if CHAIN_OF_TRUST
138 config TARGET_P1010RDB_PB
139 bool "Support P1010RDB_PB"
141 select BOARD_LATE_INIT if CHAIN_OF_TRUST
147 config TARGET_P1022DS
148 bool "Support P1022DS"
154 config TARGET_P1023RDB
155 bool "Support P1023RDB"
159 config TARGET_P1020MBG
160 bool "Support P1020MBG-PC"
167 config TARGET_P1020RDB_PC
168 bool "Support P1020RDB-PC"
175 config TARGET_P1020RDB_PD
176 bool "Support P1020RDB-PD"
183 config TARGET_P1020UTM
184 bool "Support P1020UTM"
191 config TARGET_P1021RDB
192 bool "Support P1021RDB"
199 config TARGET_P1024RDB
200 bool "Support P1024RDB"
207 config TARGET_P1025RDB
208 bool "Support P1025RDB"
215 config TARGET_P2020RDB
216 bool "Support P2020RDB-PC"
224 bool "Support p1_twr"
227 config TARGET_P2041RDB
228 bool "Support P2041RDB"
230 select BOARD_LATE_INIT if CHAIN_OF_TRUST
234 config TARGET_QEMU_PPCE500
235 bool "Support qemu-ppce500"
236 select ARCH_QEMU_E500
239 config TARGET_T1024QDS
240 bool "Support T1024QDS"
242 select BOARD_LATE_INIT if CHAIN_OF_TRUST
248 config TARGET_T1023RDB
249 bool "Support T1023RDB"
251 select BOARD_LATE_INIT if CHAIN_OF_TRUST
256 config TARGET_T1024RDB
257 bool "Support T1024RDB"
259 select BOARD_LATE_INIT if CHAIN_OF_TRUST
264 config TARGET_T1040QDS
265 bool "Support T1040QDS"
267 select BOARD_LATE_INIT if CHAIN_OF_TRUST
272 config TARGET_T1040RDB
273 bool "Support T1040RDB"
275 select BOARD_LATE_INIT if CHAIN_OF_TRUST
280 config TARGET_T1040D4RDB
281 bool "Support T1040D4RDB"
283 select BOARD_LATE_INIT if CHAIN_OF_TRUST
288 config TARGET_T1042RDB
289 bool "Support T1042RDB"
291 select BOARD_LATE_INIT if CHAIN_OF_TRUST
296 config TARGET_T1042D4RDB
297 bool "Support T1042D4RDB"
299 select BOARD_LATE_INIT if CHAIN_OF_TRUST
304 config TARGET_T1042RDB_PI
305 bool "Support T1042RDB_PI"
307 select BOARD_LATE_INIT if CHAIN_OF_TRUST
312 config TARGET_T2080QDS
313 bool "Support T2080QDS"
315 select BOARD_LATE_INIT if CHAIN_OF_TRUST
320 config TARGET_T2080RDB
321 bool "Support T2080RDB"
323 select BOARD_LATE_INIT if CHAIN_OF_TRUST
328 config TARGET_T2081QDS
329 bool "Support T2081QDS"
334 config TARGET_T4160QDS
335 bool "Support T4160QDS"
337 select BOARD_LATE_INIT if CHAIN_OF_TRUST
342 config TARGET_T4160RDB
343 bool "Support T4160RDB"
348 config TARGET_T4240QDS
349 bool "Support T4240QDS"
351 select BOARD_LATE_INIT if CHAIN_OF_TRUST
356 config TARGET_T4240RDB
357 bool "Support T4240RDB"
363 config TARGET_CONTROLCENTERD
364 bool "Support controlcenterd"
367 config TARGET_KMP204X
368 bool "Support kmp204x"
374 config TARGET_XPEDITE520X
375 bool "Support xpedite520x"
378 config TARGET_XPEDITE537X
379 bool "Support xpedite537x"
381 # Use DDR3 controller with DDR2 DIMMs on this board
382 select SYS_FSL_DDRC_GEN3
384 config TARGET_XPEDITE550X
385 bool "Support xpedite550x"
388 config TARGET_UCP1020
389 bool "Support uCP1020"
393 config TARGET_CYRUS_P5020
394 bool "Support Varisys Cyrus P5020"
398 config TARGET_CYRUS_P5040
399 bool "Support Varisys Cyrus P5040"
410 select SYS_FSL_DDR_VER_47
411 select SYS_FSL_ERRATUM_A004477
412 select SYS_FSL_ERRATUM_A005871
413 select SYS_FSL_ERRATUM_A006379
414 select SYS_FSL_ERRATUM_A006384
415 select SYS_FSL_ERRATUM_A006475
416 select SYS_FSL_ERRATUM_A006593
417 select SYS_FSL_ERRATUM_A007075
418 select SYS_FSL_ERRATUM_A007186
419 select SYS_FSL_ERRATUM_A007212
420 select SYS_FSL_ERRATUM_A009942
421 select SYS_FSL_HAS_DDR3
422 select SYS_FSL_HAS_SEC
423 select SYS_FSL_QORIQ_CHASSIS2
424 select SYS_FSL_SEC_BE
425 select SYS_FSL_SEC_COMPAT_4
435 select SYS_FSL_DDR_VER_47
436 select SYS_FSL_ERRATUM_A004477
437 select SYS_FSL_ERRATUM_A005871
438 select SYS_FSL_ERRATUM_A006379
439 select SYS_FSL_ERRATUM_A006384
440 select SYS_FSL_ERRATUM_A006475
441 select SYS_FSL_ERRATUM_A006593
442 select SYS_FSL_ERRATUM_A007075
443 select SYS_FSL_ERRATUM_A007186
444 select SYS_FSL_ERRATUM_A007212
445 select SYS_FSL_ERRATUM_A007907
446 select SYS_FSL_ERRATUM_A009942
447 select SYS_FSL_HAS_DDR3
448 select SYS_FSL_HAS_SEC
449 select SYS_FSL_QORIQ_CHASSIS2
450 select SYS_FSL_SEC_BE
451 select SYS_FSL_SEC_COMPAT_4
459 select SYS_FSL_DDR_VER_44
460 select SYS_FSL_ERRATUM_A004477
461 select SYS_FSL_ERRATUM_A005125
462 select SYS_FSL_ERRATUM_ESDHC111
463 select SYS_FSL_HAS_DDR3
464 select SYS_FSL_HAS_SEC
465 select SYS_FSL_SEC_BE
466 select SYS_FSL_SEC_COMPAT_4
473 select SYS_FSL_DDR_VER_46
474 select SYS_FSL_ERRATUM_A004477
475 select SYS_FSL_ERRATUM_A005125
476 select SYS_FSL_ERRATUM_A005434
477 select SYS_FSL_ERRATUM_ESDHC111
478 select SYS_FSL_ERRATUM_I2C_A004447
479 select SYS_FSL_ERRATUM_IFC_A002769
480 select SYS_FSL_HAS_DDR3
481 select SYS_FSL_HAS_SEC
482 select SYS_FSL_SEC_BE
483 select SYS_FSL_SEC_COMPAT_4
484 select SYS_PPC_E500_USE_DEBUG_TLB
492 select SYS_FSL_DDR_VER_46
493 select SYS_FSL_ERRATUM_A005125
494 select SYS_FSL_ERRATUM_ESDHC111
495 select SYS_FSL_HAS_DDR3
496 select SYS_FSL_HAS_SEC
497 select SYS_FSL_SEC_BE
498 select SYS_FSL_SEC_COMPAT_6
499 select SYS_PPC_E500_USE_DEBUG_TLB
505 select SYS_FSL_ERRATUM_A004508
506 select SYS_FSL_ERRATUM_A005125
507 select SYS_FSL_HAS_DDR2
508 select SYS_FSL_HAS_DDR3
509 select SYS_FSL_HAS_SEC
510 select SYS_FSL_SEC_BE
511 select SYS_FSL_SEC_COMPAT_2
512 select SYS_PPC_E500_USE_DEBUG_TLB
519 select SYS_FSL_HAS_DDR1
524 select SYS_FSL_HAS_DDR1
525 select SYS_FSL_HAS_SEC
526 select SYS_FSL_SEC_BE
527 select SYS_FSL_SEC_COMPAT_2
532 select SYS_FSL_ERRATUM_A005125
533 select SYS_FSL_HAS_DDR2
534 select SYS_FSL_HAS_SEC
535 select SYS_FSL_SEC_BE
536 select SYS_FSL_SEC_COMPAT_2
537 select SYS_PPC_E500_USE_DEBUG_TLB
543 select SYS_FSL_ERRATUM_A005125
544 select SYS_FSL_ERRATUM_NMG_DDR120
545 select SYS_FSL_ERRATUM_NMG_LBC103
546 select SYS_FSL_ERRATUM_NMG_ETSEC129
547 select SYS_FSL_ERRATUM_I2C_A004447
548 select SYS_FSL_HAS_DDR2
549 select SYS_FSL_HAS_DDR1
550 select SYS_FSL_HAS_SEC
551 select SYS_FSL_SEC_BE
552 select SYS_FSL_SEC_COMPAT_2
553 select SYS_PPC_E500_USE_DEBUG_TLB
554 imply ENV_IS_IN_FLASH
559 select SYS_FSL_HAS_DDR1
560 select SYS_FSL_HAS_SEC
561 select SYS_FSL_SEC_BE
562 select SYS_FSL_SEC_COMPAT_2
567 select SYS_FSL_HAS_DDR1
572 select SYS_FSL_HAS_DDR2
573 select SYS_FSL_HAS_SEC
574 select SYS_FSL_SEC_BE
575 select SYS_FSL_SEC_COMPAT_2
580 select SYS_FSL_ERRATUM_A004508
581 select SYS_FSL_ERRATUM_A005125
582 select SYS_FSL_HAS_DDR3
583 select SYS_FSL_HAS_SEC
584 select SYS_FSL_SEC_BE
585 select SYS_FSL_SEC_COMPAT_2
591 select SYS_FSL_ERRATUM_A004508
592 select SYS_FSL_ERRATUM_A005125
593 select SYS_FSL_ERRATUM_DDR_115
594 select SYS_FSL_ERRATUM_DDR111_DDR134
595 select SYS_FSL_HAS_DDR2
596 select SYS_FSL_HAS_DDR3
597 select SYS_FSL_HAS_SEC
598 select SYS_FSL_SEC_BE
599 select SYS_FSL_SEC_COMPAT_2
600 select SYS_PPC_E500_USE_DEBUG_TLB
602 imply ENV_IS_IN_FLASH
607 select SYS_FSL_ERRATUM_A004477
608 select SYS_FSL_ERRATUM_A004508
609 select SYS_FSL_ERRATUM_A005125
610 select SYS_FSL_ERRATUM_A006261
611 select SYS_FSL_ERRATUM_A007075
612 select SYS_FSL_ERRATUM_ESDHC111
613 select SYS_FSL_ERRATUM_I2C_A004447
614 select SYS_FSL_ERRATUM_IFC_A002769
615 select SYS_FSL_ERRATUM_P1010_A003549
616 select SYS_FSL_ERRATUM_SEC_A003571
617 select SYS_FSL_ERRATUM_IFC_A003399
618 select SYS_FSL_HAS_DDR3
619 select SYS_FSL_HAS_SEC
620 select SYS_FSL_SEC_BE
621 select SYS_FSL_SEC_COMPAT_4
622 select SYS_PPC_E500_USE_DEBUG_TLB
631 select SYS_FSL_ERRATUM_A004508
632 select SYS_FSL_ERRATUM_A005125
633 select SYS_FSL_ERRATUM_ELBC_A001
634 select SYS_FSL_ERRATUM_ESDHC111
635 select SYS_FSL_HAS_DDR3
636 select SYS_FSL_HAS_SEC
637 select SYS_FSL_SEC_BE
638 select SYS_FSL_SEC_COMPAT_2
639 select SYS_PPC_E500_USE_DEBUG_TLB
645 select SYS_FSL_ERRATUM_A004508
646 select SYS_FSL_ERRATUM_A005125
647 select SYS_FSL_ERRATUM_ELBC_A001
648 select SYS_FSL_ERRATUM_ESDHC111
649 select SYS_FSL_HAS_DDR3
650 select SYS_FSL_HAS_SEC
651 select SYS_FSL_SEC_BE
652 select SYS_FSL_SEC_COMPAT_2
653 select SYS_PPC_E500_USE_DEBUG_TLB
660 select SYS_FSL_ERRATUM_A004508
661 select SYS_FSL_ERRATUM_A005125
662 select SYS_FSL_ERRATUM_ELBC_A001
663 select SYS_FSL_ERRATUM_ESDHC111
664 select SYS_FSL_HAS_DDR3
665 select SYS_FSL_HAS_SEC
666 select SYS_FSL_SEC_BE
667 select SYS_FSL_SEC_COMPAT_2
668 select SYS_PPC_E500_USE_DEBUG_TLB
675 select SYS_FSL_ERRATUM_A004477
676 select SYS_FSL_ERRATUM_A004508
677 select SYS_FSL_ERRATUM_A005125
678 select SYS_FSL_ERRATUM_ELBC_A001
679 select SYS_FSL_ERRATUM_ESDHC111
680 select SYS_FSL_ERRATUM_SATA_A001
681 select SYS_FSL_HAS_DDR3
682 select SYS_FSL_HAS_SEC
683 select SYS_FSL_SEC_BE
684 select SYS_FSL_SEC_COMPAT_2
685 select SYS_PPC_E500_USE_DEBUG_TLB
691 select SYS_FSL_ERRATUM_A004508
692 select SYS_FSL_ERRATUM_A005125
693 select SYS_FSL_ERRATUM_I2C_A004447
694 select SYS_FSL_HAS_DDR3
695 select SYS_FSL_HAS_SEC
696 select SYS_FSL_SEC_BE
697 select SYS_FSL_SEC_COMPAT_4
703 select SYS_FSL_ERRATUM_A004508
704 select SYS_FSL_ERRATUM_A005125
705 select SYS_FSL_ERRATUM_ELBC_A001
706 select SYS_FSL_ERRATUM_ESDHC111
707 select SYS_FSL_HAS_DDR3
708 select SYS_FSL_HAS_SEC
709 select SYS_FSL_SEC_BE
710 select SYS_FSL_SEC_COMPAT_2
711 select SYS_PPC_E500_USE_DEBUG_TLB
719 select SYS_FSL_ERRATUM_A004508
720 select SYS_FSL_ERRATUM_A005125
721 select SYS_FSL_ERRATUM_ELBC_A001
722 select SYS_FSL_ERRATUM_ESDHC111
723 select SYS_FSL_HAS_DDR3
724 select SYS_FSL_HAS_SEC
725 select SYS_FSL_SEC_BE
726 select SYS_FSL_SEC_COMPAT_2
727 select SYS_PPC_E500_USE_DEBUG_TLB
734 select SYS_FSL_ERRATUM_A004477
735 select SYS_FSL_ERRATUM_A004508
736 select SYS_FSL_ERRATUM_A005125
737 select SYS_FSL_ERRATUM_ESDHC111
738 select SYS_FSL_ERRATUM_ESDHC_A001
739 select SYS_FSL_HAS_DDR3
740 select SYS_FSL_HAS_SEC
741 select SYS_FSL_SEC_BE
742 select SYS_FSL_SEC_COMPAT_2
743 select SYS_PPC_E500_USE_DEBUG_TLB
751 select SYS_FSL_ERRATUM_A004510
752 select SYS_FSL_ERRATUM_A004849
753 select SYS_FSL_ERRATUM_A006261
754 select SYS_FSL_ERRATUM_CPU_A003999
755 select SYS_FSL_ERRATUM_DDR_A003
756 select SYS_FSL_ERRATUM_DDR_A003474
757 select SYS_FSL_ERRATUM_ESDHC111
758 select SYS_FSL_ERRATUM_I2C_A004447
759 select SYS_FSL_ERRATUM_NMG_CPU_A011
760 select SYS_FSL_ERRATUM_SRIO_A004034
761 select SYS_FSL_ERRATUM_USB14
762 select SYS_FSL_HAS_DDR3
763 select SYS_FSL_HAS_SEC
764 select SYS_FSL_QORIQ_CHASSIS1
765 select SYS_FSL_SEC_BE
766 select SYS_FSL_SEC_COMPAT_4
773 select SYS_FSL_DDR_VER_44
774 select SYS_FSL_ERRATUM_A004510
775 select SYS_FSL_ERRATUM_A004849
776 select SYS_FSL_ERRATUM_A005812
777 select SYS_FSL_ERRATUM_A006261
778 select SYS_FSL_ERRATUM_CPU_A003999
779 select SYS_FSL_ERRATUM_DDR_A003
780 select SYS_FSL_ERRATUM_DDR_A003474
781 select SYS_FSL_ERRATUM_ESDHC111
782 select SYS_FSL_ERRATUM_I2C_A004447
783 select SYS_FSL_ERRATUM_NMG_CPU_A011
784 select SYS_FSL_ERRATUM_SRIO_A004034
785 select SYS_FSL_ERRATUM_USB14
786 select SYS_FSL_HAS_DDR3
787 select SYS_FSL_HAS_SEC
788 select SYS_FSL_QORIQ_CHASSIS1
789 select SYS_FSL_SEC_BE
790 select SYS_FSL_SEC_COMPAT_4
798 select SYS_FSL_DDR_VER_44
799 select SYS_FSL_ERRATUM_A004510
800 select SYS_FSL_ERRATUM_A004580
801 select SYS_FSL_ERRATUM_A004849
802 select SYS_FSL_ERRATUM_A005812
803 select SYS_FSL_ERRATUM_A007075
804 select SYS_FSL_ERRATUM_CPC_A002
805 select SYS_FSL_ERRATUM_CPC_A003
806 select SYS_FSL_ERRATUM_CPU_A003999
807 select SYS_FSL_ERRATUM_DDR_A003
808 select SYS_FSL_ERRATUM_DDR_A003474
809 select SYS_FSL_ERRATUM_ELBC_A001
810 select SYS_FSL_ERRATUM_ESDHC111
811 select SYS_FSL_ERRATUM_ESDHC13
812 select SYS_FSL_ERRATUM_ESDHC135
813 select SYS_FSL_ERRATUM_I2C_A004447
814 select SYS_FSL_ERRATUM_NMG_CPU_A011
815 select SYS_FSL_ERRATUM_SRIO_A004034
816 select SYS_P4080_ERRATUM_CPU22
817 select SYS_P4080_ERRATUM_PCIE_A003
818 select SYS_P4080_ERRATUM_SERDES8
819 select SYS_P4080_ERRATUM_SERDES9
820 select SYS_P4080_ERRATUM_SERDES_A001
821 select SYS_P4080_ERRATUM_SERDES_A005
822 select SYS_FSL_HAS_DDR3
823 select SYS_FSL_HAS_SEC
824 select SYS_FSL_QORIQ_CHASSIS1
825 select SYS_FSL_SEC_BE
826 select SYS_FSL_SEC_COMPAT_4
834 select SYS_FSL_DDR_VER_44
835 select SYS_FSL_ERRATUM_A004510
836 select SYS_FSL_ERRATUM_A006261
837 select SYS_FSL_ERRATUM_DDR_A003
838 select SYS_FSL_ERRATUM_DDR_A003474
839 select SYS_FSL_ERRATUM_ESDHC111
840 select SYS_FSL_ERRATUM_I2C_A004447
841 select SYS_FSL_ERRATUM_SRIO_A004034
842 select SYS_FSL_ERRATUM_USB14
843 select SYS_FSL_HAS_DDR3
844 select SYS_FSL_HAS_SEC
845 select SYS_FSL_QORIQ_CHASSIS1
846 select SYS_FSL_SEC_BE
847 select SYS_FSL_SEC_COMPAT_4
856 select SYS_FSL_DDR_VER_44
857 select SYS_FSL_ERRATUM_A004510
858 select SYS_FSL_ERRATUM_A004699
859 select SYS_FSL_ERRATUM_A005812
860 select SYS_FSL_ERRATUM_A006261
861 select SYS_FSL_ERRATUM_DDR_A003
862 select SYS_FSL_ERRATUM_DDR_A003474
863 select SYS_FSL_ERRATUM_ESDHC111
864 select SYS_FSL_ERRATUM_USB14
865 select SYS_FSL_HAS_DDR3
866 select SYS_FSL_HAS_SEC
867 select SYS_FSL_QORIQ_CHASSIS1
868 select SYS_FSL_SEC_BE
869 select SYS_FSL_SEC_COMPAT_4
874 config ARCH_QEMU_E500
881 select SYS_FSL_DDR_VER_50
882 select SYS_FSL_ERRATUM_A008378
883 select SYS_FSL_ERRATUM_A009663
884 select SYS_FSL_ERRATUM_A009942
885 select SYS_FSL_ERRATUM_ESDHC111
886 select SYS_FSL_HAS_DDR3
887 select SYS_FSL_HAS_DDR4
888 select SYS_FSL_HAS_SEC
889 select SYS_FSL_QORIQ_CHASSIS2
890 select SYS_FSL_SEC_BE
891 select SYS_FSL_SEC_COMPAT_5
899 select SYS_FSL_DDR_VER_50
900 select SYS_FSL_ERRATUM_A008378
901 select SYS_FSL_ERRATUM_A009663
902 select SYS_FSL_ERRATUM_A009942
903 select SYS_FSL_ERRATUM_ESDHC111
904 select SYS_FSL_HAS_DDR3
905 select SYS_FSL_HAS_DDR4
906 select SYS_FSL_HAS_SEC
907 select SYS_FSL_QORIQ_CHASSIS2
908 select SYS_FSL_SEC_BE
909 select SYS_FSL_SEC_COMPAT_5
918 select SYS_FSL_DDR_VER_50
919 select SYS_FSL_ERRATUM_A008044
920 select SYS_FSL_ERRATUM_A008378
921 select SYS_FSL_ERRATUM_A009663
922 select SYS_FSL_ERRATUM_A009942
923 select SYS_FSL_ERRATUM_ESDHC111
924 select SYS_FSL_HAS_DDR3
925 select SYS_FSL_HAS_DDR4
926 select SYS_FSL_HAS_SEC
927 select SYS_FSL_QORIQ_CHASSIS2
928 select SYS_FSL_SEC_BE
929 select SYS_FSL_SEC_COMPAT_5
938 select SYS_FSL_DDR_VER_50
939 select SYS_FSL_ERRATUM_A008044
940 select SYS_FSL_ERRATUM_A008378
941 select SYS_FSL_ERRATUM_A009663
942 select SYS_FSL_ERRATUM_A009942
943 select SYS_FSL_ERRATUM_ESDHC111
944 select SYS_FSL_HAS_DDR3
945 select SYS_FSL_HAS_DDR4
946 select SYS_FSL_HAS_SEC
947 select SYS_FSL_QORIQ_CHASSIS2
948 select SYS_FSL_SEC_BE
949 select SYS_FSL_SEC_COMPAT_5
959 select SYS_FSL_DDR_VER_47
960 select SYS_FSL_ERRATUM_A006379
961 select SYS_FSL_ERRATUM_A006593
962 select SYS_FSL_ERRATUM_A007186
963 select SYS_FSL_ERRATUM_A007212
964 select SYS_FSL_ERRATUM_A007815
965 select SYS_FSL_ERRATUM_A007907
966 select SYS_FSL_ERRATUM_A009942
967 select SYS_FSL_ERRATUM_ESDHC111
968 select SYS_FSL_HAS_DDR3
969 select SYS_FSL_HAS_SEC
970 select SYS_FSL_QORIQ_CHASSIS2
971 select SYS_FSL_SEC_BE
972 select SYS_FSL_SEC_COMPAT_4
982 select SYS_FSL_DDR_VER_47
983 select SYS_FSL_ERRATUM_A006379
984 select SYS_FSL_ERRATUM_A006593
985 select SYS_FSL_ERRATUM_A007186
986 select SYS_FSL_ERRATUM_A007212
987 select SYS_FSL_ERRATUM_A009942
988 select SYS_FSL_ERRATUM_ESDHC111
989 select SYS_FSL_HAS_DDR3
990 select SYS_FSL_HAS_SEC
991 select SYS_FSL_QORIQ_CHASSIS2
992 select SYS_FSL_SEC_BE
993 select SYS_FSL_SEC_COMPAT_4
1002 select SYS_FSL_DDR_VER_47
1003 select SYS_FSL_ERRATUM_A004468
1004 select SYS_FSL_ERRATUM_A005871
1005 select SYS_FSL_ERRATUM_A006379
1006 select SYS_FSL_ERRATUM_A006593
1007 select SYS_FSL_ERRATUM_A007186
1008 select SYS_FSL_ERRATUM_A007798
1009 select SYS_FSL_ERRATUM_A009942
1010 select SYS_FSL_HAS_DDR3
1011 select SYS_FSL_HAS_SEC
1012 select SYS_FSL_QORIQ_CHASSIS2
1013 select SYS_FSL_SEC_BE
1014 select SYS_FSL_SEC_COMPAT_4
1024 select SYS_FSL_DDR_VER_47
1025 select SYS_FSL_ERRATUM_A004468
1026 select SYS_FSL_ERRATUM_A005871
1027 select SYS_FSL_ERRATUM_A006261
1028 select SYS_FSL_ERRATUM_A006379
1029 select SYS_FSL_ERRATUM_A006593
1030 select SYS_FSL_ERRATUM_A007186
1031 select SYS_FSL_ERRATUM_A007798
1032 select SYS_FSL_ERRATUM_A007815
1033 select SYS_FSL_ERRATUM_A007907
1034 select SYS_FSL_ERRATUM_A009942
1035 select SYS_FSL_HAS_DDR3
1036 select SYS_FSL_HAS_SEC
1037 select SYS_FSL_QORIQ_CHASSIS2
1038 select SYS_FSL_SEC_BE
1039 select SYS_FSL_SEC_COMPAT_4
1052 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1057 Enble PowerPC E500MC core
1062 Enable PowerPC E6500 core
1067 Use Freescale common code for Local Access Window
1072 Enable Freescale Secure Boot feature. Normally selected
1073 by defconfig. If unsure, do not change.
1076 int "Maximum number of CPUs permitted for MPC85xx"
1077 default 12 if ARCH_T4240
1078 default 8 if ARCH_P4080 || \
1080 default 4 if ARCH_B4860 || \
1088 default 2 if ARCH_B4420 || \
1103 Set this number to the maximum number of possible CPUs in the SoC.
1104 SoCs may have multiple clusters with each cluster may have multiple
1105 ports. If some ports are reserved but higher ports are used for
1106 cores, count the reserved ports. This will allocate enough memory
1107 in spin table to properly handle all cores.
1109 config SYS_CCSRBAR_DEFAULT
1110 hex "Default CCSRBAR address"
1111 default 0xff700000 if ARCH_BSC9131 || \
1132 default 0xff600000 if ARCH_P1023
1133 default 0xfe000000 if ARCH_B4420 || \
1148 default 0xe0000000 if ARCH_QEMU_E500
1150 Default value of CCSRBAR comes from power-on-reset. It
1151 is fixed on each SoC. Some SoCs can have different value
1152 if changed by pre-boot regime. The value here must match
1153 the current value in SoC. If not sure, do not change.
1155 config SYS_FSL_ERRATUM_A004468
1158 config SYS_FSL_ERRATUM_A004477
1161 config SYS_FSL_ERRATUM_A004508
1164 config SYS_FSL_ERRATUM_A004580
1167 config SYS_FSL_ERRATUM_A004699
1170 config SYS_FSL_ERRATUM_A004849
1173 config SYS_FSL_ERRATUM_A004510
1176 config SYS_FSL_ERRATUM_A004510_SVR_REV
1178 depends on SYS_FSL_ERRATUM_A004510
1179 default 0x20 if ARCH_P4080
1182 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1184 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1187 config SYS_FSL_ERRATUM_A005125
1190 config SYS_FSL_ERRATUM_A005434
1193 config SYS_FSL_ERRATUM_A005812
1196 config SYS_FSL_ERRATUM_A005871
1199 config SYS_FSL_ERRATUM_A006261
1202 config SYS_FSL_ERRATUM_A006379
1205 config SYS_FSL_ERRATUM_A006384
1208 config SYS_FSL_ERRATUM_A006475
1211 config SYS_FSL_ERRATUM_A006593
1214 config SYS_FSL_ERRATUM_A007075
1217 config SYS_FSL_ERRATUM_A007186
1220 config SYS_FSL_ERRATUM_A007212
1223 config SYS_FSL_ERRATUM_A007815
1226 config SYS_FSL_ERRATUM_A007798
1229 config SYS_FSL_ERRATUM_A007907
1232 config SYS_FSL_ERRATUM_A008044
1235 config SYS_FSL_ERRATUM_CPC_A002
1238 config SYS_FSL_ERRATUM_CPC_A003
1241 config SYS_FSL_ERRATUM_CPU_A003999
1244 config SYS_FSL_ERRATUM_ELBC_A001
1247 config SYS_FSL_ERRATUM_I2C_A004447
1250 config SYS_FSL_A004447_SVR_REV
1252 depends on SYS_FSL_ERRATUM_I2C_A004447
1253 default 0x00 if ARCH_MPC8548
1254 default 0x10 if ARCH_P1010
1255 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1256 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1258 config SYS_FSL_ERRATUM_IFC_A002769
1261 config SYS_FSL_ERRATUM_IFC_A003399
1264 config SYS_FSL_ERRATUM_NMG_CPU_A011
1267 config SYS_FSL_ERRATUM_NMG_ETSEC129
1270 config SYS_FSL_ERRATUM_NMG_LBC103
1273 config SYS_FSL_ERRATUM_P1010_A003549
1276 config SYS_FSL_ERRATUM_SATA_A001
1279 config SYS_FSL_ERRATUM_SEC_A003571
1282 config SYS_FSL_ERRATUM_SRIO_A004034
1285 config SYS_FSL_ERRATUM_USB14
1288 config SYS_P4080_ERRATUM_CPU22
1291 config SYS_P4080_ERRATUM_PCIE_A003
1294 config SYS_P4080_ERRATUM_SERDES8
1297 config SYS_P4080_ERRATUM_SERDES9
1300 config SYS_P4080_ERRATUM_SERDES_A001
1303 config SYS_P4080_ERRATUM_SERDES_A005
1306 config SYS_FSL_QORIQ_CHASSIS1
1309 config SYS_FSL_QORIQ_CHASSIS2
1312 config SYS_FSL_NUM_LAWS
1313 int "Number of local access windows"
1315 default 32 if ARCH_B4420 || \
1326 default 16 if ARCH_T1023 || \
1330 default 12 if ARCH_BSC9131 || \
1344 default 10 if ARCH_MPC8544 || \
1348 default 8 if ARCH_MPC8540 || \
1353 Number of local access windows. This is fixed per SoC.
1354 If not sure, do not change.
1356 config SYS_FSL_THREADS_PER_CORE
1361 config SYS_NUM_TLBCAMS
1362 int "Number of TLB CAM entries"
1363 default 64 if E500MC
1366 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1367 16 for other E500 SoCs.
1372 config SYS_PPC_E500_USE_DEBUG_TLB
1381 config SYS_PPC_E500_DEBUG_TLB
1382 int "Temporary TLB entry for external debugger"
1383 depends on SYS_PPC_E500_USE_DEBUG_TLB
1384 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1385 default 1 if ARCH_MPC8536
1386 default 2 if ARCH_MPC8572 || \
1394 default 3 if ARCH_P1010 || \
1398 Select a temporary TLB entry to be used during boot to work
1399 around limitations in e500v1 and e500v2 external debugger
1400 support. This reduces the portions of the boot code where
1401 breakpoints and single stepping do not work. The value of this
1402 symbol should be set to the TLB1 entry to be used for this
1403 purpose. If unsure, do not change.
1405 config SYS_FSL_IFC_CLK_DIV
1406 int "Divider of platform clock"
1408 default 2 if ARCH_B4420 || \
1418 Defines divider of platform clock(clock input to
1421 config SYS_FSL_LBC_CLK_DIV
1422 int "Divider of platform clock"
1423 depends on FSL_ELBC || ARCH_MPC8540 || \
1424 ARCH_MPC8548 || ARCH_MPC8541 || \
1425 ARCH_MPC8555 || ARCH_MPC8560 || \
1428 default 2 if ARCH_P2041 || \
1436 Defines divider of platform clock(clock input to
1439 source "board/freescale/b4860qds/Kconfig"
1440 source "board/freescale/bsc9131rdb/Kconfig"
1441 source "board/freescale/bsc9132qds/Kconfig"
1442 source "board/freescale/c29xpcie/Kconfig"
1443 source "board/freescale/corenet_ds/Kconfig"
1444 source "board/freescale/mpc8536ds/Kconfig"
1445 source "board/freescale/mpc8541cds/Kconfig"
1446 source "board/freescale/mpc8544ds/Kconfig"
1447 source "board/freescale/mpc8548cds/Kconfig"
1448 source "board/freescale/mpc8555cds/Kconfig"
1449 source "board/freescale/mpc8568mds/Kconfig"
1450 source "board/freescale/mpc8569mds/Kconfig"
1451 source "board/freescale/mpc8572ds/Kconfig"
1452 source "board/freescale/p1010rdb/Kconfig"
1453 source "board/freescale/p1022ds/Kconfig"
1454 source "board/freescale/p1023rdb/Kconfig"
1455 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1456 source "board/freescale/p1_twr/Kconfig"
1457 source "board/freescale/p2041rdb/Kconfig"
1458 source "board/freescale/qemu-ppce500/Kconfig"
1459 source "board/freescale/t102xqds/Kconfig"
1460 source "board/freescale/t102xrdb/Kconfig"
1461 source "board/freescale/t1040qds/Kconfig"
1462 source "board/freescale/t104xrdb/Kconfig"
1463 source "board/freescale/t208xqds/Kconfig"
1464 source "board/freescale/t208xrdb/Kconfig"
1465 source "board/freescale/t4qds/Kconfig"
1466 source "board/freescale/t4rdb/Kconfig"
1467 source "board/gdsys/p1022/Kconfig"
1468 source "board/keymile/kmp204x/Kconfig"
1469 source "board/sbc8548/Kconfig"
1470 source "board/socrates/Kconfig"
1471 source "board/varisys/cyrus/Kconfig"
1472 source "board/xes/xpedite520x/Kconfig"
1473 source "board/xes/xpedite537x/Kconfig"
1474 source "board/xes/xpedite550x/Kconfig"
1475 source "board/Arcturus/ucp1020/Kconfig"