8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_B4420QDS
28 bool "Support B4420QDS"
34 config TARGET_B4860QDS
35 bool "Support B4860QDS"
37 select BOARD_LATE_INIT if CHAIN_OF_TRUST
42 config TARGET_BSC9131RDB
43 bool "Support BSC9131RDB"
46 select BOARD_EARLY_INIT_F
48 config TARGET_BSC9132QDS
49 bool "Support BSC9132QDS"
51 select BOARD_LATE_INIT if CHAIN_OF_TRUST
53 select BOARD_EARLY_INIT_F
55 config TARGET_C29XPCIE
56 bool "Support C29XPCIE"
58 select BOARD_LATE_INIT if CHAIN_OF_TRUST
65 bool "Support P3041DS"
68 select BOARD_LATE_INIT if CHAIN_OF_TRUST
73 bool "Support P4080DS"
76 select BOARD_LATE_INIT if CHAIN_OF_TRUST
81 bool "Support P5020DS"
84 select BOARD_LATE_INIT if CHAIN_OF_TRUST
89 bool "Support P5040DS"
92 select BOARD_LATE_INIT if CHAIN_OF_TRUST
96 config TARGET_MPC8536DS
97 bool "Support MPC8536DS"
99 # Use DDR3 controller with DDR2 DIMMs on this board
100 select SYS_FSL_DDRC_GEN3
104 config TARGET_MPC8541CDS
105 bool "Support MPC8541CDS"
108 config TARGET_MPC8544DS
109 bool "Support MPC8544DS"
113 config TARGET_MPC8548CDS
114 bool "Support MPC8548CDS"
117 config TARGET_MPC8555CDS
118 bool "Support MPC8555CDS"
121 config TARGET_MPC8568MDS
122 bool "Support MPC8568MDS"
125 config TARGET_MPC8569MDS
126 bool "Support MPC8569MDS"
129 config TARGET_MPC8572DS
130 bool "Support MPC8572DS"
132 # Use DDR3 controller with DDR2 DIMMs on this board
133 select SYS_FSL_DDRC_GEN3
137 config TARGET_P1010RDB_PA
138 bool "Support P1010RDB_PA"
140 select BOARD_LATE_INIT if CHAIN_OF_TRUST
147 config TARGET_P1010RDB_PB
148 bool "Support P1010RDB_PB"
150 select BOARD_LATE_INIT if CHAIN_OF_TRUST
157 config TARGET_P1022DS
158 bool "Support P1022DS"
165 config TARGET_P1023RDB
166 bool "Support P1023RDB"
171 config TARGET_P1020MBG
172 bool "Support P1020MBG-PC"
180 config TARGET_P1020RDB_PC
181 bool "Support P1020RDB-PC"
189 config TARGET_P1020RDB_PD
190 bool "Support P1020RDB-PD"
198 config TARGET_P1020UTM
199 bool "Support P1020UTM"
207 config TARGET_P1021RDB
208 bool "Support P1021RDB"
216 config TARGET_P1024RDB
217 bool "Support P1024RDB"
225 config TARGET_P1025RDB
226 bool "Support P1025RDB"
234 config TARGET_P2020RDB
235 bool "Support P2020RDB-PC"
244 bool "Support p1_twr"
247 config TARGET_P2041RDB
248 bool "Support P2041RDB"
250 select BOARD_LATE_INIT if CHAIN_OF_TRUST
255 config TARGET_QEMU_PPCE500
256 bool "Support qemu-ppce500"
257 select ARCH_QEMU_E500
260 config TARGET_T1024QDS
261 bool "Support T1024QDS"
263 select BOARD_LATE_INIT if CHAIN_OF_TRUST
270 config TARGET_T1023RDB
271 bool "Support T1023RDB"
273 select BOARD_LATE_INIT if CHAIN_OF_TRUST
279 config TARGET_T1024RDB
280 bool "Support T1024RDB"
282 select BOARD_LATE_INIT if CHAIN_OF_TRUST
288 config TARGET_T1040QDS
289 bool "Support T1040QDS"
291 select BOARD_LATE_INIT if CHAIN_OF_TRUST
297 config TARGET_T1040RDB
298 bool "Support T1040RDB"
300 select BOARD_LATE_INIT if CHAIN_OF_TRUST
306 config TARGET_T1040D4RDB
307 bool "Support T1040D4RDB"
309 select BOARD_LATE_INIT if CHAIN_OF_TRUST
315 config TARGET_T1042RDB
316 bool "Support T1042RDB"
318 select BOARD_LATE_INIT if CHAIN_OF_TRUST
323 config TARGET_T1042D4RDB
324 bool "Support T1042D4RDB"
326 select BOARD_LATE_INIT if CHAIN_OF_TRUST
332 config TARGET_T1042RDB_PI
333 bool "Support T1042RDB_PI"
335 select BOARD_LATE_INIT if CHAIN_OF_TRUST
341 config TARGET_T2080QDS
342 bool "Support T2080QDS"
344 select BOARD_LATE_INIT if CHAIN_OF_TRUST
349 config TARGET_T2080RDB
350 bool "Support T2080RDB"
352 select BOARD_LATE_INIT if CHAIN_OF_TRUST
358 config TARGET_T2081QDS
359 bool "Support T2081QDS"
364 config TARGET_T4160QDS
365 bool "Support T4160QDS"
367 select BOARD_LATE_INIT if CHAIN_OF_TRUST
373 config TARGET_T4160RDB
374 bool "Support T4160RDB"
380 config TARGET_T4240QDS
381 bool "Support T4240QDS"
383 select BOARD_LATE_INIT if CHAIN_OF_TRUST
389 config TARGET_T4240RDB
390 bool "Support T4240RDB"
397 config TARGET_CONTROLCENTERD
398 bool "Support controlcenterd"
401 config TARGET_KMP204X
402 bool "Support kmp204x"
408 config TARGET_XPEDITE520X
409 bool "Support xpedite520x"
412 config TARGET_XPEDITE537X
413 bool "Support xpedite537x"
415 # Use DDR3 controller with DDR2 DIMMs on this board
416 select SYS_FSL_DDRC_GEN3
418 config TARGET_XPEDITE550X
419 bool "Support xpedite550x"
422 config TARGET_UCP1020
423 bool "Support uCP1020"
428 config TARGET_CYRUS_P5020
429 bool "Support Varisys Cyrus P5020"
434 config TARGET_CYRUS_P5040
435 bool "Support Varisys Cyrus P5040"
447 select SYS_FSL_DDR_VER_47
448 select SYS_FSL_ERRATUM_A004477
449 select SYS_FSL_ERRATUM_A005871
450 select SYS_FSL_ERRATUM_A006379
451 select SYS_FSL_ERRATUM_A006384
452 select SYS_FSL_ERRATUM_A006475
453 select SYS_FSL_ERRATUM_A006593
454 select SYS_FSL_ERRATUM_A007075
455 select SYS_FSL_ERRATUM_A007186
456 select SYS_FSL_ERRATUM_A007212
457 select SYS_FSL_ERRATUM_A009942
458 select SYS_FSL_HAS_DDR3
459 select SYS_FSL_HAS_SEC
460 select SYS_FSL_QORIQ_CHASSIS2
461 select SYS_FSL_SEC_BE
462 select SYS_FSL_SEC_COMPAT_4
474 select SYS_FSL_DDR_VER_47
475 select SYS_FSL_ERRATUM_A004477
476 select SYS_FSL_ERRATUM_A005871
477 select SYS_FSL_ERRATUM_A006379
478 select SYS_FSL_ERRATUM_A006384
479 select SYS_FSL_ERRATUM_A006475
480 select SYS_FSL_ERRATUM_A006593
481 select SYS_FSL_ERRATUM_A007075
482 select SYS_FSL_ERRATUM_A007186
483 select SYS_FSL_ERRATUM_A007212
484 select SYS_FSL_ERRATUM_A007907
485 select SYS_FSL_ERRATUM_A009942
486 select SYS_FSL_HAS_DDR3
487 select SYS_FSL_HAS_SEC
488 select SYS_FSL_QORIQ_CHASSIS2
489 select SYS_FSL_SEC_BE
490 select SYS_FSL_SEC_COMPAT_4
500 select SYS_FSL_DDR_VER_44
501 select SYS_FSL_ERRATUM_A004477
502 select SYS_FSL_ERRATUM_A005125
503 select SYS_FSL_ERRATUM_ESDHC111
504 select SYS_FSL_HAS_DDR3
505 select SYS_FSL_HAS_SEC
506 select SYS_FSL_SEC_BE
507 select SYS_FSL_SEC_COMPAT_4
516 select SYS_FSL_DDR_VER_46
517 select SYS_FSL_ERRATUM_A004477
518 select SYS_FSL_ERRATUM_A005125
519 select SYS_FSL_ERRATUM_A005434
520 select SYS_FSL_ERRATUM_ESDHC111
521 select SYS_FSL_ERRATUM_I2C_A004447
522 select SYS_FSL_ERRATUM_IFC_A002769
523 select SYS_FSL_HAS_DDR3
524 select SYS_FSL_HAS_SEC
525 select SYS_FSL_SEC_BE
526 select SYS_FSL_SEC_COMPAT_4
527 select SYS_PPC_E500_USE_DEBUG_TLB
538 select SYS_FSL_DDR_VER_46
539 select SYS_FSL_ERRATUM_A005125
540 select SYS_FSL_ERRATUM_ESDHC111
541 select SYS_FSL_HAS_DDR3
542 select SYS_FSL_HAS_SEC
543 select SYS_FSL_SEC_BE
544 select SYS_FSL_SEC_COMPAT_6
545 select SYS_PPC_E500_USE_DEBUG_TLB
554 select SYS_FSL_ERRATUM_A004508
555 select SYS_FSL_ERRATUM_A005125
556 select SYS_FSL_HAS_DDR2
557 select SYS_FSL_HAS_DDR3
558 select SYS_FSL_HAS_SEC
559 select SYS_FSL_SEC_BE
560 select SYS_FSL_SEC_COMPAT_2
561 select SYS_PPC_E500_USE_DEBUG_TLB
570 select SYS_FSL_HAS_DDR1
575 select SYS_FSL_HAS_DDR1
576 select SYS_FSL_HAS_SEC
577 select SYS_FSL_SEC_BE
578 select SYS_FSL_SEC_COMPAT_2
583 select SYS_FSL_ERRATUM_A005125
584 select SYS_FSL_HAS_DDR2
585 select SYS_FSL_HAS_SEC
586 select SYS_FSL_SEC_BE
587 select SYS_FSL_SEC_COMPAT_2
588 select SYS_PPC_E500_USE_DEBUG_TLB
594 select SYS_FSL_ERRATUM_A005125
595 select SYS_FSL_ERRATUM_NMG_DDR120
596 select SYS_FSL_ERRATUM_NMG_LBC103
597 select SYS_FSL_ERRATUM_NMG_ETSEC129
598 select SYS_FSL_ERRATUM_I2C_A004447
599 select SYS_FSL_HAS_DDR2
600 select SYS_FSL_HAS_DDR1
601 select SYS_FSL_HAS_SEC
602 select SYS_FSL_SEC_BE
603 select SYS_FSL_SEC_COMPAT_2
604 select SYS_PPC_E500_USE_DEBUG_TLB
610 select SYS_FSL_HAS_DDR1
611 select SYS_FSL_HAS_SEC
612 select SYS_FSL_SEC_BE
613 select SYS_FSL_SEC_COMPAT_2
618 select SYS_FSL_HAS_DDR1
623 select SYS_FSL_HAS_DDR2
624 select SYS_FSL_HAS_SEC
625 select SYS_FSL_SEC_BE
626 select SYS_FSL_SEC_COMPAT_2
631 select SYS_FSL_ERRATUM_A004508
632 select SYS_FSL_ERRATUM_A005125
633 select SYS_FSL_HAS_DDR3
634 select SYS_FSL_HAS_SEC
635 select SYS_FSL_SEC_BE
636 select SYS_FSL_SEC_COMPAT_2
643 select SYS_FSL_ERRATUM_A004508
644 select SYS_FSL_ERRATUM_A005125
645 select SYS_FSL_ERRATUM_DDR_115
646 select SYS_FSL_ERRATUM_DDR111_DDR134
647 select SYS_FSL_HAS_DDR2
648 select SYS_FSL_HAS_DDR3
649 select SYS_FSL_HAS_SEC
650 select SYS_FSL_SEC_BE
651 select SYS_FSL_SEC_COMPAT_2
652 select SYS_PPC_E500_USE_DEBUG_TLB
659 select SYS_FSL_ERRATUM_A004477
660 select SYS_FSL_ERRATUM_A004508
661 select SYS_FSL_ERRATUM_A005125
662 select SYS_FSL_ERRATUM_A006261
663 select SYS_FSL_ERRATUM_A007075
664 select SYS_FSL_ERRATUM_ESDHC111
665 select SYS_FSL_ERRATUM_I2C_A004447
666 select SYS_FSL_ERRATUM_IFC_A002769
667 select SYS_FSL_ERRATUM_P1010_A003549
668 select SYS_FSL_ERRATUM_SEC_A003571
669 select SYS_FSL_ERRATUM_IFC_A003399
670 select SYS_FSL_HAS_DDR3
671 select SYS_FSL_HAS_SEC
672 select SYS_FSL_SEC_BE
673 select SYS_FSL_SEC_COMPAT_4
674 select SYS_PPC_E500_USE_DEBUG_TLB
687 select SYS_FSL_ERRATUM_A004508
688 select SYS_FSL_ERRATUM_A005125
689 select SYS_FSL_ERRATUM_ELBC_A001
690 select SYS_FSL_ERRATUM_ESDHC111
691 select SYS_FSL_HAS_DDR3
692 select SYS_FSL_HAS_SEC
693 select SYS_FSL_SEC_BE
694 select SYS_FSL_SEC_COMPAT_2
695 select SYS_PPC_E500_USE_DEBUG_TLB
701 select SYS_FSL_ERRATUM_A004508
702 select SYS_FSL_ERRATUM_A005125
703 select SYS_FSL_ERRATUM_ELBC_A001
704 select SYS_FSL_ERRATUM_ESDHC111
705 select SYS_FSL_HAS_DDR3
706 select SYS_FSL_HAS_SEC
707 select SYS_FSL_SEC_BE
708 select SYS_FSL_SEC_COMPAT_2
709 select SYS_PPC_E500_USE_DEBUG_TLB
720 select SYS_FSL_ERRATUM_A004508
721 select SYS_FSL_ERRATUM_A005125
722 select SYS_FSL_ERRATUM_ELBC_A001
723 select SYS_FSL_ERRATUM_ESDHC111
724 select SYS_FSL_HAS_DDR3
725 select SYS_FSL_HAS_SEC
726 select SYS_FSL_SEC_BE
727 select SYS_FSL_SEC_COMPAT_2
728 select SYS_PPC_E500_USE_DEBUG_TLB
739 select SYS_FSL_ERRATUM_A004477
740 select SYS_FSL_ERRATUM_A004508
741 select SYS_FSL_ERRATUM_A005125
742 select SYS_FSL_ERRATUM_ELBC_A001
743 select SYS_FSL_ERRATUM_ESDHC111
744 select SYS_FSL_ERRATUM_SATA_A001
745 select SYS_FSL_HAS_DDR3
746 select SYS_FSL_HAS_SEC
747 select SYS_FSL_SEC_BE
748 select SYS_FSL_SEC_COMPAT_2
749 select SYS_PPC_E500_USE_DEBUG_TLB
755 select SYS_FSL_ERRATUM_A004508
756 select SYS_FSL_ERRATUM_A005125
757 select SYS_FSL_ERRATUM_I2C_A004447
758 select SYS_FSL_HAS_DDR3
759 select SYS_FSL_HAS_SEC
760 select SYS_FSL_SEC_BE
761 select SYS_FSL_SEC_COMPAT_4
767 select SYS_FSL_ERRATUM_A004508
768 select SYS_FSL_ERRATUM_A005125
769 select SYS_FSL_ERRATUM_ELBC_A001
770 select SYS_FSL_ERRATUM_ESDHC111
771 select SYS_FSL_HAS_DDR3
772 select SYS_FSL_HAS_SEC
773 select SYS_FSL_SEC_BE
774 select SYS_FSL_SEC_COMPAT_2
775 select SYS_PPC_E500_USE_DEBUG_TLB
787 select SYS_FSL_ERRATUM_A004508
788 select SYS_FSL_ERRATUM_A005125
789 select SYS_FSL_ERRATUM_ELBC_A001
790 select SYS_FSL_ERRATUM_ESDHC111
791 select SYS_FSL_HAS_DDR3
792 select SYS_FSL_HAS_SEC
793 select SYS_FSL_SEC_BE
794 select SYS_FSL_SEC_COMPAT_2
795 select SYS_PPC_E500_USE_DEBUG_TLB
803 select SYS_FSL_ERRATUM_A004477
804 select SYS_FSL_ERRATUM_A004508
805 select SYS_FSL_ERRATUM_A005125
806 select SYS_FSL_ERRATUM_ESDHC111
807 select SYS_FSL_ERRATUM_ESDHC_A001
808 select SYS_FSL_HAS_DDR3
809 select SYS_FSL_HAS_SEC
810 select SYS_FSL_SEC_BE
811 select SYS_FSL_SEC_COMPAT_2
812 select SYS_PPC_E500_USE_DEBUG_TLB
822 select SYS_FSL_ERRATUM_A004510
823 select SYS_FSL_ERRATUM_A004849
824 select SYS_FSL_ERRATUM_A006261
825 select SYS_FSL_ERRATUM_CPU_A003999
826 select SYS_FSL_ERRATUM_DDR_A003
827 select SYS_FSL_ERRATUM_DDR_A003474
828 select SYS_FSL_ERRATUM_ESDHC111
829 select SYS_FSL_ERRATUM_I2C_A004447
830 select SYS_FSL_ERRATUM_NMG_CPU_A011
831 select SYS_FSL_ERRATUM_SRIO_A004034
832 select SYS_FSL_ERRATUM_USB14
833 select SYS_FSL_HAS_DDR3
834 select SYS_FSL_HAS_SEC
835 select SYS_FSL_QORIQ_CHASSIS1
836 select SYS_FSL_SEC_BE
837 select SYS_FSL_SEC_COMPAT_4
845 select SYS_FSL_DDR_VER_44
846 select SYS_FSL_ERRATUM_A004510
847 select SYS_FSL_ERRATUM_A004849
848 select SYS_FSL_ERRATUM_A005812
849 select SYS_FSL_ERRATUM_A006261
850 select SYS_FSL_ERRATUM_CPU_A003999
851 select SYS_FSL_ERRATUM_DDR_A003
852 select SYS_FSL_ERRATUM_DDR_A003474
853 select SYS_FSL_ERRATUM_ESDHC111
854 select SYS_FSL_ERRATUM_I2C_A004447
855 select SYS_FSL_ERRATUM_NMG_CPU_A011
856 select SYS_FSL_ERRATUM_SRIO_A004034
857 select SYS_FSL_ERRATUM_USB14
858 select SYS_FSL_HAS_DDR3
859 select SYS_FSL_HAS_SEC
860 select SYS_FSL_QORIQ_CHASSIS1
861 select SYS_FSL_SEC_BE
862 select SYS_FSL_SEC_COMPAT_4
873 select SYS_FSL_DDR_VER_44
874 select SYS_FSL_ERRATUM_A004510
875 select SYS_FSL_ERRATUM_A004580
876 select SYS_FSL_ERRATUM_A004849
877 select SYS_FSL_ERRATUM_A005812
878 select SYS_FSL_ERRATUM_A007075
879 select SYS_FSL_ERRATUM_CPC_A002
880 select SYS_FSL_ERRATUM_CPC_A003
881 select SYS_FSL_ERRATUM_CPU_A003999
882 select SYS_FSL_ERRATUM_DDR_A003
883 select SYS_FSL_ERRATUM_DDR_A003474
884 select SYS_FSL_ERRATUM_ELBC_A001
885 select SYS_FSL_ERRATUM_ESDHC111
886 select SYS_FSL_ERRATUM_ESDHC13
887 select SYS_FSL_ERRATUM_ESDHC135
888 select SYS_FSL_ERRATUM_I2C_A004447
889 select SYS_FSL_ERRATUM_NMG_CPU_A011
890 select SYS_FSL_ERRATUM_SRIO_A004034
891 select SYS_P4080_ERRATUM_CPU22
892 select SYS_P4080_ERRATUM_PCIE_A003
893 select SYS_P4080_ERRATUM_SERDES8
894 select SYS_P4080_ERRATUM_SERDES9
895 select SYS_P4080_ERRATUM_SERDES_A001
896 select SYS_P4080_ERRATUM_SERDES_A005
897 select SYS_FSL_HAS_DDR3
898 select SYS_FSL_HAS_SEC
899 select SYS_FSL_QORIQ_CHASSIS1
900 select SYS_FSL_SEC_BE
901 select SYS_FSL_SEC_COMPAT_4
911 select SYS_FSL_DDR_VER_44
912 select SYS_FSL_ERRATUM_A004510
913 select SYS_FSL_ERRATUM_A006261
914 select SYS_FSL_ERRATUM_DDR_A003
915 select SYS_FSL_ERRATUM_DDR_A003474
916 select SYS_FSL_ERRATUM_ESDHC111
917 select SYS_FSL_ERRATUM_I2C_A004447
918 select SYS_FSL_ERRATUM_SRIO_A004034
919 select SYS_FSL_ERRATUM_USB14
920 select SYS_FSL_HAS_DDR3
921 select SYS_FSL_HAS_SEC
922 select SYS_FSL_QORIQ_CHASSIS1
923 select SYS_FSL_SEC_BE
924 select SYS_FSL_SEC_COMPAT_4
935 select SYS_FSL_DDR_VER_44
936 select SYS_FSL_ERRATUM_A004510
937 select SYS_FSL_ERRATUM_A004699
938 select SYS_FSL_ERRATUM_A005812
939 select SYS_FSL_ERRATUM_A006261
940 select SYS_FSL_ERRATUM_DDR_A003
941 select SYS_FSL_ERRATUM_DDR_A003474
942 select SYS_FSL_ERRATUM_ESDHC111
943 select SYS_FSL_ERRATUM_USB14
944 select SYS_FSL_HAS_DDR3
945 select SYS_FSL_HAS_SEC
946 select SYS_FSL_QORIQ_CHASSIS1
947 select SYS_FSL_SEC_BE
948 select SYS_FSL_SEC_COMPAT_4
955 config ARCH_QEMU_E500
962 select SYS_FSL_DDR_VER_50
963 select SYS_FSL_ERRATUM_A008378
964 select SYS_FSL_ERRATUM_A009663
965 select SYS_FSL_ERRATUM_A009942
966 select SYS_FSL_ERRATUM_ESDHC111
967 select SYS_FSL_HAS_DDR3
968 select SYS_FSL_HAS_DDR4
969 select SYS_FSL_HAS_SEC
970 select SYS_FSL_QORIQ_CHASSIS2
971 select SYS_FSL_SEC_BE
972 select SYS_FSL_SEC_COMPAT_5
982 select SYS_FSL_DDR_VER_50
983 select SYS_FSL_ERRATUM_A008378
984 select SYS_FSL_ERRATUM_A009663
985 select SYS_FSL_ERRATUM_A009942
986 select SYS_FSL_ERRATUM_ESDHC111
987 select SYS_FSL_HAS_DDR3
988 select SYS_FSL_HAS_DDR4
989 select SYS_FSL_HAS_SEC
990 select SYS_FSL_QORIQ_CHASSIS2
991 select SYS_FSL_SEC_BE
992 select SYS_FSL_SEC_COMPAT_5
1003 select SYS_FSL_DDR_VER_50
1004 select SYS_FSL_ERRATUM_A008044
1005 select SYS_FSL_ERRATUM_A008378
1006 select SYS_FSL_ERRATUM_A009663
1007 select SYS_FSL_ERRATUM_A009942
1008 select SYS_FSL_ERRATUM_ESDHC111
1009 select SYS_FSL_HAS_DDR3
1010 select SYS_FSL_HAS_DDR4
1011 select SYS_FSL_HAS_SEC
1012 select SYS_FSL_QORIQ_CHASSIS2
1013 select SYS_FSL_SEC_BE
1014 select SYS_FSL_SEC_COMPAT_5
1026 select SYS_FSL_DDR_VER_50
1027 select SYS_FSL_ERRATUM_A008044
1028 select SYS_FSL_ERRATUM_A008378
1029 select SYS_FSL_ERRATUM_A009663
1030 select SYS_FSL_ERRATUM_A009942
1031 select SYS_FSL_ERRATUM_ESDHC111
1032 select SYS_FSL_HAS_DDR3
1033 select SYS_FSL_HAS_DDR4
1034 select SYS_FSL_HAS_SEC
1035 select SYS_FSL_QORIQ_CHASSIS2
1036 select SYS_FSL_SEC_BE
1037 select SYS_FSL_SEC_COMPAT_5
1050 select SYS_FSL_DDR_VER_47
1051 select SYS_FSL_ERRATUM_A006379
1052 select SYS_FSL_ERRATUM_A006593
1053 select SYS_FSL_ERRATUM_A007186
1054 select SYS_FSL_ERRATUM_A007212
1055 select SYS_FSL_ERRATUM_A007815
1056 select SYS_FSL_ERRATUM_A007907
1057 select SYS_FSL_ERRATUM_A009942
1058 select SYS_FSL_ERRATUM_ESDHC111
1059 select SYS_FSL_HAS_DDR3
1060 select SYS_FSL_HAS_SEC
1061 select SYS_FSL_QORIQ_CHASSIS2
1062 select SYS_FSL_SEC_BE
1063 select SYS_FSL_SEC_COMPAT_4
1076 select SYS_FSL_DDR_VER_47
1077 select SYS_FSL_ERRATUM_A006379
1078 select SYS_FSL_ERRATUM_A006593
1079 select SYS_FSL_ERRATUM_A007186
1080 select SYS_FSL_ERRATUM_A007212
1081 select SYS_FSL_ERRATUM_A009942
1082 select SYS_FSL_ERRATUM_ESDHC111
1083 select SYS_FSL_HAS_DDR3
1084 select SYS_FSL_HAS_SEC
1085 select SYS_FSL_QORIQ_CHASSIS2
1086 select SYS_FSL_SEC_BE
1087 select SYS_FSL_SEC_COMPAT_4
1098 select SYS_FSL_DDR_VER_47
1099 select SYS_FSL_ERRATUM_A004468
1100 select SYS_FSL_ERRATUM_A005871
1101 select SYS_FSL_ERRATUM_A006379
1102 select SYS_FSL_ERRATUM_A006593
1103 select SYS_FSL_ERRATUM_A007186
1104 select SYS_FSL_ERRATUM_A007798
1105 select SYS_FSL_ERRATUM_A009942
1106 select SYS_FSL_HAS_DDR3
1107 select SYS_FSL_HAS_SEC
1108 select SYS_FSL_QORIQ_CHASSIS2
1109 select SYS_FSL_SEC_BE
1110 select SYS_FSL_SEC_COMPAT_4
1123 select SYS_FSL_DDR_VER_47
1124 select SYS_FSL_ERRATUM_A004468
1125 select SYS_FSL_ERRATUM_A005871
1126 select SYS_FSL_ERRATUM_A006261
1127 select SYS_FSL_ERRATUM_A006379
1128 select SYS_FSL_ERRATUM_A006593
1129 select SYS_FSL_ERRATUM_A007186
1130 select SYS_FSL_ERRATUM_A007798
1131 select SYS_FSL_ERRATUM_A007815
1132 select SYS_FSL_ERRATUM_A007907
1133 select SYS_FSL_ERRATUM_A009942
1134 select SYS_FSL_HAS_DDR3
1135 select SYS_FSL_HAS_SEC
1136 select SYS_FSL_QORIQ_CHASSIS2
1137 select SYS_FSL_SEC_BE
1138 select SYS_FSL_SEC_COMPAT_4
1154 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1160 Enble PowerPC E500MC core
1165 Enable PowerPC E6500 core
1170 Use Freescale common code for Local Access Window
1175 Enable Freescale Secure Boot feature. Normally selected
1176 by defconfig. If unsure, do not change.
1179 int "Maximum number of CPUs permitted for MPC85xx"
1180 default 12 if ARCH_T4240
1181 default 8 if ARCH_P4080 || \
1183 default 4 if ARCH_B4860 || \
1191 default 2 if ARCH_B4420 || \
1206 Set this number to the maximum number of possible CPUs in the SoC.
1207 SoCs may have multiple clusters with each cluster may have multiple
1208 ports. If some ports are reserved but higher ports are used for
1209 cores, count the reserved ports. This will allocate enough memory
1210 in spin table to properly handle all cores.
1212 config SYS_CCSRBAR_DEFAULT
1213 hex "Default CCSRBAR address"
1214 default 0xff700000 if ARCH_BSC9131 || \
1235 default 0xff600000 if ARCH_P1023
1236 default 0xfe000000 if ARCH_B4420 || \
1251 default 0xe0000000 if ARCH_QEMU_E500
1253 Default value of CCSRBAR comes from power-on-reset. It
1254 is fixed on each SoC. Some SoCs can have different value
1255 if changed by pre-boot regime. The value here must match
1256 the current value in SoC. If not sure, do not change.
1258 config SYS_FSL_ERRATUM_A004468
1261 config SYS_FSL_ERRATUM_A004477
1264 config SYS_FSL_ERRATUM_A004508
1267 config SYS_FSL_ERRATUM_A004580
1270 config SYS_FSL_ERRATUM_A004699
1273 config SYS_FSL_ERRATUM_A004849
1276 config SYS_FSL_ERRATUM_A004510
1279 config SYS_FSL_ERRATUM_A004510_SVR_REV
1281 depends on SYS_FSL_ERRATUM_A004510
1282 default 0x20 if ARCH_P4080
1285 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1287 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1290 config SYS_FSL_ERRATUM_A005125
1293 config SYS_FSL_ERRATUM_A005434
1296 config SYS_FSL_ERRATUM_A005812
1299 config SYS_FSL_ERRATUM_A005871
1302 config SYS_FSL_ERRATUM_A006261
1305 config SYS_FSL_ERRATUM_A006379
1308 config SYS_FSL_ERRATUM_A006384
1311 config SYS_FSL_ERRATUM_A006475
1314 config SYS_FSL_ERRATUM_A006593
1317 config SYS_FSL_ERRATUM_A007075
1320 config SYS_FSL_ERRATUM_A007186
1323 config SYS_FSL_ERRATUM_A007212
1326 config SYS_FSL_ERRATUM_A007815
1329 config SYS_FSL_ERRATUM_A007798
1332 config SYS_FSL_ERRATUM_A007907
1335 config SYS_FSL_ERRATUM_A008044
1338 config SYS_FSL_ERRATUM_CPC_A002
1341 config SYS_FSL_ERRATUM_CPC_A003
1344 config SYS_FSL_ERRATUM_CPU_A003999
1347 config SYS_FSL_ERRATUM_ELBC_A001
1350 config SYS_FSL_ERRATUM_I2C_A004447
1353 config SYS_FSL_A004447_SVR_REV
1355 depends on SYS_FSL_ERRATUM_I2C_A004447
1356 default 0x00 if ARCH_MPC8548
1357 default 0x10 if ARCH_P1010
1358 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1359 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1361 config SYS_FSL_ERRATUM_IFC_A002769
1364 config SYS_FSL_ERRATUM_IFC_A003399
1367 config SYS_FSL_ERRATUM_NMG_CPU_A011
1370 config SYS_FSL_ERRATUM_NMG_ETSEC129
1373 config SYS_FSL_ERRATUM_NMG_LBC103
1376 config SYS_FSL_ERRATUM_P1010_A003549
1379 config SYS_FSL_ERRATUM_SATA_A001
1382 config SYS_FSL_ERRATUM_SEC_A003571
1385 config SYS_FSL_ERRATUM_SRIO_A004034
1388 config SYS_FSL_ERRATUM_USB14
1391 config SYS_P4080_ERRATUM_CPU22
1394 config SYS_P4080_ERRATUM_PCIE_A003
1397 config SYS_P4080_ERRATUM_SERDES8
1400 config SYS_P4080_ERRATUM_SERDES9
1403 config SYS_P4080_ERRATUM_SERDES_A001
1406 config SYS_P4080_ERRATUM_SERDES_A005
1409 config SYS_FSL_QORIQ_CHASSIS1
1412 config SYS_FSL_QORIQ_CHASSIS2
1415 config SYS_FSL_NUM_LAWS
1416 int "Number of local access windows"
1418 default 32 if ARCH_B4420 || \
1429 default 16 if ARCH_T1023 || \
1433 default 12 if ARCH_BSC9131 || \
1447 default 10 if ARCH_MPC8544 || \
1451 default 8 if ARCH_MPC8540 || \
1456 Number of local access windows. This is fixed per SoC.
1457 If not sure, do not change.
1459 config SYS_FSL_THREADS_PER_CORE
1464 config SYS_NUM_TLBCAMS
1465 int "Number of TLB CAM entries"
1466 default 64 if E500MC
1469 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1470 16 for other E500 SoCs.
1475 config SYS_PPC_E500_USE_DEBUG_TLB
1484 config SYS_PPC_E500_DEBUG_TLB
1485 int "Temporary TLB entry for external debugger"
1486 depends on SYS_PPC_E500_USE_DEBUG_TLB
1487 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1488 default 1 if ARCH_MPC8536
1489 default 2 if ARCH_MPC8572 || \
1497 default 3 if ARCH_P1010 || \
1501 Select a temporary TLB entry to be used during boot to work
1502 around limitations in e500v1 and e500v2 external debugger
1503 support. This reduces the portions of the boot code where
1504 breakpoints and single stepping do not work. The value of this
1505 symbol should be set to the TLB1 entry to be used for this
1506 purpose. If unsure, do not change.
1508 config SYS_FSL_IFC_CLK_DIV
1509 int "Divider of platform clock"
1511 default 2 if ARCH_B4420 || \
1521 Defines divider of platform clock(clock input to
1524 config SYS_FSL_LBC_CLK_DIV
1525 int "Divider of platform clock"
1526 depends on FSL_ELBC || ARCH_MPC8540 || \
1527 ARCH_MPC8548 || ARCH_MPC8541 || \
1528 ARCH_MPC8555 || ARCH_MPC8560 || \
1531 default 2 if ARCH_P2041 || \
1539 Defines divider of platform clock(clock input to
1542 source "board/freescale/b4860qds/Kconfig"
1543 source "board/freescale/bsc9131rdb/Kconfig"
1544 source "board/freescale/bsc9132qds/Kconfig"
1545 source "board/freescale/c29xpcie/Kconfig"
1546 source "board/freescale/corenet_ds/Kconfig"
1547 source "board/freescale/mpc8536ds/Kconfig"
1548 source "board/freescale/mpc8541cds/Kconfig"
1549 source "board/freescale/mpc8544ds/Kconfig"
1550 source "board/freescale/mpc8548cds/Kconfig"
1551 source "board/freescale/mpc8555cds/Kconfig"
1552 source "board/freescale/mpc8568mds/Kconfig"
1553 source "board/freescale/mpc8569mds/Kconfig"
1554 source "board/freescale/mpc8572ds/Kconfig"
1555 source "board/freescale/p1010rdb/Kconfig"
1556 source "board/freescale/p1022ds/Kconfig"
1557 source "board/freescale/p1023rdb/Kconfig"
1558 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1559 source "board/freescale/p1_twr/Kconfig"
1560 source "board/freescale/p2041rdb/Kconfig"
1561 source "board/freescale/qemu-ppce500/Kconfig"
1562 source "board/freescale/t102xqds/Kconfig"
1563 source "board/freescale/t102xrdb/Kconfig"
1564 source "board/freescale/t1040qds/Kconfig"
1565 source "board/freescale/t104xrdb/Kconfig"
1566 source "board/freescale/t208xqds/Kconfig"
1567 source "board/freescale/t208xrdb/Kconfig"
1568 source "board/freescale/t4qds/Kconfig"
1569 source "board/freescale/t4rdb/Kconfig"
1570 source "board/gdsys/p1022/Kconfig"
1571 source "board/keymile/kmp204x/Kconfig"
1572 source "board/sbc8548/Kconfig"
1573 source "board/socrates/Kconfig"
1574 source "board/varisys/cyrus/Kconfig"
1575 source "board/xes/xpedite520x/Kconfig"
1576 source "board/xes/xpedite537x/Kconfig"
1577 source "board/xes/xpedite550x/Kconfig"
1578 source "board/Arcturus/ucp1020/Kconfig"