12 bool "Support sbc8548"
15 config TARGET_SOCRATES
16 bool "Support socrates"
19 config TARGET_B4420QDS
20 bool "Support B4420QDS"
25 config TARGET_B4860QDS
26 bool "Support B4860QDS"
31 config TARGET_BSC9131RDB
32 bool "Support BSC9131RDB"
36 config TARGET_BSC9132QDS
37 bool "Support BSC9132QDS"
41 config TARGET_C29XPCIE
42 bool "Support C29XPCIE"
49 bool "Support P3041DS"
54 bool "Support P4080DS"
59 bool "Support P5020DS"
64 bool "Support P5040DS"
68 config TARGET_MPC8536DS
69 bool "Support MPC8536DS"
71 # Use DDR3 controller with DDR2 DIMMs on this board
72 select SYS_FSL_DDRC_GEN3
74 config TARGET_MPC8540ADS
75 bool "Support MPC8540ADS"
78 config TARGET_MPC8541CDS
79 bool "Support MPC8541CDS"
82 config TARGET_MPC8544DS
83 bool "Support MPC8544DS"
86 config TARGET_MPC8548CDS
87 bool "Support MPC8548CDS"
90 config TARGET_MPC8555CDS
91 bool "Support MPC8555CDS"
94 config TARGET_MPC8560ADS
95 bool "Support MPC8560ADS"
98 config TARGET_MPC8568MDS
99 bool "Support MPC8568MDS"
102 config TARGET_MPC8569MDS
103 bool "Support MPC8569MDS"
106 config TARGET_MPC8572DS
107 bool "Support MPC8572DS"
109 # Use DDR3 controller with DDR2 DIMMs on this board
110 select SYS_FSL_DDRC_GEN3
112 config TARGET_P1010RDB_PA
113 bool "Support P1010RDB_PA"
118 config TARGET_P1010RDB_PB
119 bool "Support P1010RDB_PB"
124 config TARGET_P1022DS
125 bool "Support P1022DS"
130 config TARGET_P1023RDB
131 bool "Support P1023RDB"
134 config TARGET_P1020MBG
135 bool "Support P1020MBG-PC"
140 config TARGET_P1020RDB_PC
141 bool "Support P1020RDB-PC"
146 config TARGET_P1020RDB_PD
147 bool "Support P1020RDB-PD"
152 config TARGET_P1020UTM
153 bool "Support P1020UTM"
158 config TARGET_P1021RDB
159 bool "Support P1021RDB"
164 config TARGET_P1024RDB
165 bool "Support P1024RDB"
170 config TARGET_P1025RDB
171 bool "Support P1025RDB"
176 config TARGET_P2020RDB
177 bool "Support P2020RDB-PC"
183 bool "Support p1_twr"
186 config TARGET_P2041RDB
187 bool "Support P2041RDB"
191 config TARGET_QEMU_PPCE500
192 bool "Support qemu-ppce500"
193 select ARCH_QEMU_E500
196 config TARGET_T1024QDS
197 bool "Support T1024QDS"
202 config TARGET_T1023RDB
203 bool "Support T1023RDB"
208 config TARGET_T1024RDB
209 bool "Support T1024RDB"
214 config TARGET_T1040QDS
215 bool "Support T1040QDS"
219 config TARGET_T1040RDB
220 bool "Support T1040RDB"
225 config TARGET_T1040D4RDB
226 bool "Support T1040D4RDB"
231 config TARGET_T1042RDB
232 bool "Support T1042RDB"
237 config TARGET_T1042D4RDB
238 bool "Support T1042D4RDB"
243 config TARGET_T1042RDB_PI
244 bool "Support T1042RDB_PI"
249 config TARGET_T2080QDS
250 bool "Support T2080QDS"
255 config TARGET_T2080RDB
256 bool "Support T2080RDB"
261 config TARGET_T2081QDS
262 bool "Support T2081QDS"
267 config TARGET_T4160QDS
268 bool "Support T4160QDS"
273 config TARGET_T4160RDB
274 bool "Support T4160RDB"
279 config TARGET_T4240QDS
280 bool "Support T4240QDS"
285 config TARGET_T4240RDB
286 bool "Support T4240RDB"
291 config TARGET_CONTROLCENTERD
292 bool "Support controlcenterd"
295 config TARGET_KMP204X
296 bool "Support kmp204x"
300 config TARGET_XPEDITE520X
301 bool "Support xpedite520x"
304 config TARGET_XPEDITE537X
305 bool "Support xpedite537x"
307 # Use DDR3 controller with DDR2 DIMMs on this board
308 select SYS_FSL_DDRC_GEN3
310 config TARGET_XPEDITE550X
311 bool "Support xpedite550x"
314 config TARGET_UCP1020
315 bool "Support uCP1020"
318 config TARGET_CYRUS_P5020
319 bool "Support Varisys Cyrus P5020"
323 config TARGET_CYRUS_P5040
324 bool "Support Varisys Cyrus P5040"
334 select SYS_FSL_DDR_VER_47
335 select SYS_FSL_ERRATUM_A004477
336 select SYS_FSL_ERRATUM_A005871
337 select SYS_FSL_ERRATUM_A006379
338 select SYS_FSL_ERRATUM_A006384
339 select SYS_FSL_ERRATUM_A006475
340 select SYS_FSL_ERRATUM_A006593
341 select SYS_FSL_ERRATUM_A007075
342 select SYS_FSL_ERRATUM_A007186
343 select SYS_FSL_ERRATUM_A007212
344 select SYS_FSL_ERRATUM_A009942
345 select SYS_FSL_HAS_DDR3
346 select SYS_FSL_HAS_SEC
347 select SYS_FSL_SEC_BE
348 select SYS_FSL_SEC_COMPAT_4
354 select SYS_FSL_DDR_VER_47
355 select SYS_FSL_ERRATUM_A004477
356 select SYS_FSL_ERRATUM_A005871
357 select SYS_FSL_ERRATUM_A006379
358 select SYS_FSL_ERRATUM_A006384
359 select SYS_FSL_ERRATUM_A006475
360 select SYS_FSL_ERRATUM_A006593
361 select SYS_FSL_ERRATUM_A007075
362 select SYS_FSL_ERRATUM_A007186
363 select SYS_FSL_ERRATUM_A007212
364 select SYS_FSL_ERRATUM_A009942
365 select SYS_FSL_HAS_DDR3
366 select SYS_FSL_HAS_SEC
367 select SYS_FSL_SEC_BE
368 select SYS_FSL_SEC_COMPAT_4
373 select SYS_FSL_DDR_VER_44
374 select SYS_FSL_ERRATUM_A004477
375 select SYS_FSL_ERRATUM_A005125
376 select SYS_FSL_ERRATUM_ESDHC111
377 select SYS_FSL_HAS_DDR3
378 select SYS_FSL_HAS_SEC
379 select SYS_FSL_SEC_BE
380 select SYS_FSL_SEC_COMPAT_4
385 select SYS_FSL_DDR_VER_46
386 select SYS_FSL_ERRATUM_A004477
387 select SYS_FSL_ERRATUM_A005125
388 select SYS_FSL_ERRATUM_A005434
389 select SYS_FSL_ERRATUM_ESDHC111
390 select SYS_FSL_ERRATUM_I2C_A004447
391 select SYS_FSL_ERRATUM_IFC_A002769
392 select SYS_FSL_HAS_DDR3
393 select SYS_FSL_HAS_SEC
394 select SYS_FSL_SEC_BE
395 select SYS_FSL_SEC_COMPAT_4
396 select SYS_PPC_E500_USE_DEBUG_TLB
401 select SYS_FSL_DDR_VER_46
402 select SYS_FSL_ERRATUM_A005125
403 select SYS_FSL_ERRATUM_ESDHC111
404 select SYS_FSL_HAS_DDR3
405 select SYS_FSL_HAS_SEC
406 select SYS_FSL_SEC_BE
407 select SYS_FSL_SEC_COMPAT_6
408 select SYS_PPC_E500_USE_DEBUG_TLB
413 select SYS_FSL_ERRATUM_A004508
414 select SYS_FSL_ERRATUM_A005125
415 select SYS_FSL_HAS_DDR2
416 select SYS_FSL_HAS_DDR3
417 select SYS_FSL_HAS_SEC
418 select SYS_FSL_SEC_BE
419 select SYS_FSL_SEC_COMPAT_2
420 select SYS_PPC_E500_USE_DEBUG_TLB
425 select SYS_FSL_HAS_DDR1
430 select SYS_FSL_HAS_DDR1
431 select SYS_FSL_HAS_SEC
432 select SYS_FSL_SEC_BE
433 select SYS_FSL_SEC_COMPAT_2
438 select SYS_FSL_ERRATUM_A005125
439 select SYS_FSL_HAS_DDR2
440 select SYS_FSL_HAS_SEC
441 select SYS_FSL_SEC_BE
442 select SYS_FSL_SEC_COMPAT_2
443 select SYS_PPC_E500_USE_DEBUG_TLB
448 select SYS_FSL_ERRATUM_A005125
449 select SYS_FSL_ERRATUM_NMG_DDR120
450 select SYS_FSL_ERRATUM_NMG_LBC103
451 select SYS_FSL_ERRATUM_NMG_ETSEC129
452 select SYS_FSL_ERRATUM_I2C_A004447
453 select SYS_FSL_HAS_DDR2
454 select SYS_FSL_HAS_DDR1
455 select SYS_FSL_HAS_SEC
456 select SYS_FSL_SEC_BE
457 select SYS_FSL_SEC_COMPAT_2
458 select SYS_PPC_E500_USE_DEBUG_TLB
463 select SYS_FSL_HAS_DDR1
464 select SYS_FSL_HAS_SEC
465 select SYS_FSL_SEC_BE
466 select SYS_FSL_SEC_COMPAT_2
471 select SYS_FSL_HAS_DDR1
476 select SYS_FSL_HAS_DDR2
477 select SYS_FSL_HAS_SEC
478 select SYS_FSL_SEC_BE
479 select SYS_FSL_SEC_COMPAT_2
484 select SYS_FSL_ERRATUM_A004508
485 select SYS_FSL_ERRATUM_A005125
486 select SYS_FSL_HAS_DDR3
487 select SYS_FSL_HAS_SEC
488 select SYS_FSL_SEC_BE
489 select SYS_FSL_SEC_COMPAT_2
494 select SYS_FSL_ERRATUM_A004508
495 select SYS_FSL_ERRATUM_A005125
496 select SYS_FSL_ERRATUM_DDR_115
497 select SYS_FSL_ERRATUM_DDR111_DDR134
498 select SYS_FSL_HAS_DDR2
499 select SYS_FSL_HAS_DDR3
500 select SYS_FSL_HAS_SEC
501 select SYS_FSL_SEC_BE
502 select SYS_FSL_SEC_COMPAT_2
503 select SYS_PPC_E500_USE_DEBUG_TLB
508 select SYS_FSL_ERRATUM_A004477
509 select SYS_FSL_ERRATUM_A004508
510 select SYS_FSL_ERRATUM_A005125
511 select SYS_FSL_ERRATUM_A006261
512 select SYS_FSL_ERRATUM_A007075
513 select SYS_FSL_ERRATUM_ESDHC111
514 select SYS_FSL_ERRATUM_I2C_A004447
515 select SYS_FSL_ERRATUM_IFC_A002769
516 select SYS_FSL_ERRATUM_P1010_A003549
517 select SYS_FSL_ERRATUM_SEC_A003571
518 select SYS_FSL_ERRATUM_IFC_A003399
519 select SYS_FSL_HAS_DDR3
520 select SYS_FSL_HAS_SEC
521 select SYS_FSL_SEC_BE
522 select SYS_FSL_SEC_COMPAT_4
523 select SYS_PPC_E500_USE_DEBUG_TLB
528 select SYS_FSL_ERRATUM_A004508
529 select SYS_FSL_ERRATUM_A005125
530 select SYS_FSL_ERRATUM_ELBC_A001
531 select SYS_FSL_ERRATUM_ESDHC111
532 select SYS_FSL_HAS_DDR3
533 select SYS_FSL_HAS_SEC
534 select SYS_FSL_SEC_BE
535 select SYS_FSL_SEC_COMPAT_2
536 select SYS_PPC_E500_USE_DEBUG_TLB
541 select SYS_FSL_ERRATUM_A004508
542 select SYS_FSL_ERRATUM_A005125
543 select SYS_FSL_ERRATUM_ELBC_A001
544 select SYS_FSL_ERRATUM_ESDHC111
545 select SYS_FSL_HAS_DDR3
546 select SYS_FSL_HAS_SEC
547 select SYS_FSL_SEC_BE
548 select SYS_FSL_SEC_COMPAT_2
549 select SYS_PPC_E500_USE_DEBUG_TLB
554 select SYS_FSL_ERRATUM_A004508
555 select SYS_FSL_ERRATUM_A005125
556 select SYS_FSL_ERRATUM_ELBC_A001
557 select SYS_FSL_ERRATUM_ESDHC111
558 select SYS_FSL_HAS_DDR3
559 select SYS_FSL_HAS_SEC
560 select SYS_FSL_SEC_BE
561 select SYS_FSL_SEC_COMPAT_2
562 select SYS_PPC_E500_USE_DEBUG_TLB
567 select SYS_FSL_ERRATUM_A004477
568 select SYS_FSL_ERRATUM_A004508
569 select SYS_FSL_ERRATUM_A005125
570 select SYS_FSL_ERRATUM_ELBC_A001
571 select SYS_FSL_ERRATUM_ESDHC111
572 select SYS_FSL_ERRATUM_SATA_A001
573 select SYS_FSL_HAS_DDR3
574 select SYS_FSL_HAS_SEC
575 select SYS_FSL_SEC_BE
576 select SYS_FSL_SEC_COMPAT_2
577 select SYS_PPC_E500_USE_DEBUG_TLB
582 select SYS_FSL_ERRATUM_A004508
583 select SYS_FSL_ERRATUM_A005125
584 select SYS_FSL_ERRATUM_I2C_A004447
585 select SYS_FSL_HAS_DDR3
586 select SYS_FSL_HAS_SEC
587 select SYS_FSL_SEC_BE
588 select SYS_FSL_SEC_COMPAT_4
593 select SYS_FSL_ERRATUM_A004508
594 select SYS_FSL_ERRATUM_A005125
595 select SYS_FSL_ERRATUM_ELBC_A001
596 select SYS_FSL_ERRATUM_ESDHC111
597 select SYS_FSL_HAS_DDR3
598 select SYS_FSL_HAS_SEC
599 select SYS_FSL_SEC_BE
600 select SYS_FSL_SEC_COMPAT_2
601 select SYS_PPC_E500_USE_DEBUG_TLB
606 select SYS_FSL_ERRATUM_A004508
607 select SYS_FSL_ERRATUM_A005125
608 select SYS_FSL_ERRATUM_ELBC_A001
609 select SYS_FSL_ERRATUM_ESDHC111
610 select SYS_FSL_HAS_DDR3
611 select SYS_FSL_HAS_SEC
612 select SYS_FSL_SEC_BE
613 select SYS_FSL_SEC_COMPAT_2
614 select SYS_PPC_E500_USE_DEBUG_TLB
619 select SYS_FSL_ERRATUM_A004477
620 select SYS_FSL_ERRATUM_A004508
621 select SYS_FSL_ERRATUM_A005125
622 select SYS_FSL_ERRATUM_ESDHC111
623 select SYS_FSL_ERRATUM_ESDHC_A001
624 select SYS_FSL_HAS_DDR3
625 select SYS_FSL_HAS_SEC
626 select SYS_FSL_SEC_BE
627 select SYS_FSL_SEC_COMPAT_2
628 select SYS_PPC_E500_USE_DEBUG_TLB
634 select SYS_FSL_ERRATUM_A004510
635 select SYS_FSL_ERRATUM_A004849
636 select SYS_FSL_ERRATUM_A006261
637 select SYS_FSL_ERRATUM_CPU_A003999
638 select SYS_FSL_ERRATUM_DDR_A003
639 select SYS_FSL_ERRATUM_DDR_A003474
640 select SYS_FSL_ERRATUM_ESDHC111
641 select SYS_FSL_ERRATUM_I2C_A004447
642 select SYS_FSL_ERRATUM_NMG_CPU_A011
643 select SYS_FSL_ERRATUM_SRIO_A004034
644 select SYS_FSL_ERRATUM_USB14
645 select SYS_FSL_HAS_DDR3
646 select SYS_FSL_HAS_SEC
647 select SYS_FSL_SEC_BE
648 select SYS_FSL_SEC_COMPAT_4
654 select SYS_FSL_DDR_VER_44
655 select SYS_FSL_ERRATUM_A004510
656 select SYS_FSL_ERRATUM_A004849
657 select SYS_FSL_ERRATUM_A005812
658 select SYS_FSL_ERRATUM_A006261
659 select SYS_FSL_ERRATUM_CPU_A003999
660 select SYS_FSL_ERRATUM_DDR_A003
661 select SYS_FSL_ERRATUM_DDR_A003474
662 select SYS_FSL_ERRATUM_ESDHC111
663 select SYS_FSL_ERRATUM_I2C_A004447
664 select SYS_FSL_ERRATUM_NMG_CPU_A011
665 select SYS_FSL_ERRATUM_SRIO_A004034
666 select SYS_FSL_ERRATUM_USB14
667 select SYS_FSL_HAS_DDR3
668 select SYS_FSL_HAS_SEC
669 select SYS_FSL_SEC_BE
670 select SYS_FSL_SEC_COMPAT_4
676 select SYS_FSL_DDR_VER_44
677 select SYS_FSL_ERRATUM_A004510
678 select SYS_FSL_ERRATUM_A004580
679 select SYS_FSL_ERRATUM_A004849
680 select SYS_FSL_ERRATUM_A005812
681 select SYS_FSL_ERRATUM_A007075
682 select SYS_FSL_ERRATUM_CPC_A002
683 select SYS_FSL_ERRATUM_CPC_A003
684 select SYS_FSL_ERRATUM_CPU_A003999
685 select SYS_FSL_ERRATUM_DDR_A003
686 select SYS_FSL_ERRATUM_DDR_A003474
687 select SYS_FSL_ERRATUM_ELBC_A001
688 select SYS_FSL_ERRATUM_ESDHC111
689 select SYS_FSL_ERRATUM_ESDHC13
690 select SYS_FSL_ERRATUM_ESDHC135
691 select SYS_FSL_ERRATUM_I2C_A004447
692 select SYS_FSL_ERRATUM_NMG_CPU_A011
693 select SYS_FSL_ERRATUM_SRIO_A004034
694 select SYS_P4080_ERRATUM_CPU22
695 select SYS_P4080_ERRATUM_PCIE_A003
696 select SYS_P4080_ERRATUM_SERDES8
697 select SYS_P4080_ERRATUM_SERDES9
698 select SYS_P4080_ERRATUM_SERDES_A001
699 select SYS_P4080_ERRATUM_SERDES_A005
700 select SYS_FSL_HAS_DDR3
701 select SYS_FSL_HAS_SEC
702 select SYS_FSL_SEC_BE
703 select SYS_FSL_SEC_COMPAT_4
709 select SYS_FSL_DDR_VER_44
710 select SYS_FSL_ERRATUM_A004510
711 select SYS_FSL_ERRATUM_A006261
712 select SYS_FSL_ERRATUM_DDR_A003
713 select SYS_FSL_ERRATUM_DDR_A003474
714 select SYS_FSL_ERRATUM_ESDHC111
715 select SYS_FSL_ERRATUM_I2C_A004447
716 select SYS_FSL_ERRATUM_SRIO_A004034
717 select SYS_FSL_ERRATUM_USB14
718 select SYS_FSL_HAS_DDR3
719 select SYS_FSL_HAS_SEC
720 select SYS_FSL_SEC_BE
721 select SYS_FSL_SEC_COMPAT_4
727 select SYS_FSL_DDR_VER_44
728 select SYS_FSL_ERRATUM_A004510
729 select SYS_FSL_ERRATUM_A004699
730 select SYS_FSL_ERRATUM_A005812
731 select SYS_FSL_ERRATUM_A006261
732 select SYS_FSL_ERRATUM_DDR_A003
733 select SYS_FSL_ERRATUM_DDR_A003474
734 select SYS_FSL_ERRATUM_ESDHC111
735 select SYS_FSL_ERRATUM_USB14
736 select SYS_FSL_HAS_DDR3
737 select SYS_FSL_HAS_SEC
738 select SYS_FSL_SEC_BE
739 select SYS_FSL_SEC_COMPAT_4
741 config ARCH_QEMU_E500
748 select SYS_FSL_DDR_VER_50
749 select SYS_FSL_ERRATUM_A008378
750 select SYS_FSL_ERRATUM_A009663
751 select SYS_FSL_ERRATUM_A009942
752 select SYS_FSL_ERRATUM_ESDHC111
753 select SYS_FSL_HAS_DDR3
754 select SYS_FSL_HAS_DDR4
755 select SYS_FSL_HAS_SEC
756 select SYS_FSL_SEC_BE
757 select SYS_FSL_SEC_COMPAT_5
763 select SYS_FSL_DDR_VER_50
764 select SYS_FSL_ERRATUM_A008378
765 select SYS_FSL_ERRATUM_A009663
766 select SYS_FSL_ERRATUM_A009942
767 select SYS_FSL_ERRATUM_ESDHC111
768 select SYS_FSL_HAS_DDR3
769 select SYS_FSL_HAS_DDR4
770 select SYS_FSL_HAS_SEC
771 select SYS_FSL_SEC_BE
772 select SYS_FSL_SEC_COMPAT_5
778 select SYS_FSL_DDR_VER_50
779 select SYS_FSL_ERRATUM_A008044
780 select SYS_FSL_ERRATUM_A008378
781 select SYS_FSL_ERRATUM_A009663
782 select SYS_FSL_ERRATUM_A009942
783 select SYS_FSL_ERRATUM_ESDHC111
784 select SYS_FSL_HAS_DDR3
785 select SYS_FSL_HAS_DDR4
786 select SYS_FSL_HAS_SEC
787 select SYS_FSL_SEC_BE
788 select SYS_FSL_SEC_COMPAT_5
794 select SYS_FSL_DDR_VER_50
795 select SYS_FSL_ERRATUM_A008044
796 select SYS_FSL_ERRATUM_A008378
797 select SYS_FSL_ERRATUM_A009663
798 select SYS_FSL_ERRATUM_A009942
799 select SYS_FSL_ERRATUM_ESDHC111
800 select SYS_FSL_HAS_DDR3
801 select SYS_FSL_HAS_DDR4
802 select SYS_FSL_HAS_SEC
803 select SYS_FSL_SEC_BE
804 select SYS_FSL_SEC_COMPAT_5
810 select SYS_FSL_DDR_VER_47
811 select SYS_FSL_ERRATUM_A006379
812 select SYS_FSL_ERRATUM_A006593
813 select SYS_FSL_ERRATUM_A007186
814 select SYS_FSL_ERRATUM_A007212
815 select SYS_FSL_ERRATUM_A009942
816 select SYS_FSL_ERRATUM_ESDHC111
817 select SYS_FSL_HAS_DDR3
818 select SYS_FSL_HAS_SEC
819 select SYS_FSL_SEC_BE
820 select SYS_FSL_SEC_COMPAT_4
826 select SYS_FSL_DDR_VER_47
827 select SYS_FSL_ERRATUM_A006379
828 select SYS_FSL_ERRATUM_A006593
829 select SYS_FSL_ERRATUM_A007186
830 select SYS_FSL_ERRATUM_A007212
831 select SYS_FSL_ERRATUM_A009942
832 select SYS_FSL_ERRATUM_ESDHC111
833 select SYS_FSL_HAS_DDR3
834 select SYS_FSL_HAS_SEC
835 select SYS_FSL_SEC_BE
836 select SYS_FSL_SEC_COMPAT_4
842 select SYS_FSL_DDR_VER_47
843 select SYS_FSL_ERRATUM_A004468
844 select SYS_FSL_ERRATUM_A005871
845 select SYS_FSL_ERRATUM_A006379
846 select SYS_FSL_ERRATUM_A006593
847 select SYS_FSL_ERRATUM_A007186
848 select SYS_FSL_ERRATUM_A007798
849 select SYS_FSL_ERRATUM_A009942
850 select SYS_FSL_HAS_DDR3
851 select SYS_FSL_HAS_SEC
852 select SYS_FSL_SEC_BE
853 select SYS_FSL_SEC_COMPAT_4
859 select SYS_FSL_DDR_VER_47
860 select SYS_FSL_ERRATUM_A004468
861 select SYS_FSL_ERRATUM_A005871
862 select SYS_FSL_ERRATUM_A006261
863 select SYS_FSL_ERRATUM_A006379
864 select SYS_FSL_ERRATUM_A006593
865 select SYS_FSL_ERRATUM_A007186
866 select SYS_FSL_ERRATUM_A007798
867 select SYS_FSL_ERRATUM_A009942
868 select SYS_FSL_HAS_DDR3
869 select SYS_FSL_HAS_SEC
870 select SYS_FSL_SEC_BE
871 select SYS_FSL_SEC_COMPAT_4
881 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
886 Enble PowerPC E500MC core
891 Use Freescale common code for Local Access Window
896 Enable Freescale Secure Boot feature. Normally selected
897 by defconfig. If unsure, do not change.
900 int "Maximum number of CPUs permitted for MPC85xx"
901 default 12 if ARCH_T4240
902 default 8 if ARCH_P4080 || \
904 default 4 if ARCH_B4860 || \
912 default 2 if ARCH_B4420 || \
927 Set this number to the maximum number of possible CPUs in the SoC.
928 SoCs may have multiple clusters with each cluster may have multiple
929 ports. If some ports are reserved but higher ports are used for
930 cores, count the reserved ports. This will allocate enough memory
931 in spin table to properly handle all cores.
933 config SYS_CCSRBAR_DEFAULT
934 hex "Default CCSRBAR address"
935 default 0xff700000 if ARCH_BSC9131 || \
956 default 0xff600000 if ARCH_P1023
957 default 0xfe000000 if ARCH_B4420 || \
972 default 0xe0000000 if ARCH_QEMU_E500
974 Default value of CCSRBAR comes from power-on-reset. It
975 is fixed on each SoC. Some SoCs can have different value
976 if changed by pre-boot regime. The value here must match
977 the current value in SoC. If not sure, do not change.
979 config SYS_FSL_ERRATUM_A004468
982 config SYS_FSL_ERRATUM_A004477
985 config SYS_FSL_ERRATUM_A004508
988 config SYS_FSL_ERRATUM_A004580
991 config SYS_FSL_ERRATUM_A004699
994 config SYS_FSL_ERRATUM_A004849
997 config SYS_FSL_ERRATUM_A004510
1000 config SYS_FSL_ERRATUM_A004510_SVR_REV
1002 depends on SYS_FSL_ERRATUM_A004510
1003 default 0x20 if ARCH_P4080
1006 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1008 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1011 config SYS_FSL_ERRATUM_A005125
1014 config SYS_FSL_ERRATUM_A005434
1017 config SYS_FSL_ERRATUM_A005812
1020 config SYS_FSL_ERRATUM_A005871
1023 config SYS_FSL_ERRATUM_A006261
1026 config SYS_FSL_ERRATUM_A006379
1029 config SYS_FSL_ERRATUM_A006384
1032 config SYS_FSL_ERRATUM_A006475
1035 config SYS_FSL_ERRATUM_A006593
1038 config SYS_FSL_ERRATUM_A007075
1041 config SYS_FSL_ERRATUM_A007186
1044 config SYS_FSL_ERRATUM_A007212
1047 config SYS_FSL_ERRATUM_A007798
1050 config SYS_FSL_ERRATUM_A008044
1053 config SYS_FSL_ERRATUM_CPC_A002
1056 config SYS_FSL_ERRATUM_CPC_A003
1059 config SYS_FSL_ERRATUM_CPU_A003999
1062 config SYS_FSL_ERRATUM_ELBC_A001
1065 config SYS_FSL_ERRATUM_I2C_A004447
1068 config SYS_FSL_A004447_SVR_REV
1070 depends on SYS_FSL_ERRATUM_I2C_A004447
1071 default 0x00 if ARCH_MPC8548
1072 default 0x10 if ARCH_P1010
1073 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1074 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1076 config SYS_FSL_ERRATUM_IFC_A002769
1079 config SYS_FSL_ERRATUM_IFC_A003399
1082 config SYS_FSL_ERRATUM_NMG_CPU_A011
1085 config SYS_FSL_ERRATUM_NMG_ETSEC129
1088 config SYS_FSL_ERRATUM_NMG_LBC103
1091 config SYS_FSL_ERRATUM_P1010_A003549
1094 config SYS_FSL_ERRATUM_SATA_A001
1097 config SYS_FSL_ERRATUM_SEC_A003571
1100 config SYS_FSL_ERRATUM_SRIO_A004034
1103 config SYS_FSL_ERRATUM_USB14
1106 config SYS_P4080_ERRATUM_CPU22
1109 config SYS_P4080_ERRATUM_PCIE_A003
1112 config SYS_P4080_ERRATUM_SERDES8
1115 config SYS_P4080_ERRATUM_SERDES9
1118 config SYS_P4080_ERRATUM_SERDES_A001
1121 config SYS_P4080_ERRATUM_SERDES_A005
1124 config SYS_FSL_NUM_LAWS
1125 int "Number of local access windows"
1127 default 32 if ARCH_B4420 || \
1138 default 16 if ARCH_T1023 || \
1142 default 12 if ARCH_BSC9131 || \
1156 default 10 if ARCH_MPC8544 || \
1160 default 8 if ARCH_MPC8540 || \
1165 Number of local access windows. This is fixed per SoC.
1166 If not sure, do not change.
1168 config SYS_NUM_TLBCAMS
1169 int "Number of TLB CAM entries"
1170 default 64 if E500MC
1173 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1174 16 for other E500 SoCs.
1176 config SYS_PPC_E500_USE_DEBUG_TLB
1179 config SYS_PPC_E500_DEBUG_TLB
1180 int "Temporary TLB entry for external debugger"
1181 depends on SYS_PPC_E500_USE_DEBUG_TLB
1182 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1183 default 1 if ARCH_MPC8536
1184 default 2 if ARCH_MPC8572 || \
1192 default 3 if ARCH_P1010 || \
1196 Select a temporary TLB entry to be used during boot to work
1197 around limitations in e500v1 and e500v2 external debugger
1198 support. This reduces the portions of the boot code where
1199 breakpoints and single stepping do not work. The value of this
1200 symbol should be set to the TLB1 entry to be used for this
1201 purpose. If unsure, do not change.
1203 source "board/freescale/b4860qds/Kconfig"
1204 source "board/freescale/bsc9131rdb/Kconfig"
1205 source "board/freescale/bsc9132qds/Kconfig"
1206 source "board/freescale/c29xpcie/Kconfig"
1207 source "board/freescale/corenet_ds/Kconfig"
1208 source "board/freescale/mpc8536ds/Kconfig"
1209 source "board/freescale/mpc8540ads/Kconfig"
1210 source "board/freescale/mpc8541cds/Kconfig"
1211 source "board/freescale/mpc8544ds/Kconfig"
1212 source "board/freescale/mpc8548cds/Kconfig"
1213 source "board/freescale/mpc8555cds/Kconfig"
1214 source "board/freescale/mpc8560ads/Kconfig"
1215 source "board/freescale/mpc8568mds/Kconfig"
1216 source "board/freescale/mpc8569mds/Kconfig"
1217 source "board/freescale/mpc8572ds/Kconfig"
1218 source "board/freescale/p1010rdb/Kconfig"
1219 source "board/freescale/p1022ds/Kconfig"
1220 source "board/freescale/p1023rdb/Kconfig"
1221 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1222 source "board/freescale/p1_twr/Kconfig"
1223 source "board/freescale/p2041rdb/Kconfig"
1224 source "board/freescale/qemu-ppce500/Kconfig"
1225 source "board/freescale/t102xqds/Kconfig"
1226 source "board/freescale/t102xrdb/Kconfig"
1227 source "board/freescale/t1040qds/Kconfig"
1228 source "board/freescale/t104xrdb/Kconfig"
1229 source "board/freescale/t208xqds/Kconfig"
1230 source "board/freescale/t208xrdb/Kconfig"
1231 source "board/freescale/t4qds/Kconfig"
1232 source "board/freescale/t4rdb/Kconfig"
1233 source "board/gdsys/p1022/Kconfig"
1234 source "board/keymile/kmp204x/Kconfig"
1235 source "board/sbc8548/Kconfig"
1236 source "board/socrates/Kconfig"
1237 source "board/varisys/cyrus/Kconfig"
1238 source "board/xes/xpedite520x/Kconfig"
1239 source "board/xes/xpedite537x/Kconfig"
1240 source "board/xes/xpedite550x/Kconfig"
1241 source "board/Arcturus/ucp1020/Kconfig"