8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_B4420QDS
28 bool "Support B4420QDS"
33 config TARGET_B4860QDS
34 bool "Support B4860QDS"
36 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 config TARGET_BSC9131RDB
41 bool "Support BSC9131RDB"
44 select BOARD_EARLY_INIT_F
46 config TARGET_BSC9132QDS
47 bool "Support BSC9132QDS"
49 select BOARD_LATE_INIT if CHAIN_OF_TRUST
51 select BOARD_EARLY_INIT_F
53 config TARGET_C29XPCIE
54 bool "Support C29XPCIE"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
62 bool "Support P3041DS"
65 select BOARD_LATE_INIT if CHAIN_OF_TRUST
69 bool "Support P4080DS"
72 select BOARD_LATE_INIT if CHAIN_OF_TRUST
76 bool "Support P5020DS"
79 select BOARD_LATE_INIT if CHAIN_OF_TRUST
83 bool "Support P5040DS"
86 select BOARD_LATE_INIT if CHAIN_OF_TRUST
89 config TARGET_MPC8536DS
90 bool "Support MPC8536DS"
92 # Use DDR3 controller with DDR2 DIMMs on this board
93 select SYS_FSL_DDRC_GEN3
96 config TARGET_MPC8541CDS
97 bool "Support MPC8541CDS"
100 config TARGET_MPC8544DS
101 bool "Support MPC8544DS"
104 config TARGET_MPC8548CDS
105 bool "Support MPC8548CDS"
108 config TARGET_MPC8555CDS
109 bool "Support MPC8555CDS"
112 config TARGET_MPC8568MDS
113 bool "Support MPC8568MDS"
116 config TARGET_MPC8569MDS
117 bool "Support MPC8569MDS"
120 config TARGET_MPC8572DS
121 bool "Support MPC8572DS"
123 # Use DDR3 controller with DDR2 DIMMs on this board
124 select SYS_FSL_DDRC_GEN3
127 config TARGET_P1010RDB_PA
128 bool "Support P1010RDB_PA"
130 select BOARD_LATE_INIT if CHAIN_OF_TRUST
136 config TARGET_P1010RDB_PB
137 bool "Support P1010RDB_PB"
139 select BOARD_LATE_INIT if CHAIN_OF_TRUST
145 config TARGET_P1022DS
146 bool "Support P1022DS"
152 config TARGET_P1023RDB
153 bool "Support P1023RDB"
157 config TARGET_P1020MBG
158 bool "Support P1020MBG-PC"
165 config TARGET_P1020RDB_PC
166 bool "Support P1020RDB-PC"
173 config TARGET_P1020RDB_PD
174 bool "Support P1020RDB-PD"
181 config TARGET_P1020UTM
182 bool "Support P1020UTM"
189 config TARGET_P1021RDB
190 bool "Support P1021RDB"
197 config TARGET_P1024RDB
198 bool "Support P1024RDB"
205 config TARGET_P1025RDB
206 bool "Support P1025RDB"
213 config TARGET_P2020RDB
214 bool "Support P2020RDB-PC"
222 bool "Support p1_twr"
225 config TARGET_P2041RDB
226 bool "Support P2041RDB"
228 select BOARD_LATE_INIT if CHAIN_OF_TRUST
232 config TARGET_QEMU_PPCE500
233 bool "Support qemu-ppce500"
234 select ARCH_QEMU_E500
237 config TARGET_T1024QDS
238 bool "Support T1024QDS"
240 select BOARD_LATE_INIT if CHAIN_OF_TRUST
246 config TARGET_T1023RDB
247 bool "Support T1023RDB"
249 select BOARD_LATE_INIT if CHAIN_OF_TRUST
254 config TARGET_T1024RDB
255 bool "Support T1024RDB"
257 select BOARD_LATE_INIT if CHAIN_OF_TRUST
262 config TARGET_T1040QDS
263 bool "Support T1040QDS"
265 select BOARD_LATE_INIT if CHAIN_OF_TRUST
270 config TARGET_T1040RDB
271 bool "Support T1040RDB"
273 select BOARD_LATE_INIT if CHAIN_OF_TRUST
278 config TARGET_T1040D4RDB
279 bool "Support T1040D4RDB"
281 select BOARD_LATE_INIT if CHAIN_OF_TRUST
286 config TARGET_T1042RDB
287 bool "Support T1042RDB"
289 select BOARD_LATE_INIT if CHAIN_OF_TRUST
294 config TARGET_T1042D4RDB
295 bool "Support T1042D4RDB"
297 select BOARD_LATE_INIT if CHAIN_OF_TRUST
302 config TARGET_T1042RDB_PI
303 bool "Support T1042RDB_PI"
305 select BOARD_LATE_INIT if CHAIN_OF_TRUST
310 config TARGET_T2080QDS
311 bool "Support T2080QDS"
313 select BOARD_LATE_INIT if CHAIN_OF_TRUST
318 config TARGET_T2080RDB
319 bool "Support T2080RDB"
321 select BOARD_LATE_INIT if CHAIN_OF_TRUST
326 config TARGET_T2081QDS
327 bool "Support T2081QDS"
332 config TARGET_T4160QDS
333 bool "Support T4160QDS"
335 select BOARD_LATE_INIT if CHAIN_OF_TRUST
340 config TARGET_T4160RDB
341 bool "Support T4160RDB"
346 config TARGET_T4240QDS
347 bool "Support T4240QDS"
349 select BOARD_LATE_INIT if CHAIN_OF_TRUST
354 config TARGET_T4240RDB
355 bool "Support T4240RDB"
361 config TARGET_CONTROLCENTERD
362 bool "Support controlcenterd"
365 config TARGET_KMP204X
366 bool "Support kmp204x"
372 config TARGET_XPEDITE520X
373 bool "Support xpedite520x"
376 config TARGET_XPEDITE537X
377 bool "Support xpedite537x"
379 # Use DDR3 controller with DDR2 DIMMs on this board
380 select SYS_FSL_DDRC_GEN3
382 config TARGET_XPEDITE550X
383 bool "Support xpedite550x"
386 config TARGET_UCP1020
387 bool "Support uCP1020"
391 config TARGET_CYRUS_P5020
392 bool "Support Varisys Cyrus P5020"
396 config TARGET_CYRUS_P5040
397 bool "Support Varisys Cyrus P5040"
408 select SYS_FSL_DDR_VER_47
409 select SYS_FSL_ERRATUM_A004477
410 select SYS_FSL_ERRATUM_A005871
411 select SYS_FSL_ERRATUM_A006379
412 select SYS_FSL_ERRATUM_A006384
413 select SYS_FSL_ERRATUM_A006475
414 select SYS_FSL_ERRATUM_A006593
415 select SYS_FSL_ERRATUM_A007075
416 select SYS_FSL_ERRATUM_A007186
417 select SYS_FSL_ERRATUM_A007212
418 select SYS_FSL_ERRATUM_A009942
419 select SYS_FSL_HAS_DDR3
420 select SYS_FSL_HAS_SEC
421 select SYS_FSL_QORIQ_CHASSIS2
422 select SYS_FSL_SEC_BE
423 select SYS_FSL_SEC_COMPAT_4
433 select SYS_FSL_DDR_VER_47
434 select SYS_FSL_ERRATUM_A004477
435 select SYS_FSL_ERRATUM_A005871
436 select SYS_FSL_ERRATUM_A006379
437 select SYS_FSL_ERRATUM_A006384
438 select SYS_FSL_ERRATUM_A006475
439 select SYS_FSL_ERRATUM_A006593
440 select SYS_FSL_ERRATUM_A007075
441 select SYS_FSL_ERRATUM_A007186
442 select SYS_FSL_ERRATUM_A007212
443 select SYS_FSL_ERRATUM_A007907
444 select SYS_FSL_ERRATUM_A009942
445 select SYS_FSL_HAS_DDR3
446 select SYS_FSL_HAS_SEC
447 select SYS_FSL_QORIQ_CHASSIS2
448 select SYS_FSL_SEC_BE
449 select SYS_FSL_SEC_COMPAT_4
457 select SYS_FSL_DDR_VER_44
458 select SYS_FSL_ERRATUM_A004477
459 select SYS_FSL_ERRATUM_A005125
460 select SYS_FSL_ERRATUM_ESDHC111
461 select SYS_FSL_HAS_DDR3
462 select SYS_FSL_HAS_SEC
463 select SYS_FSL_SEC_BE
464 select SYS_FSL_SEC_COMPAT_4
471 select SYS_FSL_DDR_VER_46
472 select SYS_FSL_ERRATUM_A004477
473 select SYS_FSL_ERRATUM_A005125
474 select SYS_FSL_ERRATUM_A005434
475 select SYS_FSL_ERRATUM_ESDHC111
476 select SYS_FSL_ERRATUM_I2C_A004447
477 select SYS_FSL_ERRATUM_IFC_A002769
478 select SYS_FSL_HAS_DDR3
479 select SYS_FSL_HAS_SEC
480 select SYS_FSL_SEC_BE
481 select SYS_FSL_SEC_COMPAT_4
482 select SYS_PPC_E500_USE_DEBUG_TLB
490 select SYS_FSL_DDR_VER_46
491 select SYS_FSL_ERRATUM_A005125
492 select SYS_FSL_ERRATUM_ESDHC111
493 select SYS_FSL_HAS_DDR3
494 select SYS_FSL_HAS_SEC
495 select SYS_FSL_SEC_BE
496 select SYS_FSL_SEC_COMPAT_6
497 select SYS_PPC_E500_USE_DEBUG_TLB
503 select SYS_FSL_ERRATUM_A004508
504 select SYS_FSL_ERRATUM_A005125
505 select SYS_FSL_HAS_DDR2
506 select SYS_FSL_HAS_DDR3
507 select SYS_FSL_HAS_SEC
508 select SYS_FSL_SEC_BE
509 select SYS_FSL_SEC_COMPAT_2
510 select SYS_PPC_E500_USE_DEBUG_TLB
517 select SYS_FSL_HAS_DDR1
522 select SYS_FSL_HAS_DDR1
523 select SYS_FSL_HAS_SEC
524 select SYS_FSL_SEC_BE
525 select SYS_FSL_SEC_COMPAT_2
530 select SYS_FSL_ERRATUM_A005125
531 select SYS_FSL_HAS_DDR2
532 select SYS_FSL_HAS_SEC
533 select SYS_FSL_SEC_BE
534 select SYS_FSL_SEC_COMPAT_2
535 select SYS_PPC_E500_USE_DEBUG_TLB
541 select SYS_FSL_ERRATUM_A005125
542 select SYS_FSL_ERRATUM_NMG_DDR120
543 select SYS_FSL_ERRATUM_NMG_LBC103
544 select SYS_FSL_ERRATUM_NMG_ETSEC129
545 select SYS_FSL_ERRATUM_I2C_A004447
546 select SYS_FSL_HAS_DDR2
547 select SYS_FSL_HAS_DDR1
548 select SYS_FSL_HAS_SEC
549 select SYS_FSL_SEC_BE
550 select SYS_FSL_SEC_COMPAT_2
551 select SYS_PPC_E500_USE_DEBUG_TLB
556 select SYS_FSL_HAS_DDR1
557 select SYS_FSL_HAS_SEC
558 select SYS_FSL_SEC_BE
559 select SYS_FSL_SEC_COMPAT_2
564 select SYS_FSL_HAS_DDR1
569 select SYS_FSL_HAS_DDR2
570 select SYS_FSL_HAS_SEC
571 select SYS_FSL_SEC_BE
572 select SYS_FSL_SEC_COMPAT_2
577 select SYS_FSL_ERRATUM_A004508
578 select SYS_FSL_ERRATUM_A005125
579 select SYS_FSL_HAS_DDR3
580 select SYS_FSL_HAS_SEC
581 select SYS_FSL_SEC_BE
582 select SYS_FSL_SEC_COMPAT_2
588 select SYS_FSL_ERRATUM_A004508
589 select SYS_FSL_ERRATUM_A005125
590 select SYS_FSL_ERRATUM_DDR_115
591 select SYS_FSL_ERRATUM_DDR111_DDR134
592 select SYS_FSL_HAS_DDR2
593 select SYS_FSL_HAS_DDR3
594 select SYS_FSL_HAS_SEC
595 select SYS_FSL_SEC_BE
596 select SYS_FSL_SEC_COMPAT_2
597 select SYS_PPC_E500_USE_DEBUG_TLB
603 select SYS_FSL_ERRATUM_A004477
604 select SYS_FSL_ERRATUM_A004508
605 select SYS_FSL_ERRATUM_A005125
606 select SYS_FSL_ERRATUM_A006261
607 select SYS_FSL_ERRATUM_A007075
608 select SYS_FSL_ERRATUM_ESDHC111
609 select SYS_FSL_ERRATUM_I2C_A004447
610 select SYS_FSL_ERRATUM_IFC_A002769
611 select SYS_FSL_ERRATUM_P1010_A003549
612 select SYS_FSL_ERRATUM_SEC_A003571
613 select SYS_FSL_ERRATUM_IFC_A003399
614 select SYS_FSL_HAS_DDR3
615 select SYS_FSL_HAS_SEC
616 select SYS_FSL_SEC_BE
617 select SYS_FSL_SEC_COMPAT_4
618 select SYS_PPC_E500_USE_DEBUG_TLB
627 select SYS_FSL_ERRATUM_A004508
628 select SYS_FSL_ERRATUM_A005125
629 select SYS_FSL_ERRATUM_ELBC_A001
630 select SYS_FSL_ERRATUM_ESDHC111
631 select SYS_FSL_HAS_DDR3
632 select SYS_FSL_HAS_SEC
633 select SYS_FSL_SEC_BE
634 select SYS_FSL_SEC_COMPAT_2
635 select SYS_PPC_E500_USE_DEBUG_TLB
641 select SYS_FSL_ERRATUM_A004508
642 select SYS_FSL_ERRATUM_A005125
643 select SYS_FSL_ERRATUM_ELBC_A001
644 select SYS_FSL_ERRATUM_ESDHC111
645 select SYS_FSL_HAS_DDR3
646 select SYS_FSL_HAS_SEC
647 select SYS_FSL_SEC_BE
648 select SYS_FSL_SEC_COMPAT_2
649 select SYS_PPC_E500_USE_DEBUG_TLB
656 select SYS_FSL_ERRATUM_A004508
657 select SYS_FSL_ERRATUM_A005125
658 select SYS_FSL_ERRATUM_ELBC_A001
659 select SYS_FSL_ERRATUM_ESDHC111
660 select SYS_FSL_HAS_DDR3
661 select SYS_FSL_HAS_SEC
662 select SYS_FSL_SEC_BE
663 select SYS_FSL_SEC_COMPAT_2
664 select SYS_PPC_E500_USE_DEBUG_TLB
671 select SYS_FSL_ERRATUM_A004477
672 select SYS_FSL_ERRATUM_A004508
673 select SYS_FSL_ERRATUM_A005125
674 select SYS_FSL_ERRATUM_ELBC_A001
675 select SYS_FSL_ERRATUM_ESDHC111
676 select SYS_FSL_ERRATUM_SATA_A001
677 select SYS_FSL_HAS_DDR3
678 select SYS_FSL_HAS_SEC
679 select SYS_FSL_SEC_BE
680 select SYS_FSL_SEC_COMPAT_2
681 select SYS_PPC_E500_USE_DEBUG_TLB
687 select SYS_FSL_ERRATUM_A004508
688 select SYS_FSL_ERRATUM_A005125
689 select SYS_FSL_ERRATUM_I2C_A004447
690 select SYS_FSL_HAS_DDR3
691 select SYS_FSL_HAS_SEC
692 select SYS_FSL_SEC_BE
693 select SYS_FSL_SEC_COMPAT_4
699 select SYS_FSL_ERRATUM_A004508
700 select SYS_FSL_ERRATUM_A005125
701 select SYS_FSL_ERRATUM_ELBC_A001
702 select SYS_FSL_ERRATUM_ESDHC111
703 select SYS_FSL_HAS_DDR3
704 select SYS_FSL_HAS_SEC
705 select SYS_FSL_SEC_BE
706 select SYS_FSL_SEC_COMPAT_2
707 select SYS_PPC_E500_USE_DEBUG_TLB
715 select SYS_FSL_ERRATUM_A004508
716 select SYS_FSL_ERRATUM_A005125
717 select SYS_FSL_ERRATUM_ELBC_A001
718 select SYS_FSL_ERRATUM_ESDHC111
719 select SYS_FSL_HAS_DDR3
720 select SYS_FSL_HAS_SEC
721 select SYS_FSL_SEC_BE
722 select SYS_FSL_SEC_COMPAT_2
723 select SYS_PPC_E500_USE_DEBUG_TLB
730 select SYS_FSL_ERRATUM_A004477
731 select SYS_FSL_ERRATUM_A004508
732 select SYS_FSL_ERRATUM_A005125
733 select SYS_FSL_ERRATUM_ESDHC111
734 select SYS_FSL_ERRATUM_ESDHC_A001
735 select SYS_FSL_HAS_DDR3
736 select SYS_FSL_HAS_SEC
737 select SYS_FSL_SEC_BE
738 select SYS_FSL_SEC_COMPAT_2
739 select SYS_PPC_E500_USE_DEBUG_TLB
747 select SYS_FSL_ERRATUM_A004510
748 select SYS_FSL_ERRATUM_A004849
749 select SYS_FSL_ERRATUM_A006261
750 select SYS_FSL_ERRATUM_CPU_A003999
751 select SYS_FSL_ERRATUM_DDR_A003
752 select SYS_FSL_ERRATUM_DDR_A003474
753 select SYS_FSL_ERRATUM_ESDHC111
754 select SYS_FSL_ERRATUM_I2C_A004447
755 select SYS_FSL_ERRATUM_NMG_CPU_A011
756 select SYS_FSL_ERRATUM_SRIO_A004034
757 select SYS_FSL_ERRATUM_USB14
758 select SYS_FSL_HAS_DDR3
759 select SYS_FSL_HAS_SEC
760 select SYS_FSL_QORIQ_CHASSIS1
761 select SYS_FSL_SEC_BE
762 select SYS_FSL_SEC_COMPAT_4
769 select SYS_FSL_DDR_VER_44
770 select SYS_FSL_ERRATUM_A004510
771 select SYS_FSL_ERRATUM_A004849
772 select SYS_FSL_ERRATUM_A005812
773 select SYS_FSL_ERRATUM_A006261
774 select SYS_FSL_ERRATUM_CPU_A003999
775 select SYS_FSL_ERRATUM_DDR_A003
776 select SYS_FSL_ERRATUM_DDR_A003474
777 select SYS_FSL_ERRATUM_ESDHC111
778 select SYS_FSL_ERRATUM_I2C_A004447
779 select SYS_FSL_ERRATUM_NMG_CPU_A011
780 select SYS_FSL_ERRATUM_SRIO_A004034
781 select SYS_FSL_ERRATUM_USB14
782 select SYS_FSL_HAS_DDR3
783 select SYS_FSL_HAS_SEC
784 select SYS_FSL_QORIQ_CHASSIS1
785 select SYS_FSL_SEC_BE
786 select SYS_FSL_SEC_COMPAT_4
794 select SYS_FSL_DDR_VER_44
795 select SYS_FSL_ERRATUM_A004510
796 select SYS_FSL_ERRATUM_A004580
797 select SYS_FSL_ERRATUM_A004849
798 select SYS_FSL_ERRATUM_A005812
799 select SYS_FSL_ERRATUM_A007075
800 select SYS_FSL_ERRATUM_CPC_A002
801 select SYS_FSL_ERRATUM_CPC_A003
802 select SYS_FSL_ERRATUM_CPU_A003999
803 select SYS_FSL_ERRATUM_DDR_A003
804 select SYS_FSL_ERRATUM_DDR_A003474
805 select SYS_FSL_ERRATUM_ELBC_A001
806 select SYS_FSL_ERRATUM_ESDHC111
807 select SYS_FSL_ERRATUM_ESDHC13
808 select SYS_FSL_ERRATUM_ESDHC135
809 select SYS_FSL_ERRATUM_I2C_A004447
810 select SYS_FSL_ERRATUM_NMG_CPU_A011
811 select SYS_FSL_ERRATUM_SRIO_A004034
812 select SYS_P4080_ERRATUM_CPU22
813 select SYS_P4080_ERRATUM_PCIE_A003
814 select SYS_P4080_ERRATUM_SERDES8
815 select SYS_P4080_ERRATUM_SERDES9
816 select SYS_P4080_ERRATUM_SERDES_A001
817 select SYS_P4080_ERRATUM_SERDES_A005
818 select SYS_FSL_HAS_DDR3
819 select SYS_FSL_HAS_SEC
820 select SYS_FSL_QORIQ_CHASSIS1
821 select SYS_FSL_SEC_BE
822 select SYS_FSL_SEC_COMPAT_4
830 select SYS_FSL_DDR_VER_44
831 select SYS_FSL_ERRATUM_A004510
832 select SYS_FSL_ERRATUM_A006261
833 select SYS_FSL_ERRATUM_DDR_A003
834 select SYS_FSL_ERRATUM_DDR_A003474
835 select SYS_FSL_ERRATUM_ESDHC111
836 select SYS_FSL_ERRATUM_I2C_A004447
837 select SYS_FSL_ERRATUM_SRIO_A004034
838 select SYS_FSL_ERRATUM_USB14
839 select SYS_FSL_HAS_DDR3
840 select SYS_FSL_HAS_SEC
841 select SYS_FSL_QORIQ_CHASSIS1
842 select SYS_FSL_SEC_BE
843 select SYS_FSL_SEC_COMPAT_4
852 select SYS_FSL_DDR_VER_44
853 select SYS_FSL_ERRATUM_A004510
854 select SYS_FSL_ERRATUM_A004699
855 select SYS_FSL_ERRATUM_A005812
856 select SYS_FSL_ERRATUM_A006261
857 select SYS_FSL_ERRATUM_DDR_A003
858 select SYS_FSL_ERRATUM_DDR_A003474
859 select SYS_FSL_ERRATUM_ESDHC111
860 select SYS_FSL_ERRATUM_USB14
861 select SYS_FSL_HAS_DDR3
862 select SYS_FSL_HAS_SEC
863 select SYS_FSL_QORIQ_CHASSIS1
864 select SYS_FSL_SEC_BE
865 select SYS_FSL_SEC_COMPAT_4
870 config ARCH_QEMU_E500
877 select SYS_FSL_DDR_VER_50
878 select SYS_FSL_ERRATUM_A008378
879 select SYS_FSL_ERRATUM_A009663
880 select SYS_FSL_ERRATUM_A009942
881 select SYS_FSL_ERRATUM_ESDHC111
882 select SYS_FSL_HAS_DDR3
883 select SYS_FSL_HAS_DDR4
884 select SYS_FSL_HAS_SEC
885 select SYS_FSL_QORIQ_CHASSIS2
886 select SYS_FSL_SEC_BE
887 select SYS_FSL_SEC_COMPAT_5
895 select SYS_FSL_DDR_VER_50
896 select SYS_FSL_ERRATUM_A008378
897 select SYS_FSL_ERRATUM_A009663
898 select SYS_FSL_ERRATUM_A009942
899 select SYS_FSL_ERRATUM_ESDHC111
900 select SYS_FSL_HAS_DDR3
901 select SYS_FSL_HAS_DDR4
902 select SYS_FSL_HAS_SEC
903 select SYS_FSL_QORIQ_CHASSIS2
904 select SYS_FSL_SEC_BE
905 select SYS_FSL_SEC_COMPAT_5
914 select SYS_FSL_DDR_VER_50
915 select SYS_FSL_ERRATUM_A008044
916 select SYS_FSL_ERRATUM_A008378
917 select SYS_FSL_ERRATUM_A009663
918 select SYS_FSL_ERRATUM_A009942
919 select SYS_FSL_ERRATUM_ESDHC111
920 select SYS_FSL_HAS_DDR3
921 select SYS_FSL_HAS_DDR4
922 select SYS_FSL_HAS_SEC
923 select SYS_FSL_QORIQ_CHASSIS2
924 select SYS_FSL_SEC_BE
925 select SYS_FSL_SEC_COMPAT_5
934 select SYS_FSL_DDR_VER_50
935 select SYS_FSL_ERRATUM_A008044
936 select SYS_FSL_ERRATUM_A008378
937 select SYS_FSL_ERRATUM_A009663
938 select SYS_FSL_ERRATUM_A009942
939 select SYS_FSL_ERRATUM_ESDHC111
940 select SYS_FSL_HAS_DDR3
941 select SYS_FSL_HAS_DDR4
942 select SYS_FSL_HAS_SEC
943 select SYS_FSL_QORIQ_CHASSIS2
944 select SYS_FSL_SEC_BE
945 select SYS_FSL_SEC_COMPAT_5
955 select SYS_FSL_DDR_VER_47
956 select SYS_FSL_ERRATUM_A006379
957 select SYS_FSL_ERRATUM_A006593
958 select SYS_FSL_ERRATUM_A007186
959 select SYS_FSL_ERRATUM_A007212
960 select SYS_FSL_ERRATUM_A007815
961 select SYS_FSL_ERRATUM_A007907
962 select SYS_FSL_ERRATUM_A009942
963 select SYS_FSL_ERRATUM_ESDHC111
964 select SYS_FSL_HAS_DDR3
965 select SYS_FSL_HAS_SEC
966 select SYS_FSL_QORIQ_CHASSIS2
967 select SYS_FSL_SEC_BE
968 select SYS_FSL_SEC_COMPAT_4
978 select SYS_FSL_DDR_VER_47
979 select SYS_FSL_ERRATUM_A006379
980 select SYS_FSL_ERRATUM_A006593
981 select SYS_FSL_ERRATUM_A007186
982 select SYS_FSL_ERRATUM_A007212
983 select SYS_FSL_ERRATUM_A009942
984 select SYS_FSL_ERRATUM_ESDHC111
985 select SYS_FSL_HAS_DDR3
986 select SYS_FSL_HAS_SEC
987 select SYS_FSL_QORIQ_CHASSIS2
988 select SYS_FSL_SEC_BE
989 select SYS_FSL_SEC_COMPAT_4
998 select SYS_FSL_DDR_VER_47
999 select SYS_FSL_ERRATUM_A004468
1000 select SYS_FSL_ERRATUM_A005871
1001 select SYS_FSL_ERRATUM_A006379
1002 select SYS_FSL_ERRATUM_A006593
1003 select SYS_FSL_ERRATUM_A007186
1004 select SYS_FSL_ERRATUM_A007798
1005 select SYS_FSL_ERRATUM_A009942
1006 select SYS_FSL_HAS_DDR3
1007 select SYS_FSL_HAS_SEC
1008 select SYS_FSL_QORIQ_CHASSIS2
1009 select SYS_FSL_SEC_BE
1010 select SYS_FSL_SEC_COMPAT_4
1020 select SYS_FSL_DDR_VER_47
1021 select SYS_FSL_ERRATUM_A004468
1022 select SYS_FSL_ERRATUM_A005871
1023 select SYS_FSL_ERRATUM_A006261
1024 select SYS_FSL_ERRATUM_A006379
1025 select SYS_FSL_ERRATUM_A006593
1026 select SYS_FSL_ERRATUM_A007186
1027 select SYS_FSL_ERRATUM_A007798
1028 select SYS_FSL_ERRATUM_A007815
1029 select SYS_FSL_ERRATUM_A007907
1030 select SYS_FSL_ERRATUM_A009942
1031 select SYS_FSL_HAS_DDR3
1032 select SYS_FSL_HAS_SEC
1033 select SYS_FSL_QORIQ_CHASSIS2
1034 select SYS_FSL_SEC_BE
1035 select SYS_FSL_SEC_COMPAT_4
1048 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1053 Enble PowerPC E500MC core
1058 Enable PowerPC E6500 core
1063 Use Freescale common code for Local Access Window
1068 Enable Freescale Secure Boot feature. Normally selected
1069 by defconfig. If unsure, do not change.
1072 int "Maximum number of CPUs permitted for MPC85xx"
1073 default 12 if ARCH_T4240
1074 default 8 if ARCH_P4080 || \
1076 default 4 if ARCH_B4860 || \
1084 default 2 if ARCH_B4420 || \
1099 Set this number to the maximum number of possible CPUs in the SoC.
1100 SoCs may have multiple clusters with each cluster may have multiple
1101 ports. If some ports are reserved but higher ports are used for
1102 cores, count the reserved ports. This will allocate enough memory
1103 in spin table to properly handle all cores.
1105 config SYS_CCSRBAR_DEFAULT
1106 hex "Default CCSRBAR address"
1107 default 0xff700000 if ARCH_BSC9131 || \
1128 default 0xff600000 if ARCH_P1023
1129 default 0xfe000000 if ARCH_B4420 || \
1144 default 0xe0000000 if ARCH_QEMU_E500
1146 Default value of CCSRBAR comes from power-on-reset. It
1147 is fixed on each SoC. Some SoCs can have different value
1148 if changed by pre-boot regime. The value here must match
1149 the current value in SoC. If not sure, do not change.
1151 config SYS_FSL_ERRATUM_A004468
1154 config SYS_FSL_ERRATUM_A004477
1157 config SYS_FSL_ERRATUM_A004508
1160 config SYS_FSL_ERRATUM_A004580
1163 config SYS_FSL_ERRATUM_A004699
1166 config SYS_FSL_ERRATUM_A004849
1169 config SYS_FSL_ERRATUM_A004510
1172 config SYS_FSL_ERRATUM_A004510_SVR_REV
1174 depends on SYS_FSL_ERRATUM_A004510
1175 default 0x20 if ARCH_P4080
1178 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1180 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1183 config SYS_FSL_ERRATUM_A005125
1186 config SYS_FSL_ERRATUM_A005434
1189 config SYS_FSL_ERRATUM_A005812
1192 config SYS_FSL_ERRATUM_A005871
1195 config SYS_FSL_ERRATUM_A006261
1198 config SYS_FSL_ERRATUM_A006379
1201 config SYS_FSL_ERRATUM_A006384
1204 config SYS_FSL_ERRATUM_A006475
1207 config SYS_FSL_ERRATUM_A006593
1210 config SYS_FSL_ERRATUM_A007075
1213 config SYS_FSL_ERRATUM_A007186
1216 config SYS_FSL_ERRATUM_A007212
1219 config SYS_FSL_ERRATUM_A007815
1222 config SYS_FSL_ERRATUM_A007798
1225 config SYS_FSL_ERRATUM_A007907
1228 config SYS_FSL_ERRATUM_A008044
1231 config SYS_FSL_ERRATUM_CPC_A002
1234 config SYS_FSL_ERRATUM_CPC_A003
1237 config SYS_FSL_ERRATUM_CPU_A003999
1240 config SYS_FSL_ERRATUM_ELBC_A001
1243 config SYS_FSL_ERRATUM_I2C_A004447
1246 config SYS_FSL_A004447_SVR_REV
1248 depends on SYS_FSL_ERRATUM_I2C_A004447
1249 default 0x00 if ARCH_MPC8548
1250 default 0x10 if ARCH_P1010
1251 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1252 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1254 config SYS_FSL_ERRATUM_IFC_A002769
1257 config SYS_FSL_ERRATUM_IFC_A003399
1260 config SYS_FSL_ERRATUM_NMG_CPU_A011
1263 config SYS_FSL_ERRATUM_NMG_ETSEC129
1266 config SYS_FSL_ERRATUM_NMG_LBC103
1269 config SYS_FSL_ERRATUM_P1010_A003549
1272 config SYS_FSL_ERRATUM_SATA_A001
1275 config SYS_FSL_ERRATUM_SEC_A003571
1278 config SYS_FSL_ERRATUM_SRIO_A004034
1281 config SYS_FSL_ERRATUM_USB14
1284 config SYS_P4080_ERRATUM_CPU22
1287 config SYS_P4080_ERRATUM_PCIE_A003
1290 config SYS_P4080_ERRATUM_SERDES8
1293 config SYS_P4080_ERRATUM_SERDES9
1296 config SYS_P4080_ERRATUM_SERDES_A001
1299 config SYS_P4080_ERRATUM_SERDES_A005
1302 config SYS_FSL_QORIQ_CHASSIS1
1305 config SYS_FSL_QORIQ_CHASSIS2
1308 config SYS_FSL_NUM_LAWS
1309 int "Number of local access windows"
1311 default 32 if ARCH_B4420 || \
1322 default 16 if ARCH_T1023 || \
1326 default 12 if ARCH_BSC9131 || \
1340 default 10 if ARCH_MPC8544 || \
1344 default 8 if ARCH_MPC8540 || \
1349 Number of local access windows. This is fixed per SoC.
1350 If not sure, do not change.
1352 config SYS_FSL_THREADS_PER_CORE
1357 config SYS_NUM_TLBCAMS
1358 int "Number of TLB CAM entries"
1359 default 64 if E500MC
1362 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1363 16 for other E500 SoCs.
1368 config SYS_PPC_E500_USE_DEBUG_TLB
1377 config SYS_PPC_E500_DEBUG_TLB
1378 int "Temporary TLB entry for external debugger"
1379 depends on SYS_PPC_E500_USE_DEBUG_TLB
1380 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1381 default 1 if ARCH_MPC8536
1382 default 2 if ARCH_MPC8572 || \
1390 default 3 if ARCH_P1010 || \
1394 Select a temporary TLB entry to be used during boot to work
1395 around limitations in e500v1 and e500v2 external debugger
1396 support. This reduces the portions of the boot code where
1397 breakpoints and single stepping do not work. The value of this
1398 symbol should be set to the TLB1 entry to be used for this
1399 purpose. If unsure, do not change.
1401 config SYS_FSL_IFC_CLK_DIV
1402 int "Divider of platform clock"
1404 default 2 if ARCH_B4420 || \
1414 Defines divider of platform clock(clock input to
1417 config SYS_FSL_LBC_CLK_DIV
1418 int "Divider of platform clock"
1419 depends on FSL_ELBC || ARCH_MPC8540 || \
1420 ARCH_MPC8548 || ARCH_MPC8541 || \
1421 ARCH_MPC8555 || ARCH_MPC8560 || \
1424 default 2 if ARCH_P2041 || \
1432 Defines divider of platform clock(clock input to
1435 source "board/freescale/b4860qds/Kconfig"
1436 source "board/freescale/bsc9131rdb/Kconfig"
1437 source "board/freescale/bsc9132qds/Kconfig"
1438 source "board/freescale/c29xpcie/Kconfig"
1439 source "board/freescale/corenet_ds/Kconfig"
1440 source "board/freescale/mpc8536ds/Kconfig"
1441 source "board/freescale/mpc8541cds/Kconfig"
1442 source "board/freescale/mpc8544ds/Kconfig"
1443 source "board/freescale/mpc8548cds/Kconfig"
1444 source "board/freescale/mpc8555cds/Kconfig"
1445 source "board/freescale/mpc8568mds/Kconfig"
1446 source "board/freescale/mpc8569mds/Kconfig"
1447 source "board/freescale/mpc8572ds/Kconfig"
1448 source "board/freescale/p1010rdb/Kconfig"
1449 source "board/freescale/p1022ds/Kconfig"
1450 source "board/freescale/p1023rdb/Kconfig"
1451 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1452 source "board/freescale/p1_twr/Kconfig"
1453 source "board/freescale/p2041rdb/Kconfig"
1454 source "board/freescale/qemu-ppce500/Kconfig"
1455 source "board/freescale/t102xqds/Kconfig"
1456 source "board/freescale/t102xrdb/Kconfig"
1457 source "board/freescale/t1040qds/Kconfig"
1458 source "board/freescale/t104xrdb/Kconfig"
1459 source "board/freescale/t208xqds/Kconfig"
1460 source "board/freescale/t208xrdb/Kconfig"
1461 source "board/freescale/t4qds/Kconfig"
1462 source "board/freescale/t4rdb/Kconfig"
1463 source "board/gdsys/p1022/Kconfig"
1464 source "board/keymile/kmp204x/Kconfig"
1465 source "board/sbc8548/Kconfig"
1466 source "board/socrates/Kconfig"
1467 source "board/varisys/cyrus/Kconfig"
1468 source "board/xes/xpedite520x/Kconfig"
1469 source "board/xes/xpedite537x/Kconfig"
1470 source "board/xes/xpedite550x/Kconfig"
1471 source "board/Arcturus/ucp1020/Kconfig"