8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_B4420QDS
28 bool "Support B4420QDS"
33 config TARGET_B4860QDS
34 bool "Support B4860QDS"
36 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 config TARGET_BSC9131RDB
41 bool "Support BSC9131RDB"
44 select BOARD_EARLY_INIT_F
46 config TARGET_BSC9132QDS
47 bool "Support BSC9132QDS"
49 select BOARD_LATE_INIT if CHAIN_OF_TRUST
51 select BOARD_EARLY_INIT_F
53 config TARGET_C29XPCIE
54 bool "Support C29XPCIE"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
62 bool "Support P3041DS"
65 select BOARD_LATE_INIT if CHAIN_OF_TRUST
68 bool "Support P4080DS"
71 select BOARD_LATE_INIT if CHAIN_OF_TRUST
74 bool "Support P5020DS"
77 select BOARD_LATE_INIT if CHAIN_OF_TRUST
80 bool "Support P5040DS"
83 select BOARD_LATE_INIT if CHAIN_OF_TRUST
85 config TARGET_MPC8536DS
86 bool "Support MPC8536DS"
88 # Use DDR3 controller with DDR2 DIMMs on this board
89 select SYS_FSL_DDRC_GEN3
91 config TARGET_MPC8541CDS
92 bool "Support MPC8541CDS"
95 config TARGET_MPC8544DS
96 bool "Support MPC8544DS"
99 config TARGET_MPC8548CDS
100 bool "Support MPC8548CDS"
103 config TARGET_MPC8555CDS
104 bool "Support MPC8555CDS"
107 config TARGET_MPC8568MDS
108 bool "Support MPC8568MDS"
111 config TARGET_MPC8569MDS
112 bool "Support MPC8569MDS"
115 config TARGET_MPC8572DS
116 bool "Support MPC8572DS"
118 # Use DDR3 controller with DDR2 DIMMs on this board
119 select SYS_FSL_DDRC_GEN3
122 config TARGET_P1010RDB_PA
123 bool "Support P1010RDB_PA"
125 select BOARD_LATE_INIT if CHAIN_OF_TRUST
130 config TARGET_P1010RDB_PB
131 bool "Support P1010RDB_PB"
133 select BOARD_LATE_INIT if CHAIN_OF_TRUST
138 config TARGET_P1022DS
139 bool "Support P1022DS"
144 config TARGET_P1023RDB
145 bool "Support P1023RDB"
149 config TARGET_P1020MBG
150 bool "Support P1020MBG-PC"
156 config TARGET_P1020RDB_PC
157 bool "Support P1020RDB-PC"
163 config TARGET_P1020RDB_PD
164 bool "Support P1020RDB-PD"
170 config TARGET_P1020UTM
171 bool "Support P1020UTM"
177 config TARGET_P1021RDB
178 bool "Support P1021RDB"
184 config TARGET_P1024RDB
185 bool "Support P1024RDB"
191 config TARGET_P1025RDB
192 bool "Support P1025RDB"
198 config TARGET_P2020RDB
199 bool "Support P2020RDB-PC"
206 bool "Support p1_twr"
209 config TARGET_P2041RDB
210 bool "Support P2041RDB"
212 select BOARD_LATE_INIT if CHAIN_OF_TRUST
215 config TARGET_QEMU_PPCE500
216 bool "Support qemu-ppce500"
217 select ARCH_QEMU_E500
220 config TARGET_T1024QDS
221 bool "Support T1024QDS"
223 select BOARD_LATE_INIT if CHAIN_OF_TRUST
228 config TARGET_T1023RDB
229 bool "Support T1023RDB"
231 select BOARD_LATE_INIT if CHAIN_OF_TRUST
236 config TARGET_T1024RDB
237 bool "Support T1024RDB"
239 select BOARD_LATE_INIT if CHAIN_OF_TRUST
244 config TARGET_T1040QDS
245 bool "Support T1040QDS"
247 select BOARD_LATE_INIT if CHAIN_OF_TRUST
251 config TARGET_T1040RDB
252 bool "Support T1040RDB"
254 select BOARD_LATE_INIT if CHAIN_OF_TRUST
258 config TARGET_T1040D4RDB
259 bool "Support T1040D4RDB"
261 select BOARD_LATE_INIT if CHAIN_OF_TRUST
265 config TARGET_T1042RDB
266 bool "Support T1042RDB"
268 select BOARD_LATE_INIT if CHAIN_OF_TRUST
272 config TARGET_T1042D4RDB
273 bool "Support T1042D4RDB"
275 select BOARD_LATE_INIT if CHAIN_OF_TRUST
279 config TARGET_T1042RDB_PI
280 bool "Support T1042RDB_PI"
282 select BOARD_LATE_INIT if CHAIN_OF_TRUST
286 config TARGET_T2080QDS
287 bool "Support T2080QDS"
289 select BOARD_LATE_INIT if CHAIN_OF_TRUST
293 config TARGET_T2080RDB
294 bool "Support T2080RDB"
296 select BOARD_LATE_INIT if CHAIN_OF_TRUST
300 config TARGET_T2081QDS
301 bool "Support T2081QDS"
306 config TARGET_T4160QDS
307 bool "Support T4160QDS"
309 select BOARD_LATE_INIT if CHAIN_OF_TRUST
313 config TARGET_T4160RDB
314 bool "Support T4160RDB"
319 config TARGET_T4240QDS
320 bool "Support T4240QDS"
322 select BOARD_LATE_INIT if CHAIN_OF_TRUST
326 config TARGET_T4240RDB
327 bool "Support T4240RDB"
332 config TARGET_CONTROLCENTERD
333 bool "Support controlcenterd"
336 config TARGET_KMP204X
337 bool "Support kmp204x"
343 config TARGET_XPEDITE520X
344 bool "Support xpedite520x"
347 config TARGET_XPEDITE537X
348 bool "Support xpedite537x"
350 # Use DDR3 controller with DDR2 DIMMs on this board
351 select SYS_FSL_DDRC_GEN3
353 config TARGET_XPEDITE550X
354 bool "Support xpedite550x"
357 config TARGET_UCP1020
358 bool "Support uCP1020"
361 config TARGET_CYRUS_P5020
362 bool "Support Varisys Cyrus P5020"
366 config TARGET_CYRUS_P5040
367 bool "Support Varisys Cyrus P5040"
378 select SYS_FSL_DDR_VER_47
379 select SYS_FSL_ERRATUM_A004477
380 select SYS_FSL_ERRATUM_A005871
381 select SYS_FSL_ERRATUM_A006379
382 select SYS_FSL_ERRATUM_A006384
383 select SYS_FSL_ERRATUM_A006475
384 select SYS_FSL_ERRATUM_A006593
385 select SYS_FSL_ERRATUM_A007075
386 select SYS_FSL_ERRATUM_A007186
387 select SYS_FSL_ERRATUM_A007212
388 select SYS_FSL_ERRATUM_A009942
389 select SYS_FSL_HAS_DDR3
390 select SYS_FSL_HAS_SEC
391 select SYS_FSL_QORIQ_CHASSIS2
392 select SYS_FSL_SEC_BE
393 select SYS_FSL_SEC_COMPAT_4
403 select SYS_FSL_DDR_VER_47
404 select SYS_FSL_ERRATUM_A004477
405 select SYS_FSL_ERRATUM_A005871
406 select SYS_FSL_ERRATUM_A006379
407 select SYS_FSL_ERRATUM_A006384
408 select SYS_FSL_ERRATUM_A006475
409 select SYS_FSL_ERRATUM_A006593
410 select SYS_FSL_ERRATUM_A007075
411 select SYS_FSL_ERRATUM_A007186
412 select SYS_FSL_ERRATUM_A007212
413 select SYS_FSL_ERRATUM_A007907
414 select SYS_FSL_ERRATUM_A009942
415 select SYS_FSL_HAS_DDR3
416 select SYS_FSL_HAS_SEC
417 select SYS_FSL_QORIQ_CHASSIS2
418 select SYS_FSL_SEC_BE
419 select SYS_FSL_SEC_COMPAT_4
427 select SYS_FSL_DDR_VER_44
428 select SYS_FSL_ERRATUM_A004477
429 select SYS_FSL_ERRATUM_A005125
430 select SYS_FSL_ERRATUM_ESDHC111
431 select SYS_FSL_HAS_DDR3
432 select SYS_FSL_HAS_SEC
433 select SYS_FSL_SEC_BE
434 select SYS_FSL_SEC_COMPAT_4
441 select SYS_FSL_DDR_VER_46
442 select SYS_FSL_ERRATUM_A004477
443 select SYS_FSL_ERRATUM_A005125
444 select SYS_FSL_ERRATUM_A005434
445 select SYS_FSL_ERRATUM_ESDHC111
446 select SYS_FSL_ERRATUM_I2C_A004447
447 select SYS_FSL_ERRATUM_IFC_A002769
448 select SYS_FSL_HAS_DDR3
449 select SYS_FSL_HAS_SEC
450 select SYS_FSL_SEC_BE
451 select SYS_FSL_SEC_COMPAT_4
452 select SYS_PPC_E500_USE_DEBUG_TLB
459 select SYS_FSL_DDR_VER_46
460 select SYS_FSL_ERRATUM_A005125
461 select SYS_FSL_ERRATUM_ESDHC111
462 select SYS_FSL_HAS_DDR3
463 select SYS_FSL_HAS_SEC
464 select SYS_FSL_SEC_BE
465 select SYS_FSL_SEC_COMPAT_6
466 select SYS_PPC_E500_USE_DEBUG_TLB
472 select SYS_FSL_ERRATUM_A004508
473 select SYS_FSL_ERRATUM_A005125
474 select SYS_FSL_HAS_DDR2
475 select SYS_FSL_HAS_DDR3
476 select SYS_FSL_HAS_SEC
477 select SYS_FSL_SEC_BE
478 select SYS_FSL_SEC_COMPAT_2
479 select SYS_PPC_E500_USE_DEBUG_TLB
485 select SYS_FSL_HAS_DDR1
490 select SYS_FSL_HAS_DDR1
491 select SYS_FSL_HAS_SEC
492 select SYS_FSL_SEC_BE
493 select SYS_FSL_SEC_COMPAT_2
498 select SYS_FSL_ERRATUM_A005125
499 select SYS_FSL_HAS_DDR2
500 select SYS_FSL_HAS_SEC
501 select SYS_FSL_SEC_BE
502 select SYS_FSL_SEC_COMPAT_2
503 select SYS_PPC_E500_USE_DEBUG_TLB
509 select SYS_FSL_ERRATUM_A005125
510 select SYS_FSL_ERRATUM_NMG_DDR120
511 select SYS_FSL_ERRATUM_NMG_LBC103
512 select SYS_FSL_ERRATUM_NMG_ETSEC129
513 select SYS_FSL_ERRATUM_I2C_A004447
514 select SYS_FSL_HAS_DDR2
515 select SYS_FSL_HAS_DDR1
516 select SYS_FSL_HAS_SEC
517 select SYS_FSL_SEC_BE
518 select SYS_FSL_SEC_COMPAT_2
519 select SYS_PPC_E500_USE_DEBUG_TLB
524 select SYS_FSL_HAS_DDR1
525 select SYS_FSL_HAS_SEC
526 select SYS_FSL_SEC_BE
527 select SYS_FSL_SEC_COMPAT_2
532 select SYS_FSL_HAS_DDR1
537 select SYS_FSL_HAS_DDR2
538 select SYS_FSL_HAS_SEC
539 select SYS_FSL_SEC_BE
540 select SYS_FSL_SEC_COMPAT_2
545 select SYS_FSL_ERRATUM_A004508
546 select SYS_FSL_ERRATUM_A005125
547 select SYS_FSL_HAS_DDR3
548 select SYS_FSL_HAS_SEC
549 select SYS_FSL_SEC_BE
550 select SYS_FSL_SEC_COMPAT_2
556 select SYS_FSL_ERRATUM_A004508
557 select SYS_FSL_ERRATUM_A005125
558 select SYS_FSL_ERRATUM_DDR_115
559 select SYS_FSL_ERRATUM_DDR111_DDR134
560 select SYS_FSL_HAS_DDR2
561 select SYS_FSL_HAS_DDR3
562 select SYS_FSL_HAS_SEC
563 select SYS_FSL_SEC_BE
564 select SYS_FSL_SEC_COMPAT_2
565 select SYS_PPC_E500_USE_DEBUG_TLB
571 select SYS_FSL_ERRATUM_A004477
572 select SYS_FSL_ERRATUM_A004508
573 select SYS_FSL_ERRATUM_A005125
574 select SYS_FSL_ERRATUM_A006261
575 select SYS_FSL_ERRATUM_A007075
576 select SYS_FSL_ERRATUM_ESDHC111
577 select SYS_FSL_ERRATUM_I2C_A004447
578 select SYS_FSL_ERRATUM_IFC_A002769
579 select SYS_FSL_ERRATUM_P1010_A003549
580 select SYS_FSL_ERRATUM_SEC_A003571
581 select SYS_FSL_ERRATUM_IFC_A003399
582 select SYS_FSL_HAS_DDR3
583 select SYS_FSL_HAS_SEC
584 select SYS_FSL_SEC_BE
585 select SYS_FSL_SEC_COMPAT_4
586 select SYS_PPC_E500_USE_DEBUG_TLB
593 select SYS_FSL_ERRATUM_A004508
594 select SYS_FSL_ERRATUM_A005125
595 select SYS_FSL_ERRATUM_ELBC_A001
596 select SYS_FSL_ERRATUM_ESDHC111
597 select SYS_FSL_HAS_DDR3
598 select SYS_FSL_HAS_SEC
599 select SYS_FSL_SEC_BE
600 select SYS_FSL_SEC_COMPAT_2
601 select SYS_PPC_E500_USE_DEBUG_TLB
607 select SYS_FSL_ERRATUM_A004508
608 select SYS_FSL_ERRATUM_A005125
609 select SYS_FSL_ERRATUM_ELBC_A001
610 select SYS_FSL_ERRATUM_ESDHC111
611 select SYS_FSL_HAS_DDR3
612 select SYS_FSL_HAS_SEC
613 select SYS_FSL_SEC_BE
614 select SYS_FSL_SEC_COMPAT_2
615 select SYS_PPC_E500_USE_DEBUG_TLB
621 select SYS_FSL_ERRATUM_A004508
622 select SYS_FSL_ERRATUM_A005125
623 select SYS_FSL_ERRATUM_ELBC_A001
624 select SYS_FSL_ERRATUM_ESDHC111
625 select SYS_FSL_HAS_DDR3
626 select SYS_FSL_HAS_SEC
627 select SYS_FSL_SEC_BE
628 select SYS_FSL_SEC_COMPAT_2
629 select SYS_PPC_E500_USE_DEBUG_TLB
635 select SYS_FSL_ERRATUM_A004477
636 select SYS_FSL_ERRATUM_A004508
637 select SYS_FSL_ERRATUM_A005125
638 select SYS_FSL_ERRATUM_ELBC_A001
639 select SYS_FSL_ERRATUM_ESDHC111
640 select SYS_FSL_ERRATUM_SATA_A001
641 select SYS_FSL_HAS_DDR3
642 select SYS_FSL_HAS_SEC
643 select SYS_FSL_SEC_BE
644 select SYS_FSL_SEC_COMPAT_2
645 select SYS_PPC_E500_USE_DEBUG_TLB
651 select SYS_FSL_ERRATUM_A004508
652 select SYS_FSL_ERRATUM_A005125
653 select SYS_FSL_ERRATUM_I2C_A004447
654 select SYS_FSL_HAS_DDR3
655 select SYS_FSL_HAS_SEC
656 select SYS_FSL_SEC_BE
657 select SYS_FSL_SEC_COMPAT_4
663 select SYS_FSL_ERRATUM_A004508
664 select SYS_FSL_ERRATUM_A005125
665 select SYS_FSL_ERRATUM_ELBC_A001
666 select SYS_FSL_ERRATUM_ESDHC111
667 select SYS_FSL_HAS_DDR3
668 select SYS_FSL_HAS_SEC
669 select SYS_FSL_SEC_BE
670 select SYS_FSL_SEC_COMPAT_2
671 select SYS_PPC_E500_USE_DEBUG_TLB
678 select SYS_FSL_ERRATUM_A004508
679 select SYS_FSL_ERRATUM_A005125
680 select SYS_FSL_ERRATUM_ELBC_A001
681 select SYS_FSL_ERRATUM_ESDHC111
682 select SYS_FSL_HAS_DDR3
683 select SYS_FSL_HAS_SEC
684 select SYS_FSL_SEC_BE
685 select SYS_FSL_SEC_COMPAT_2
686 select SYS_PPC_E500_USE_DEBUG_TLB
692 select SYS_FSL_ERRATUM_A004477
693 select SYS_FSL_ERRATUM_A004508
694 select SYS_FSL_ERRATUM_A005125
695 select SYS_FSL_ERRATUM_ESDHC111
696 select SYS_FSL_ERRATUM_ESDHC_A001
697 select SYS_FSL_HAS_DDR3
698 select SYS_FSL_HAS_SEC
699 select SYS_FSL_SEC_BE
700 select SYS_FSL_SEC_COMPAT_2
701 select SYS_PPC_E500_USE_DEBUG_TLB
709 select SYS_FSL_ERRATUM_A004510
710 select SYS_FSL_ERRATUM_A004849
711 select SYS_FSL_ERRATUM_A006261
712 select SYS_FSL_ERRATUM_CPU_A003999
713 select SYS_FSL_ERRATUM_DDR_A003
714 select SYS_FSL_ERRATUM_DDR_A003474
715 select SYS_FSL_ERRATUM_ESDHC111
716 select SYS_FSL_ERRATUM_I2C_A004447
717 select SYS_FSL_ERRATUM_NMG_CPU_A011
718 select SYS_FSL_ERRATUM_SRIO_A004034
719 select SYS_FSL_ERRATUM_USB14
720 select SYS_FSL_HAS_DDR3
721 select SYS_FSL_HAS_SEC
722 select SYS_FSL_QORIQ_CHASSIS1
723 select SYS_FSL_SEC_BE
724 select SYS_FSL_SEC_COMPAT_4
731 select SYS_FSL_DDR_VER_44
732 select SYS_FSL_ERRATUM_A004510
733 select SYS_FSL_ERRATUM_A004849
734 select SYS_FSL_ERRATUM_A005812
735 select SYS_FSL_ERRATUM_A006261
736 select SYS_FSL_ERRATUM_CPU_A003999
737 select SYS_FSL_ERRATUM_DDR_A003
738 select SYS_FSL_ERRATUM_DDR_A003474
739 select SYS_FSL_ERRATUM_ESDHC111
740 select SYS_FSL_ERRATUM_I2C_A004447
741 select SYS_FSL_ERRATUM_NMG_CPU_A011
742 select SYS_FSL_ERRATUM_SRIO_A004034
743 select SYS_FSL_ERRATUM_USB14
744 select SYS_FSL_HAS_DDR3
745 select SYS_FSL_HAS_SEC
746 select SYS_FSL_QORIQ_CHASSIS1
747 select SYS_FSL_SEC_BE
748 select SYS_FSL_SEC_COMPAT_4
755 select SYS_FSL_DDR_VER_44
756 select SYS_FSL_ERRATUM_A004510
757 select SYS_FSL_ERRATUM_A004580
758 select SYS_FSL_ERRATUM_A004849
759 select SYS_FSL_ERRATUM_A005812
760 select SYS_FSL_ERRATUM_A007075
761 select SYS_FSL_ERRATUM_CPC_A002
762 select SYS_FSL_ERRATUM_CPC_A003
763 select SYS_FSL_ERRATUM_CPU_A003999
764 select SYS_FSL_ERRATUM_DDR_A003
765 select SYS_FSL_ERRATUM_DDR_A003474
766 select SYS_FSL_ERRATUM_ELBC_A001
767 select SYS_FSL_ERRATUM_ESDHC111
768 select SYS_FSL_ERRATUM_ESDHC13
769 select SYS_FSL_ERRATUM_ESDHC135
770 select SYS_FSL_ERRATUM_I2C_A004447
771 select SYS_FSL_ERRATUM_NMG_CPU_A011
772 select SYS_FSL_ERRATUM_SRIO_A004034
773 select SYS_P4080_ERRATUM_CPU22
774 select SYS_P4080_ERRATUM_PCIE_A003
775 select SYS_P4080_ERRATUM_SERDES8
776 select SYS_P4080_ERRATUM_SERDES9
777 select SYS_P4080_ERRATUM_SERDES_A001
778 select SYS_P4080_ERRATUM_SERDES_A005
779 select SYS_FSL_HAS_DDR3
780 select SYS_FSL_HAS_SEC
781 select SYS_FSL_QORIQ_CHASSIS1
782 select SYS_FSL_SEC_BE
783 select SYS_FSL_SEC_COMPAT_4
790 select SYS_FSL_DDR_VER_44
791 select SYS_FSL_ERRATUM_A004510
792 select SYS_FSL_ERRATUM_A006261
793 select SYS_FSL_ERRATUM_DDR_A003
794 select SYS_FSL_ERRATUM_DDR_A003474
795 select SYS_FSL_ERRATUM_ESDHC111
796 select SYS_FSL_ERRATUM_I2C_A004447
797 select SYS_FSL_ERRATUM_SRIO_A004034
798 select SYS_FSL_ERRATUM_USB14
799 select SYS_FSL_HAS_DDR3
800 select SYS_FSL_HAS_SEC
801 select SYS_FSL_QORIQ_CHASSIS1
802 select SYS_FSL_SEC_BE
803 select SYS_FSL_SEC_COMPAT_4
811 select SYS_FSL_DDR_VER_44
812 select SYS_FSL_ERRATUM_A004510
813 select SYS_FSL_ERRATUM_A004699
814 select SYS_FSL_ERRATUM_A005812
815 select SYS_FSL_ERRATUM_A006261
816 select SYS_FSL_ERRATUM_DDR_A003
817 select SYS_FSL_ERRATUM_DDR_A003474
818 select SYS_FSL_ERRATUM_ESDHC111
819 select SYS_FSL_ERRATUM_USB14
820 select SYS_FSL_HAS_DDR3
821 select SYS_FSL_HAS_SEC
822 select SYS_FSL_QORIQ_CHASSIS1
823 select SYS_FSL_SEC_BE
824 select SYS_FSL_SEC_COMPAT_4
828 config ARCH_QEMU_E500
835 select SYS_FSL_DDR_VER_50
836 select SYS_FSL_ERRATUM_A008378
837 select SYS_FSL_ERRATUM_A009663
838 select SYS_FSL_ERRATUM_A009942
839 select SYS_FSL_ERRATUM_ESDHC111
840 select SYS_FSL_HAS_DDR3
841 select SYS_FSL_HAS_DDR4
842 select SYS_FSL_HAS_SEC
843 select SYS_FSL_QORIQ_CHASSIS2
844 select SYS_FSL_SEC_BE
845 select SYS_FSL_SEC_COMPAT_5
853 select SYS_FSL_DDR_VER_50
854 select SYS_FSL_ERRATUM_A008378
855 select SYS_FSL_ERRATUM_A009663
856 select SYS_FSL_ERRATUM_A009942
857 select SYS_FSL_ERRATUM_ESDHC111
858 select SYS_FSL_HAS_DDR3
859 select SYS_FSL_HAS_DDR4
860 select SYS_FSL_HAS_SEC
861 select SYS_FSL_QORIQ_CHASSIS2
862 select SYS_FSL_SEC_BE
863 select SYS_FSL_SEC_COMPAT_5
871 select SYS_FSL_DDR_VER_50
872 select SYS_FSL_ERRATUM_A008044
873 select SYS_FSL_ERRATUM_A008378
874 select SYS_FSL_ERRATUM_A009663
875 select SYS_FSL_ERRATUM_A009942
876 select SYS_FSL_ERRATUM_ESDHC111
877 select SYS_FSL_HAS_DDR3
878 select SYS_FSL_HAS_DDR4
879 select SYS_FSL_HAS_SEC
880 select SYS_FSL_QORIQ_CHASSIS2
881 select SYS_FSL_SEC_BE
882 select SYS_FSL_SEC_COMPAT_5
889 select SYS_FSL_DDR_VER_50
890 select SYS_FSL_ERRATUM_A008044
891 select SYS_FSL_ERRATUM_A008378
892 select SYS_FSL_ERRATUM_A009663
893 select SYS_FSL_ERRATUM_A009942
894 select SYS_FSL_ERRATUM_ESDHC111
895 select SYS_FSL_HAS_DDR3
896 select SYS_FSL_HAS_DDR4
897 select SYS_FSL_HAS_SEC
898 select SYS_FSL_QORIQ_CHASSIS2
899 select SYS_FSL_SEC_BE
900 select SYS_FSL_SEC_COMPAT_5
908 select SYS_FSL_DDR_VER_47
909 select SYS_FSL_ERRATUM_A006379
910 select SYS_FSL_ERRATUM_A006593
911 select SYS_FSL_ERRATUM_A007186
912 select SYS_FSL_ERRATUM_A007212
913 select SYS_FSL_ERRATUM_A007815
914 select SYS_FSL_ERRATUM_A007907
915 select SYS_FSL_ERRATUM_A009942
916 select SYS_FSL_ERRATUM_ESDHC111
917 select SYS_FSL_HAS_DDR3
918 select SYS_FSL_HAS_SEC
919 select SYS_FSL_QORIQ_CHASSIS2
920 select SYS_FSL_SEC_BE
921 select SYS_FSL_SEC_COMPAT_4
930 select SYS_FSL_DDR_VER_47
931 select SYS_FSL_ERRATUM_A006379
932 select SYS_FSL_ERRATUM_A006593
933 select SYS_FSL_ERRATUM_A007186
934 select SYS_FSL_ERRATUM_A007212
935 select SYS_FSL_ERRATUM_A009942
936 select SYS_FSL_ERRATUM_ESDHC111
937 select SYS_FSL_HAS_DDR3
938 select SYS_FSL_HAS_SEC
939 select SYS_FSL_QORIQ_CHASSIS2
940 select SYS_FSL_SEC_BE
941 select SYS_FSL_SEC_COMPAT_4
950 select SYS_FSL_DDR_VER_47
951 select SYS_FSL_ERRATUM_A004468
952 select SYS_FSL_ERRATUM_A005871
953 select SYS_FSL_ERRATUM_A006379
954 select SYS_FSL_ERRATUM_A006593
955 select SYS_FSL_ERRATUM_A007186
956 select SYS_FSL_ERRATUM_A007798
957 select SYS_FSL_ERRATUM_A009942
958 select SYS_FSL_HAS_DDR3
959 select SYS_FSL_HAS_SEC
960 select SYS_FSL_QORIQ_CHASSIS2
961 select SYS_FSL_SEC_BE
962 select SYS_FSL_SEC_COMPAT_4
971 select SYS_FSL_DDR_VER_47
972 select SYS_FSL_ERRATUM_A004468
973 select SYS_FSL_ERRATUM_A005871
974 select SYS_FSL_ERRATUM_A006261
975 select SYS_FSL_ERRATUM_A006379
976 select SYS_FSL_ERRATUM_A006593
977 select SYS_FSL_ERRATUM_A007186
978 select SYS_FSL_ERRATUM_A007798
979 select SYS_FSL_ERRATUM_A007815
980 select SYS_FSL_ERRATUM_A007907
981 select SYS_FSL_ERRATUM_A009942
982 select SYS_FSL_HAS_DDR3
983 select SYS_FSL_HAS_SEC
984 select SYS_FSL_QORIQ_CHASSIS2
985 select SYS_FSL_SEC_BE
986 select SYS_FSL_SEC_COMPAT_4
998 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1003 Enble PowerPC E500MC core
1008 Enable PowerPC E6500 core
1013 Use Freescale common code for Local Access Window
1018 Enable Freescale Secure Boot feature. Normally selected
1019 by defconfig. If unsure, do not change.
1022 int "Maximum number of CPUs permitted for MPC85xx"
1023 default 12 if ARCH_T4240
1024 default 8 if ARCH_P4080 || \
1026 default 4 if ARCH_B4860 || \
1034 default 2 if ARCH_B4420 || \
1049 Set this number to the maximum number of possible CPUs in the SoC.
1050 SoCs may have multiple clusters with each cluster may have multiple
1051 ports. If some ports are reserved but higher ports are used for
1052 cores, count the reserved ports. This will allocate enough memory
1053 in spin table to properly handle all cores.
1055 config SYS_CCSRBAR_DEFAULT
1056 hex "Default CCSRBAR address"
1057 default 0xff700000 if ARCH_BSC9131 || \
1078 default 0xff600000 if ARCH_P1023
1079 default 0xfe000000 if ARCH_B4420 || \
1094 default 0xe0000000 if ARCH_QEMU_E500
1096 Default value of CCSRBAR comes from power-on-reset. It
1097 is fixed on each SoC. Some SoCs can have different value
1098 if changed by pre-boot regime. The value here must match
1099 the current value in SoC. If not sure, do not change.
1101 config SYS_FSL_ERRATUM_A004468
1104 config SYS_FSL_ERRATUM_A004477
1107 config SYS_FSL_ERRATUM_A004508
1110 config SYS_FSL_ERRATUM_A004580
1113 config SYS_FSL_ERRATUM_A004699
1116 config SYS_FSL_ERRATUM_A004849
1119 config SYS_FSL_ERRATUM_A004510
1122 config SYS_FSL_ERRATUM_A004510_SVR_REV
1124 depends on SYS_FSL_ERRATUM_A004510
1125 default 0x20 if ARCH_P4080
1128 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1130 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1133 config SYS_FSL_ERRATUM_A005125
1136 config SYS_FSL_ERRATUM_A005434
1139 config SYS_FSL_ERRATUM_A005812
1142 config SYS_FSL_ERRATUM_A005871
1145 config SYS_FSL_ERRATUM_A006261
1148 config SYS_FSL_ERRATUM_A006379
1151 config SYS_FSL_ERRATUM_A006384
1154 config SYS_FSL_ERRATUM_A006475
1157 config SYS_FSL_ERRATUM_A006593
1160 config SYS_FSL_ERRATUM_A007075
1163 config SYS_FSL_ERRATUM_A007186
1166 config SYS_FSL_ERRATUM_A007212
1169 config SYS_FSL_ERRATUM_A007815
1172 config SYS_FSL_ERRATUM_A007798
1175 config SYS_FSL_ERRATUM_A007907
1178 config SYS_FSL_ERRATUM_A008044
1181 config SYS_FSL_ERRATUM_CPC_A002
1184 config SYS_FSL_ERRATUM_CPC_A003
1187 config SYS_FSL_ERRATUM_CPU_A003999
1190 config SYS_FSL_ERRATUM_ELBC_A001
1193 config SYS_FSL_ERRATUM_I2C_A004447
1196 config SYS_FSL_A004447_SVR_REV
1198 depends on SYS_FSL_ERRATUM_I2C_A004447
1199 default 0x00 if ARCH_MPC8548
1200 default 0x10 if ARCH_P1010
1201 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1202 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1204 config SYS_FSL_ERRATUM_IFC_A002769
1207 config SYS_FSL_ERRATUM_IFC_A003399
1210 config SYS_FSL_ERRATUM_NMG_CPU_A011
1213 config SYS_FSL_ERRATUM_NMG_ETSEC129
1216 config SYS_FSL_ERRATUM_NMG_LBC103
1219 config SYS_FSL_ERRATUM_P1010_A003549
1222 config SYS_FSL_ERRATUM_SATA_A001
1225 config SYS_FSL_ERRATUM_SEC_A003571
1228 config SYS_FSL_ERRATUM_SRIO_A004034
1231 config SYS_FSL_ERRATUM_USB14
1234 config SYS_P4080_ERRATUM_CPU22
1237 config SYS_P4080_ERRATUM_PCIE_A003
1240 config SYS_P4080_ERRATUM_SERDES8
1243 config SYS_P4080_ERRATUM_SERDES9
1246 config SYS_P4080_ERRATUM_SERDES_A001
1249 config SYS_P4080_ERRATUM_SERDES_A005
1252 config SYS_FSL_QORIQ_CHASSIS1
1255 config SYS_FSL_QORIQ_CHASSIS2
1258 config SYS_FSL_NUM_LAWS
1259 int "Number of local access windows"
1261 default 32 if ARCH_B4420 || \
1272 default 16 if ARCH_T1023 || \
1276 default 12 if ARCH_BSC9131 || \
1290 default 10 if ARCH_MPC8544 || \
1294 default 8 if ARCH_MPC8540 || \
1299 Number of local access windows. This is fixed per SoC.
1300 If not sure, do not change.
1302 config SYS_FSL_THREADS_PER_CORE
1307 config SYS_NUM_TLBCAMS
1308 int "Number of TLB CAM entries"
1309 default 64 if E500MC
1312 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1313 16 for other E500 SoCs.
1318 config SYS_PPC_E500_USE_DEBUG_TLB
1327 config SYS_PPC_E500_DEBUG_TLB
1328 int "Temporary TLB entry for external debugger"
1329 depends on SYS_PPC_E500_USE_DEBUG_TLB
1330 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1331 default 1 if ARCH_MPC8536
1332 default 2 if ARCH_MPC8572 || \
1340 default 3 if ARCH_P1010 || \
1344 Select a temporary TLB entry to be used during boot to work
1345 around limitations in e500v1 and e500v2 external debugger
1346 support. This reduces the portions of the boot code where
1347 breakpoints and single stepping do not work. The value of this
1348 symbol should be set to the TLB1 entry to be used for this
1349 purpose. If unsure, do not change.
1351 config SYS_FSL_IFC_CLK_DIV
1352 int "Divider of platform clock"
1354 default 2 if ARCH_B4420 || \
1364 Defines divider of platform clock(clock input to
1367 config SYS_FSL_LBC_CLK_DIV
1368 int "Divider of platform clock"
1369 depends on FSL_ELBC || ARCH_MPC8540 || \
1370 ARCH_MPC8548 || ARCH_MPC8541 || \
1371 ARCH_MPC8555 || ARCH_MPC8560 || \
1374 default 2 if ARCH_P2041 || \
1382 Defines divider of platform clock(clock input to
1385 source "board/freescale/b4860qds/Kconfig"
1386 source "board/freescale/bsc9131rdb/Kconfig"
1387 source "board/freescale/bsc9132qds/Kconfig"
1388 source "board/freescale/c29xpcie/Kconfig"
1389 source "board/freescale/corenet_ds/Kconfig"
1390 source "board/freescale/mpc8536ds/Kconfig"
1391 source "board/freescale/mpc8541cds/Kconfig"
1392 source "board/freescale/mpc8544ds/Kconfig"
1393 source "board/freescale/mpc8548cds/Kconfig"
1394 source "board/freescale/mpc8555cds/Kconfig"
1395 source "board/freescale/mpc8568mds/Kconfig"
1396 source "board/freescale/mpc8569mds/Kconfig"
1397 source "board/freescale/mpc8572ds/Kconfig"
1398 source "board/freescale/p1010rdb/Kconfig"
1399 source "board/freescale/p1022ds/Kconfig"
1400 source "board/freescale/p1023rdb/Kconfig"
1401 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1402 source "board/freescale/p1_twr/Kconfig"
1403 source "board/freescale/p2041rdb/Kconfig"
1404 source "board/freescale/qemu-ppce500/Kconfig"
1405 source "board/freescale/t102xqds/Kconfig"
1406 source "board/freescale/t102xrdb/Kconfig"
1407 source "board/freescale/t1040qds/Kconfig"
1408 source "board/freescale/t104xrdb/Kconfig"
1409 source "board/freescale/t208xqds/Kconfig"
1410 source "board/freescale/t208xrdb/Kconfig"
1411 source "board/freescale/t4qds/Kconfig"
1412 source "board/freescale/t4rdb/Kconfig"
1413 source "board/gdsys/p1022/Kconfig"
1414 source "board/keymile/kmp204x/Kconfig"
1415 source "board/sbc8548/Kconfig"
1416 source "board/socrates/Kconfig"
1417 source "board/varisys/cyrus/Kconfig"
1418 source "board/xes/xpedite520x/Kconfig"
1419 source "board/xes/xpedite537x/Kconfig"
1420 source "board/xes/xpedite550x/Kconfig"
1421 source "board/Arcturus/ucp1020/Kconfig"