8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_B4420QDS
28 bool "Support B4420QDS"
33 config TARGET_B4860QDS
34 bool "Support B4860QDS"
36 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 config TARGET_BSC9131RDB
41 bool "Support BSC9131RDB"
44 select BOARD_EARLY_INIT_F
46 config TARGET_BSC9132QDS
47 bool "Support BSC9132QDS"
49 select BOARD_LATE_INIT if CHAIN_OF_TRUST
51 select BOARD_EARLY_INIT_F
53 config TARGET_C29XPCIE
54 bool "Support C29XPCIE"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
62 bool "Support P3041DS"
65 select BOARD_LATE_INIT if CHAIN_OF_TRUST
69 bool "Support P4080DS"
72 select BOARD_LATE_INIT if CHAIN_OF_TRUST
76 bool "Support P5020DS"
79 select BOARD_LATE_INIT if CHAIN_OF_TRUST
83 bool "Support P5040DS"
86 select BOARD_LATE_INIT if CHAIN_OF_TRUST
89 config TARGET_MPC8536DS
90 bool "Support MPC8536DS"
92 # Use DDR3 controller with DDR2 DIMMs on this board
93 select SYS_FSL_DDRC_GEN3
96 config TARGET_MPC8541CDS
97 bool "Support MPC8541CDS"
100 config TARGET_MPC8544DS
101 bool "Support MPC8544DS"
104 config TARGET_MPC8548CDS
105 bool "Support MPC8548CDS"
108 config TARGET_MPC8555CDS
109 bool "Support MPC8555CDS"
112 config TARGET_MPC8568MDS
113 bool "Support MPC8568MDS"
116 config TARGET_MPC8569MDS
117 bool "Support MPC8569MDS"
120 config TARGET_MPC8572DS
121 bool "Support MPC8572DS"
123 # Use DDR3 controller with DDR2 DIMMs on this board
124 select SYS_FSL_DDRC_GEN3
127 config TARGET_P1010RDB_PA
128 bool "Support P1010RDB_PA"
130 select BOARD_LATE_INIT if CHAIN_OF_TRUST
136 config TARGET_P1010RDB_PB
137 bool "Support P1010RDB_PB"
139 select BOARD_LATE_INIT if CHAIN_OF_TRUST
145 config TARGET_P1022DS
146 bool "Support P1022DS"
152 config TARGET_P1023RDB
153 bool "Support P1023RDB"
157 config TARGET_P1020MBG
158 bool "Support P1020MBG-PC"
165 config TARGET_P1020RDB_PC
166 bool "Support P1020RDB-PC"
173 config TARGET_P1020RDB_PD
174 bool "Support P1020RDB-PD"
181 config TARGET_P1020UTM
182 bool "Support P1020UTM"
189 config TARGET_P1021RDB
190 bool "Support P1021RDB"
197 config TARGET_P1024RDB
198 bool "Support P1024RDB"
205 config TARGET_P1025RDB
206 bool "Support P1025RDB"
213 config TARGET_P2020RDB
214 bool "Support P2020RDB-PC"
222 bool "Support p1_twr"
225 config TARGET_P2041RDB
226 bool "Support P2041RDB"
228 select BOARD_LATE_INIT if CHAIN_OF_TRUST
232 config TARGET_QEMU_PPCE500
233 bool "Support qemu-ppce500"
234 select ARCH_QEMU_E500
237 config TARGET_T1024QDS
238 bool "Support T1024QDS"
240 select BOARD_LATE_INIT if CHAIN_OF_TRUST
246 config TARGET_T1023RDB
247 bool "Support T1023RDB"
249 select BOARD_LATE_INIT if CHAIN_OF_TRUST
254 config TARGET_T1024RDB
255 bool "Support T1024RDB"
257 select BOARD_LATE_INIT if CHAIN_OF_TRUST
262 config TARGET_T1040QDS
263 bool "Support T1040QDS"
265 select BOARD_LATE_INIT if CHAIN_OF_TRUST
270 config TARGET_T1040RDB
271 bool "Support T1040RDB"
273 select BOARD_LATE_INIT if CHAIN_OF_TRUST
278 config TARGET_T1040D4RDB
279 bool "Support T1040D4RDB"
281 select BOARD_LATE_INIT if CHAIN_OF_TRUST
286 config TARGET_T1042RDB
287 bool "Support T1042RDB"
289 select BOARD_LATE_INIT if CHAIN_OF_TRUST
294 config TARGET_T1042D4RDB
295 bool "Support T1042D4RDB"
297 select BOARD_LATE_INIT if CHAIN_OF_TRUST
302 config TARGET_T1042RDB_PI
303 bool "Support T1042RDB_PI"
305 select BOARD_LATE_INIT if CHAIN_OF_TRUST
310 config TARGET_T2080QDS
311 bool "Support T2080QDS"
313 select BOARD_LATE_INIT if CHAIN_OF_TRUST
318 config TARGET_T2080RDB
319 bool "Support T2080RDB"
321 select BOARD_LATE_INIT if CHAIN_OF_TRUST
326 config TARGET_T2081QDS
327 bool "Support T2081QDS"
332 config TARGET_T4160QDS
333 bool "Support T4160QDS"
335 select BOARD_LATE_INIT if CHAIN_OF_TRUST
340 config TARGET_T4160RDB
341 bool "Support T4160RDB"
346 config TARGET_T4240QDS
347 bool "Support T4240QDS"
349 select BOARD_LATE_INIT if CHAIN_OF_TRUST
354 config TARGET_T4240RDB
355 bool "Support T4240RDB"
361 config TARGET_CONTROLCENTERD
362 bool "Support controlcenterd"
365 config TARGET_KMP204X
366 bool "Support kmp204x"
372 config TARGET_XPEDITE520X
373 bool "Support xpedite520x"
376 config TARGET_XPEDITE537X
377 bool "Support xpedite537x"
379 # Use DDR3 controller with DDR2 DIMMs on this board
380 select SYS_FSL_DDRC_GEN3
382 config TARGET_XPEDITE550X
383 bool "Support xpedite550x"
386 config TARGET_UCP1020
387 bool "Support uCP1020"
391 config TARGET_CYRUS_P5020
392 bool "Support Varisys Cyrus P5020"
396 config TARGET_CYRUS_P5040
397 bool "Support Varisys Cyrus P5040"
408 select SYS_FSL_DDR_VER_47
409 select SYS_FSL_ERRATUM_A004477
410 select SYS_FSL_ERRATUM_A005871
411 select SYS_FSL_ERRATUM_A006379
412 select SYS_FSL_ERRATUM_A006384
413 select SYS_FSL_ERRATUM_A006475
414 select SYS_FSL_ERRATUM_A006593
415 select SYS_FSL_ERRATUM_A007075
416 select SYS_FSL_ERRATUM_A007186
417 select SYS_FSL_ERRATUM_A007212
418 select SYS_FSL_ERRATUM_A009942
419 select SYS_FSL_HAS_DDR3
420 select SYS_FSL_HAS_SEC
421 select SYS_FSL_QORIQ_CHASSIS2
422 select SYS_FSL_SEC_BE
423 select SYS_FSL_SEC_COMPAT_4
435 select SYS_FSL_DDR_VER_47
436 select SYS_FSL_ERRATUM_A004477
437 select SYS_FSL_ERRATUM_A005871
438 select SYS_FSL_ERRATUM_A006379
439 select SYS_FSL_ERRATUM_A006384
440 select SYS_FSL_ERRATUM_A006475
441 select SYS_FSL_ERRATUM_A006593
442 select SYS_FSL_ERRATUM_A007075
443 select SYS_FSL_ERRATUM_A007186
444 select SYS_FSL_ERRATUM_A007212
445 select SYS_FSL_ERRATUM_A007907
446 select SYS_FSL_ERRATUM_A009942
447 select SYS_FSL_HAS_DDR3
448 select SYS_FSL_HAS_SEC
449 select SYS_FSL_QORIQ_CHASSIS2
450 select SYS_FSL_SEC_BE
451 select SYS_FSL_SEC_COMPAT_4
461 select SYS_FSL_DDR_VER_44
462 select SYS_FSL_ERRATUM_A004477
463 select SYS_FSL_ERRATUM_A005125
464 select SYS_FSL_ERRATUM_ESDHC111
465 select SYS_FSL_HAS_DDR3
466 select SYS_FSL_HAS_SEC
467 select SYS_FSL_SEC_BE
468 select SYS_FSL_SEC_COMPAT_4
477 select SYS_FSL_DDR_VER_46
478 select SYS_FSL_ERRATUM_A004477
479 select SYS_FSL_ERRATUM_A005125
480 select SYS_FSL_ERRATUM_A005434
481 select SYS_FSL_ERRATUM_ESDHC111
482 select SYS_FSL_ERRATUM_I2C_A004447
483 select SYS_FSL_ERRATUM_IFC_A002769
484 select SYS_FSL_HAS_DDR3
485 select SYS_FSL_HAS_SEC
486 select SYS_FSL_SEC_BE
487 select SYS_FSL_SEC_COMPAT_4
488 select SYS_PPC_E500_USE_DEBUG_TLB
499 select SYS_FSL_DDR_VER_46
500 select SYS_FSL_ERRATUM_A005125
501 select SYS_FSL_ERRATUM_ESDHC111
502 select SYS_FSL_HAS_DDR3
503 select SYS_FSL_HAS_SEC
504 select SYS_FSL_SEC_BE
505 select SYS_FSL_SEC_COMPAT_6
506 select SYS_PPC_E500_USE_DEBUG_TLB
515 select SYS_FSL_ERRATUM_A004508
516 select SYS_FSL_ERRATUM_A005125
517 select SYS_FSL_HAS_DDR2
518 select SYS_FSL_HAS_DDR3
519 select SYS_FSL_HAS_SEC
520 select SYS_FSL_SEC_BE
521 select SYS_FSL_SEC_COMPAT_2
522 select SYS_PPC_E500_USE_DEBUG_TLB
531 select SYS_FSL_HAS_DDR1
536 select SYS_FSL_HAS_DDR1
537 select SYS_FSL_HAS_SEC
538 select SYS_FSL_SEC_BE
539 select SYS_FSL_SEC_COMPAT_2
544 select SYS_FSL_ERRATUM_A005125
545 select SYS_FSL_HAS_DDR2
546 select SYS_FSL_HAS_SEC
547 select SYS_FSL_SEC_BE
548 select SYS_FSL_SEC_COMPAT_2
549 select SYS_PPC_E500_USE_DEBUG_TLB
555 select SYS_FSL_ERRATUM_A005125
556 select SYS_FSL_ERRATUM_NMG_DDR120
557 select SYS_FSL_ERRATUM_NMG_LBC103
558 select SYS_FSL_ERRATUM_NMG_ETSEC129
559 select SYS_FSL_ERRATUM_I2C_A004447
560 select SYS_FSL_HAS_DDR2
561 select SYS_FSL_HAS_DDR1
562 select SYS_FSL_HAS_SEC
563 select SYS_FSL_SEC_BE
564 select SYS_FSL_SEC_COMPAT_2
565 select SYS_PPC_E500_USE_DEBUG_TLB
571 select SYS_FSL_HAS_DDR1
572 select SYS_FSL_HAS_SEC
573 select SYS_FSL_SEC_BE
574 select SYS_FSL_SEC_COMPAT_2
579 select SYS_FSL_HAS_DDR1
584 select SYS_FSL_HAS_DDR2
585 select SYS_FSL_HAS_SEC
586 select SYS_FSL_SEC_BE
587 select SYS_FSL_SEC_COMPAT_2
592 select SYS_FSL_ERRATUM_A004508
593 select SYS_FSL_ERRATUM_A005125
594 select SYS_FSL_HAS_DDR3
595 select SYS_FSL_HAS_SEC
596 select SYS_FSL_SEC_BE
597 select SYS_FSL_SEC_COMPAT_2
604 select SYS_FSL_ERRATUM_A004508
605 select SYS_FSL_ERRATUM_A005125
606 select SYS_FSL_ERRATUM_DDR_115
607 select SYS_FSL_ERRATUM_DDR111_DDR134
608 select SYS_FSL_HAS_DDR2
609 select SYS_FSL_HAS_DDR3
610 select SYS_FSL_HAS_SEC
611 select SYS_FSL_SEC_BE
612 select SYS_FSL_SEC_COMPAT_2
613 select SYS_PPC_E500_USE_DEBUG_TLB
620 select SYS_FSL_ERRATUM_A004477
621 select SYS_FSL_ERRATUM_A004508
622 select SYS_FSL_ERRATUM_A005125
623 select SYS_FSL_ERRATUM_A006261
624 select SYS_FSL_ERRATUM_A007075
625 select SYS_FSL_ERRATUM_ESDHC111
626 select SYS_FSL_ERRATUM_I2C_A004447
627 select SYS_FSL_ERRATUM_IFC_A002769
628 select SYS_FSL_ERRATUM_P1010_A003549
629 select SYS_FSL_ERRATUM_SEC_A003571
630 select SYS_FSL_ERRATUM_IFC_A003399
631 select SYS_FSL_HAS_DDR3
632 select SYS_FSL_HAS_SEC
633 select SYS_FSL_SEC_BE
634 select SYS_FSL_SEC_COMPAT_4
635 select SYS_PPC_E500_USE_DEBUG_TLB
647 select SYS_FSL_ERRATUM_A004508
648 select SYS_FSL_ERRATUM_A005125
649 select SYS_FSL_ERRATUM_ELBC_A001
650 select SYS_FSL_ERRATUM_ESDHC111
651 select SYS_FSL_HAS_DDR3
652 select SYS_FSL_HAS_SEC
653 select SYS_FSL_SEC_BE
654 select SYS_FSL_SEC_COMPAT_2
655 select SYS_PPC_E500_USE_DEBUG_TLB
661 select SYS_FSL_ERRATUM_A004508
662 select SYS_FSL_ERRATUM_A005125
663 select SYS_FSL_ERRATUM_ELBC_A001
664 select SYS_FSL_ERRATUM_ESDHC111
665 select SYS_FSL_HAS_DDR3
666 select SYS_FSL_HAS_SEC
667 select SYS_FSL_SEC_BE
668 select SYS_FSL_SEC_COMPAT_2
669 select SYS_PPC_E500_USE_DEBUG_TLB
679 select SYS_FSL_ERRATUM_A004508
680 select SYS_FSL_ERRATUM_A005125
681 select SYS_FSL_ERRATUM_ELBC_A001
682 select SYS_FSL_ERRATUM_ESDHC111
683 select SYS_FSL_HAS_DDR3
684 select SYS_FSL_HAS_SEC
685 select SYS_FSL_SEC_BE
686 select SYS_FSL_SEC_COMPAT_2
687 select SYS_PPC_E500_USE_DEBUG_TLB
697 select SYS_FSL_ERRATUM_A004477
698 select SYS_FSL_ERRATUM_A004508
699 select SYS_FSL_ERRATUM_A005125
700 select SYS_FSL_ERRATUM_ELBC_A001
701 select SYS_FSL_ERRATUM_ESDHC111
702 select SYS_FSL_ERRATUM_SATA_A001
703 select SYS_FSL_HAS_DDR3
704 select SYS_FSL_HAS_SEC
705 select SYS_FSL_SEC_BE
706 select SYS_FSL_SEC_COMPAT_2
707 select SYS_PPC_E500_USE_DEBUG_TLB
713 select SYS_FSL_ERRATUM_A004508
714 select SYS_FSL_ERRATUM_A005125
715 select SYS_FSL_ERRATUM_I2C_A004447
716 select SYS_FSL_HAS_DDR3
717 select SYS_FSL_HAS_SEC
718 select SYS_FSL_SEC_BE
719 select SYS_FSL_SEC_COMPAT_4
725 select SYS_FSL_ERRATUM_A004508
726 select SYS_FSL_ERRATUM_A005125
727 select SYS_FSL_ERRATUM_ELBC_A001
728 select SYS_FSL_ERRATUM_ESDHC111
729 select SYS_FSL_HAS_DDR3
730 select SYS_FSL_HAS_SEC
731 select SYS_FSL_SEC_BE
732 select SYS_FSL_SEC_COMPAT_2
733 select SYS_PPC_E500_USE_DEBUG_TLB
744 select SYS_FSL_ERRATUM_A004508
745 select SYS_FSL_ERRATUM_A005125
746 select SYS_FSL_ERRATUM_ELBC_A001
747 select SYS_FSL_ERRATUM_ESDHC111
748 select SYS_FSL_HAS_DDR3
749 select SYS_FSL_HAS_SEC
750 select SYS_FSL_SEC_BE
751 select SYS_FSL_SEC_COMPAT_2
752 select SYS_PPC_E500_USE_DEBUG_TLB
760 select SYS_FSL_ERRATUM_A004477
761 select SYS_FSL_ERRATUM_A004508
762 select SYS_FSL_ERRATUM_A005125
763 select SYS_FSL_ERRATUM_ESDHC111
764 select SYS_FSL_ERRATUM_ESDHC_A001
765 select SYS_FSL_HAS_DDR3
766 select SYS_FSL_HAS_SEC
767 select SYS_FSL_SEC_BE
768 select SYS_FSL_SEC_COMPAT_2
769 select SYS_PPC_E500_USE_DEBUG_TLB
779 select SYS_FSL_ERRATUM_A004510
780 select SYS_FSL_ERRATUM_A004849
781 select SYS_FSL_ERRATUM_A006261
782 select SYS_FSL_ERRATUM_CPU_A003999
783 select SYS_FSL_ERRATUM_DDR_A003
784 select SYS_FSL_ERRATUM_DDR_A003474
785 select SYS_FSL_ERRATUM_ESDHC111
786 select SYS_FSL_ERRATUM_I2C_A004447
787 select SYS_FSL_ERRATUM_NMG_CPU_A011
788 select SYS_FSL_ERRATUM_SRIO_A004034
789 select SYS_FSL_ERRATUM_USB14
790 select SYS_FSL_HAS_DDR3
791 select SYS_FSL_HAS_SEC
792 select SYS_FSL_QORIQ_CHASSIS1
793 select SYS_FSL_SEC_BE
794 select SYS_FSL_SEC_COMPAT_4
802 select SYS_FSL_DDR_VER_44
803 select SYS_FSL_ERRATUM_A004510
804 select SYS_FSL_ERRATUM_A004849
805 select SYS_FSL_ERRATUM_A005812
806 select SYS_FSL_ERRATUM_A006261
807 select SYS_FSL_ERRATUM_CPU_A003999
808 select SYS_FSL_ERRATUM_DDR_A003
809 select SYS_FSL_ERRATUM_DDR_A003474
810 select SYS_FSL_ERRATUM_ESDHC111
811 select SYS_FSL_ERRATUM_I2C_A004447
812 select SYS_FSL_ERRATUM_NMG_CPU_A011
813 select SYS_FSL_ERRATUM_SRIO_A004034
814 select SYS_FSL_ERRATUM_USB14
815 select SYS_FSL_HAS_DDR3
816 select SYS_FSL_HAS_SEC
817 select SYS_FSL_QORIQ_CHASSIS1
818 select SYS_FSL_SEC_BE
819 select SYS_FSL_SEC_COMPAT_4
829 select SYS_FSL_DDR_VER_44
830 select SYS_FSL_ERRATUM_A004510
831 select SYS_FSL_ERRATUM_A004580
832 select SYS_FSL_ERRATUM_A004849
833 select SYS_FSL_ERRATUM_A005812
834 select SYS_FSL_ERRATUM_A007075
835 select SYS_FSL_ERRATUM_CPC_A002
836 select SYS_FSL_ERRATUM_CPC_A003
837 select SYS_FSL_ERRATUM_CPU_A003999
838 select SYS_FSL_ERRATUM_DDR_A003
839 select SYS_FSL_ERRATUM_DDR_A003474
840 select SYS_FSL_ERRATUM_ELBC_A001
841 select SYS_FSL_ERRATUM_ESDHC111
842 select SYS_FSL_ERRATUM_ESDHC13
843 select SYS_FSL_ERRATUM_ESDHC135
844 select SYS_FSL_ERRATUM_I2C_A004447
845 select SYS_FSL_ERRATUM_NMG_CPU_A011
846 select SYS_FSL_ERRATUM_SRIO_A004034
847 select SYS_P4080_ERRATUM_CPU22
848 select SYS_P4080_ERRATUM_PCIE_A003
849 select SYS_P4080_ERRATUM_SERDES8
850 select SYS_P4080_ERRATUM_SERDES9
851 select SYS_P4080_ERRATUM_SERDES_A001
852 select SYS_P4080_ERRATUM_SERDES_A005
853 select SYS_FSL_HAS_DDR3
854 select SYS_FSL_HAS_SEC
855 select SYS_FSL_QORIQ_CHASSIS1
856 select SYS_FSL_SEC_BE
857 select SYS_FSL_SEC_COMPAT_4
866 select SYS_FSL_DDR_VER_44
867 select SYS_FSL_ERRATUM_A004510
868 select SYS_FSL_ERRATUM_A006261
869 select SYS_FSL_ERRATUM_DDR_A003
870 select SYS_FSL_ERRATUM_DDR_A003474
871 select SYS_FSL_ERRATUM_ESDHC111
872 select SYS_FSL_ERRATUM_I2C_A004447
873 select SYS_FSL_ERRATUM_SRIO_A004034
874 select SYS_FSL_ERRATUM_USB14
875 select SYS_FSL_HAS_DDR3
876 select SYS_FSL_HAS_SEC
877 select SYS_FSL_QORIQ_CHASSIS1
878 select SYS_FSL_SEC_BE
879 select SYS_FSL_SEC_COMPAT_4
889 select SYS_FSL_DDR_VER_44
890 select SYS_FSL_ERRATUM_A004510
891 select SYS_FSL_ERRATUM_A004699
892 select SYS_FSL_ERRATUM_A005812
893 select SYS_FSL_ERRATUM_A006261
894 select SYS_FSL_ERRATUM_DDR_A003
895 select SYS_FSL_ERRATUM_DDR_A003474
896 select SYS_FSL_ERRATUM_ESDHC111
897 select SYS_FSL_ERRATUM_USB14
898 select SYS_FSL_HAS_DDR3
899 select SYS_FSL_HAS_SEC
900 select SYS_FSL_QORIQ_CHASSIS1
901 select SYS_FSL_SEC_BE
902 select SYS_FSL_SEC_COMPAT_4
908 config ARCH_QEMU_E500
915 select SYS_FSL_DDR_VER_50
916 select SYS_FSL_ERRATUM_A008378
917 select SYS_FSL_ERRATUM_A009663
918 select SYS_FSL_ERRATUM_A009942
919 select SYS_FSL_ERRATUM_ESDHC111
920 select SYS_FSL_HAS_DDR3
921 select SYS_FSL_HAS_DDR4
922 select SYS_FSL_HAS_SEC
923 select SYS_FSL_QORIQ_CHASSIS2
924 select SYS_FSL_SEC_BE
925 select SYS_FSL_SEC_COMPAT_5
935 select SYS_FSL_DDR_VER_50
936 select SYS_FSL_ERRATUM_A008378
937 select SYS_FSL_ERRATUM_A009663
938 select SYS_FSL_ERRATUM_A009942
939 select SYS_FSL_ERRATUM_ESDHC111
940 select SYS_FSL_HAS_DDR3
941 select SYS_FSL_HAS_DDR4
942 select SYS_FSL_HAS_SEC
943 select SYS_FSL_QORIQ_CHASSIS2
944 select SYS_FSL_SEC_BE
945 select SYS_FSL_SEC_COMPAT_5
956 select SYS_FSL_DDR_VER_50
957 select SYS_FSL_ERRATUM_A008044
958 select SYS_FSL_ERRATUM_A008378
959 select SYS_FSL_ERRATUM_A009663
960 select SYS_FSL_ERRATUM_A009942
961 select SYS_FSL_ERRATUM_ESDHC111
962 select SYS_FSL_HAS_DDR3
963 select SYS_FSL_HAS_DDR4
964 select SYS_FSL_HAS_SEC
965 select SYS_FSL_QORIQ_CHASSIS2
966 select SYS_FSL_SEC_BE
967 select SYS_FSL_SEC_COMPAT_5
978 select SYS_FSL_DDR_VER_50
979 select SYS_FSL_ERRATUM_A008044
980 select SYS_FSL_ERRATUM_A008378
981 select SYS_FSL_ERRATUM_A009663
982 select SYS_FSL_ERRATUM_A009942
983 select SYS_FSL_ERRATUM_ESDHC111
984 select SYS_FSL_HAS_DDR3
985 select SYS_FSL_HAS_DDR4
986 select SYS_FSL_HAS_SEC
987 select SYS_FSL_QORIQ_CHASSIS2
988 select SYS_FSL_SEC_BE
989 select SYS_FSL_SEC_COMPAT_5
1001 select SYS_FSL_DDR_VER_47
1002 select SYS_FSL_ERRATUM_A006379
1003 select SYS_FSL_ERRATUM_A006593
1004 select SYS_FSL_ERRATUM_A007186
1005 select SYS_FSL_ERRATUM_A007212
1006 select SYS_FSL_ERRATUM_A007815
1007 select SYS_FSL_ERRATUM_A007907
1008 select SYS_FSL_ERRATUM_A009942
1009 select SYS_FSL_ERRATUM_ESDHC111
1010 select SYS_FSL_HAS_DDR3
1011 select SYS_FSL_HAS_SEC
1012 select SYS_FSL_QORIQ_CHASSIS2
1013 select SYS_FSL_SEC_BE
1014 select SYS_FSL_SEC_COMPAT_4
1026 select SYS_FSL_DDR_VER_47
1027 select SYS_FSL_ERRATUM_A006379
1028 select SYS_FSL_ERRATUM_A006593
1029 select SYS_FSL_ERRATUM_A007186
1030 select SYS_FSL_ERRATUM_A007212
1031 select SYS_FSL_ERRATUM_A009942
1032 select SYS_FSL_ERRATUM_ESDHC111
1033 select SYS_FSL_HAS_DDR3
1034 select SYS_FSL_HAS_SEC
1035 select SYS_FSL_QORIQ_CHASSIS2
1036 select SYS_FSL_SEC_BE
1037 select SYS_FSL_SEC_COMPAT_4
1048 select SYS_FSL_DDR_VER_47
1049 select SYS_FSL_ERRATUM_A004468
1050 select SYS_FSL_ERRATUM_A005871
1051 select SYS_FSL_ERRATUM_A006379
1052 select SYS_FSL_ERRATUM_A006593
1053 select SYS_FSL_ERRATUM_A007186
1054 select SYS_FSL_ERRATUM_A007798
1055 select SYS_FSL_ERRATUM_A009942
1056 select SYS_FSL_HAS_DDR3
1057 select SYS_FSL_HAS_SEC
1058 select SYS_FSL_QORIQ_CHASSIS2
1059 select SYS_FSL_SEC_BE
1060 select SYS_FSL_SEC_COMPAT_4
1072 select SYS_FSL_DDR_VER_47
1073 select SYS_FSL_ERRATUM_A004468
1074 select SYS_FSL_ERRATUM_A005871
1075 select SYS_FSL_ERRATUM_A006261
1076 select SYS_FSL_ERRATUM_A006379
1077 select SYS_FSL_ERRATUM_A006593
1078 select SYS_FSL_ERRATUM_A007186
1079 select SYS_FSL_ERRATUM_A007798
1080 select SYS_FSL_ERRATUM_A007815
1081 select SYS_FSL_ERRATUM_A007907
1082 select SYS_FSL_ERRATUM_A009942
1083 select SYS_FSL_HAS_DDR3
1084 select SYS_FSL_HAS_SEC
1085 select SYS_FSL_QORIQ_CHASSIS2
1086 select SYS_FSL_SEC_BE
1087 select SYS_FSL_SEC_COMPAT_4
1102 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1108 Enble PowerPC E500MC core
1113 Enable PowerPC E6500 core
1118 Use Freescale common code for Local Access Window
1123 Enable Freescale Secure Boot feature. Normally selected
1124 by defconfig. If unsure, do not change.
1127 int "Maximum number of CPUs permitted for MPC85xx"
1128 default 12 if ARCH_T4240
1129 default 8 if ARCH_P4080 || \
1131 default 4 if ARCH_B4860 || \
1139 default 2 if ARCH_B4420 || \
1154 Set this number to the maximum number of possible CPUs in the SoC.
1155 SoCs may have multiple clusters with each cluster may have multiple
1156 ports. If some ports are reserved but higher ports are used for
1157 cores, count the reserved ports. This will allocate enough memory
1158 in spin table to properly handle all cores.
1160 config SYS_CCSRBAR_DEFAULT
1161 hex "Default CCSRBAR address"
1162 default 0xff700000 if ARCH_BSC9131 || \
1183 default 0xff600000 if ARCH_P1023
1184 default 0xfe000000 if ARCH_B4420 || \
1199 default 0xe0000000 if ARCH_QEMU_E500
1201 Default value of CCSRBAR comes from power-on-reset. It
1202 is fixed on each SoC. Some SoCs can have different value
1203 if changed by pre-boot regime. The value here must match
1204 the current value in SoC. If not sure, do not change.
1206 config SYS_FSL_ERRATUM_A004468
1209 config SYS_FSL_ERRATUM_A004477
1212 config SYS_FSL_ERRATUM_A004508
1215 config SYS_FSL_ERRATUM_A004580
1218 config SYS_FSL_ERRATUM_A004699
1221 config SYS_FSL_ERRATUM_A004849
1224 config SYS_FSL_ERRATUM_A004510
1227 config SYS_FSL_ERRATUM_A004510_SVR_REV
1229 depends on SYS_FSL_ERRATUM_A004510
1230 default 0x20 if ARCH_P4080
1233 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1235 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1238 config SYS_FSL_ERRATUM_A005125
1241 config SYS_FSL_ERRATUM_A005434
1244 config SYS_FSL_ERRATUM_A005812
1247 config SYS_FSL_ERRATUM_A005871
1250 config SYS_FSL_ERRATUM_A006261
1253 config SYS_FSL_ERRATUM_A006379
1256 config SYS_FSL_ERRATUM_A006384
1259 config SYS_FSL_ERRATUM_A006475
1262 config SYS_FSL_ERRATUM_A006593
1265 config SYS_FSL_ERRATUM_A007075
1268 config SYS_FSL_ERRATUM_A007186
1271 config SYS_FSL_ERRATUM_A007212
1274 config SYS_FSL_ERRATUM_A007815
1277 config SYS_FSL_ERRATUM_A007798
1280 config SYS_FSL_ERRATUM_A007907
1283 config SYS_FSL_ERRATUM_A008044
1286 config SYS_FSL_ERRATUM_CPC_A002
1289 config SYS_FSL_ERRATUM_CPC_A003
1292 config SYS_FSL_ERRATUM_CPU_A003999
1295 config SYS_FSL_ERRATUM_ELBC_A001
1298 config SYS_FSL_ERRATUM_I2C_A004447
1301 config SYS_FSL_A004447_SVR_REV
1303 depends on SYS_FSL_ERRATUM_I2C_A004447
1304 default 0x00 if ARCH_MPC8548
1305 default 0x10 if ARCH_P1010
1306 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1307 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1309 config SYS_FSL_ERRATUM_IFC_A002769
1312 config SYS_FSL_ERRATUM_IFC_A003399
1315 config SYS_FSL_ERRATUM_NMG_CPU_A011
1318 config SYS_FSL_ERRATUM_NMG_ETSEC129
1321 config SYS_FSL_ERRATUM_NMG_LBC103
1324 config SYS_FSL_ERRATUM_P1010_A003549
1327 config SYS_FSL_ERRATUM_SATA_A001
1330 config SYS_FSL_ERRATUM_SEC_A003571
1333 config SYS_FSL_ERRATUM_SRIO_A004034
1336 config SYS_FSL_ERRATUM_USB14
1339 config SYS_P4080_ERRATUM_CPU22
1342 config SYS_P4080_ERRATUM_PCIE_A003
1345 config SYS_P4080_ERRATUM_SERDES8
1348 config SYS_P4080_ERRATUM_SERDES9
1351 config SYS_P4080_ERRATUM_SERDES_A001
1354 config SYS_P4080_ERRATUM_SERDES_A005
1357 config SYS_FSL_QORIQ_CHASSIS1
1360 config SYS_FSL_QORIQ_CHASSIS2
1363 config SYS_FSL_NUM_LAWS
1364 int "Number of local access windows"
1366 default 32 if ARCH_B4420 || \
1377 default 16 if ARCH_T1023 || \
1381 default 12 if ARCH_BSC9131 || \
1395 default 10 if ARCH_MPC8544 || \
1399 default 8 if ARCH_MPC8540 || \
1404 Number of local access windows. This is fixed per SoC.
1405 If not sure, do not change.
1407 config SYS_FSL_THREADS_PER_CORE
1412 config SYS_NUM_TLBCAMS
1413 int "Number of TLB CAM entries"
1414 default 64 if E500MC
1417 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1418 16 for other E500 SoCs.
1423 config SYS_PPC_E500_USE_DEBUG_TLB
1432 config SYS_PPC_E500_DEBUG_TLB
1433 int "Temporary TLB entry for external debugger"
1434 depends on SYS_PPC_E500_USE_DEBUG_TLB
1435 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1436 default 1 if ARCH_MPC8536
1437 default 2 if ARCH_MPC8572 || \
1445 default 3 if ARCH_P1010 || \
1449 Select a temporary TLB entry to be used during boot to work
1450 around limitations in e500v1 and e500v2 external debugger
1451 support. This reduces the portions of the boot code where
1452 breakpoints and single stepping do not work. The value of this
1453 symbol should be set to the TLB1 entry to be used for this
1454 purpose. If unsure, do not change.
1456 config SYS_FSL_IFC_CLK_DIV
1457 int "Divider of platform clock"
1459 default 2 if ARCH_B4420 || \
1469 Defines divider of platform clock(clock input to
1472 config SYS_FSL_LBC_CLK_DIV
1473 int "Divider of platform clock"
1474 depends on FSL_ELBC || ARCH_MPC8540 || \
1475 ARCH_MPC8548 || ARCH_MPC8541 || \
1476 ARCH_MPC8555 || ARCH_MPC8560 || \
1479 default 2 if ARCH_P2041 || \
1487 Defines divider of platform clock(clock input to
1490 source "board/freescale/b4860qds/Kconfig"
1491 source "board/freescale/bsc9131rdb/Kconfig"
1492 source "board/freescale/bsc9132qds/Kconfig"
1493 source "board/freescale/c29xpcie/Kconfig"
1494 source "board/freescale/corenet_ds/Kconfig"
1495 source "board/freescale/mpc8536ds/Kconfig"
1496 source "board/freescale/mpc8541cds/Kconfig"
1497 source "board/freescale/mpc8544ds/Kconfig"
1498 source "board/freescale/mpc8548cds/Kconfig"
1499 source "board/freescale/mpc8555cds/Kconfig"
1500 source "board/freescale/mpc8568mds/Kconfig"
1501 source "board/freescale/mpc8569mds/Kconfig"
1502 source "board/freescale/mpc8572ds/Kconfig"
1503 source "board/freescale/p1010rdb/Kconfig"
1504 source "board/freescale/p1022ds/Kconfig"
1505 source "board/freescale/p1023rdb/Kconfig"
1506 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1507 source "board/freescale/p1_twr/Kconfig"
1508 source "board/freescale/p2041rdb/Kconfig"
1509 source "board/freescale/qemu-ppce500/Kconfig"
1510 source "board/freescale/t102xqds/Kconfig"
1511 source "board/freescale/t102xrdb/Kconfig"
1512 source "board/freescale/t1040qds/Kconfig"
1513 source "board/freescale/t104xrdb/Kconfig"
1514 source "board/freescale/t208xqds/Kconfig"
1515 source "board/freescale/t208xrdb/Kconfig"
1516 source "board/freescale/t4qds/Kconfig"
1517 source "board/freescale/t4rdb/Kconfig"
1518 source "board/gdsys/p1022/Kconfig"
1519 source "board/keymile/kmp204x/Kconfig"
1520 source "board/sbc8548/Kconfig"
1521 source "board/socrates/Kconfig"
1522 source "board/varisys/cyrus/Kconfig"
1523 source "board/xes/xpedite520x/Kconfig"
1524 source "board/xes/xpedite537x/Kconfig"
1525 source "board/xes/xpedite550x/Kconfig"
1526 source "board/Arcturus/ucp1020/Kconfig"