8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_B4420QDS
28 bool "Support B4420QDS"
33 config TARGET_B4860QDS
34 bool "Support B4860QDS"
36 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 config TARGET_BSC9131RDB
41 bool "Support BSC9131RDB"
44 select BOARD_EARLY_INIT_F
46 config TARGET_BSC9132QDS
47 bool "Support BSC9132QDS"
49 select BOARD_LATE_INIT if CHAIN_OF_TRUST
51 select BOARD_EARLY_INIT_F
53 config TARGET_C29XPCIE
54 bool "Support C29XPCIE"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
62 bool "Support P3041DS"
65 select BOARD_LATE_INIT if CHAIN_OF_TRUST
68 bool "Support P4080DS"
71 select BOARD_LATE_INIT if CHAIN_OF_TRUST
74 bool "Support P5020DS"
77 select BOARD_LATE_INIT if CHAIN_OF_TRUST
80 bool "Support P5040DS"
83 select BOARD_LATE_INIT if CHAIN_OF_TRUST
85 config TARGET_MPC8536DS
86 bool "Support MPC8536DS"
88 # Use DDR3 controller with DDR2 DIMMs on this board
89 select SYS_FSL_DDRC_GEN3
91 config TARGET_MPC8540ADS
92 bool "Support MPC8540ADS"
95 config TARGET_MPC8541CDS
96 bool "Support MPC8541CDS"
99 config TARGET_MPC8544DS
100 bool "Support MPC8544DS"
103 config TARGET_MPC8548CDS
104 bool "Support MPC8548CDS"
107 config TARGET_MPC8555CDS
108 bool "Support MPC8555CDS"
111 config TARGET_MPC8560ADS
112 bool "Support MPC8560ADS"
115 config TARGET_MPC8568MDS
116 bool "Support MPC8568MDS"
119 config TARGET_MPC8569MDS
120 bool "Support MPC8569MDS"
123 config TARGET_MPC8572DS
124 bool "Support MPC8572DS"
126 # Use DDR3 controller with DDR2 DIMMs on this board
127 select SYS_FSL_DDRC_GEN3
129 config TARGET_P1010RDB_PA
130 bool "Support P1010RDB_PA"
132 select BOARD_LATE_INIT if CHAIN_OF_TRUST
137 config TARGET_P1010RDB_PB
138 bool "Support P1010RDB_PB"
140 select BOARD_LATE_INIT if CHAIN_OF_TRUST
145 config TARGET_P1022DS
146 bool "Support P1022DS"
151 config TARGET_P1023RDB
152 bool "Support P1023RDB"
156 config TARGET_P1020MBG
157 bool "Support P1020MBG-PC"
163 config TARGET_P1020RDB_PC
164 bool "Support P1020RDB-PC"
170 config TARGET_P1020RDB_PD
171 bool "Support P1020RDB-PD"
177 config TARGET_P1020UTM
178 bool "Support P1020UTM"
184 config TARGET_P1021RDB
185 bool "Support P1021RDB"
191 config TARGET_P1024RDB
192 bool "Support P1024RDB"
198 config TARGET_P1025RDB
199 bool "Support P1025RDB"
205 config TARGET_P2020RDB
206 bool "Support P2020RDB-PC"
213 bool "Support p1_twr"
216 config TARGET_P2041RDB
217 bool "Support P2041RDB"
219 select BOARD_LATE_INIT if CHAIN_OF_TRUST
222 config TARGET_QEMU_PPCE500
223 bool "Support qemu-ppce500"
224 select ARCH_QEMU_E500
227 config TARGET_T1024QDS
228 bool "Support T1024QDS"
230 select BOARD_LATE_INIT if CHAIN_OF_TRUST
235 config TARGET_T1023RDB
236 bool "Support T1023RDB"
238 select BOARD_LATE_INIT if CHAIN_OF_TRUST
243 config TARGET_T1024RDB
244 bool "Support T1024RDB"
246 select BOARD_LATE_INIT if CHAIN_OF_TRUST
251 config TARGET_T1040QDS
252 bool "Support T1040QDS"
254 select BOARD_LATE_INIT if CHAIN_OF_TRUST
258 config TARGET_T1040RDB
259 bool "Support T1040RDB"
261 select BOARD_LATE_INIT if CHAIN_OF_TRUST
265 config TARGET_T1040D4RDB
266 bool "Support T1040D4RDB"
268 select BOARD_LATE_INIT if CHAIN_OF_TRUST
272 config TARGET_T1042RDB
273 bool "Support T1042RDB"
275 select BOARD_LATE_INIT if CHAIN_OF_TRUST
279 config TARGET_T1042D4RDB
280 bool "Support T1042D4RDB"
282 select BOARD_LATE_INIT if CHAIN_OF_TRUST
286 config TARGET_T1042RDB_PI
287 bool "Support T1042RDB_PI"
289 select BOARD_LATE_INIT if CHAIN_OF_TRUST
293 config TARGET_T2080QDS
294 bool "Support T2080QDS"
296 select BOARD_LATE_INIT if CHAIN_OF_TRUST
300 config TARGET_T2080RDB
301 bool "Support T2080RDB"
303 select BOARD_LATE_INIT if CHAIN_OF_TRUST
307 config TARGET_T2081QDS
308 bool "Support T2081QDS"
313 config TARGET_T4160QDS
314 bool "Support T4160QDS"
316 select BOARD_LATE_INIT if CHAIN_OF_TRUST
320 config TARGET_T4160RDB
321 bool "Support T4160RDB"
326 config TARGET_T4240QDS
327 bool "Support T4240QDS"
329 select BOARD_LATE_INIT if CHAIN_OF_TRUST
333 config TARGET_T4240RDB
334 bool "Support T4240RDB"
339 config TARGET_CONTROLCENTERD
340 bool "Support controlcenterd"
343 config TARGET_KMP204X
344 bool "Support kmp204x"
350 config TARGET_XPEDITE520X
351 bool "Support xpedite520x"
354 config TARGET_XPEDITE537X
355 bool "Support xpedite537x"
357 # Use DDR3 controller with DDR2 DIMMs on this board
358 select SYS_FSL_DDRC_GEN3
360 config TARGET_XPEDITE550X
361 bool "Support xpedite550x"
364 config TARGET_UCP1020
365 bool "Support uCP1020"
368 config TARGET_CYRUS_P5020
369 bool "Support Varisys Cyrus P5020"
373 config TARGET_CYRUS_P5040
374 bool "Support Varisys Cyrus P5040"
385 select SYS_FSL_DDR_VER_47
386 select SYS_FSL_ERRATUM_A004477
387 select SYS_FSL_ERRATUM_A005871
388 select SYS_FSL_ERRATUM_A006379
389 select SYS_FSL_ERRATUM_A006384
390 select SYS_FSL_ERRATUM_A006475
391 select SYS_FSL_ERRATUM_A006593
392 select SYS_FSL_ERRATUM_A007075
393 select SYS_FSL_ERRATUM_A007186
394 select SYS_FSL_ERRATUM_A007212
395 select SYS_FSL_ERRATUM_A009942
396 select SYS_FSL_HAS_DDR3
397 select SYS_FSL_HAS_SEC
398 select SYS_FSL_QORIQ_CHASSIS2
399 select SYS_FSL_SEC_BE
400 select SYS_FSL_SEC_COMPAT_4
410 select SYS_FSL_DDR_VER_47
411 select SYS_FSL_ERRATUM_A004477
412 select SYS_FSL_ERRATUM_A005871
413 select SYS_FSL_ERRATUM_A006379
414 select SYS_FSL_ERRATUM_A006384
415 select SYS_FSL_ERRATUM_A006475
416 select SYS_FSL_ERRATUM_A006593
417 select SYS_FSL_ERRATUM_A007075
418 select SYS_FSL_ERRATUM_A007186
419 select SYS_FSL_ERRATUM_A007212
420 select SYS_FSL_ERRATUM_A007907
421 select SYS_FSL_ERRATUM_A009942
422 select SYS_FSL_HAS_DDR3
423 select SYS_FSL_HAS_SEC
424 select SYS_FSL_QORIQ_CHASSIS2
425 select SYS_FSL_SEC_BE
426 select SYS_FSL_SEC_COMPAT_4
434 select SYS_FSL_DDR_VER_44
435 select SYS_FSL_ERRATUM_A004477
436 select SYS_FSL_ERRATUM_A005125
437 select SYS_FSL_ERRATUM_ESDHC111
438 select SYS_FSL_HAS_DDR3
439 select SYS_FSL_HAS_SEC
440 select SYS_FSL_SEC_BE
441 select SYS_FSL_SEC_COMPAT_4
448 select SYS_FSL_DDR_VER_46
449 select SYS_FSL_ERRATUM_A004477
450 select SYS_FSL_ERRATUM_A005125
451 select SYS_FSL_ERRATUM_A005434
452 select SYS_FSL_ERRATUM_ESDHC111
453 select SYS_FSL_ERRATUM_I2C_A004447
454 select SYS_FSL_ERRATUM_IFC_A002769
455 select SYS_FSL_HAS_DDR3
456 select SYS_FSL_HAS_SEC
457 select SYS_FSL_SEC_BE
458 select SYS_FSL_SEC_COMPAT_4
459 select SYS_PPC_E500_USE_DEBUG_TLB
466 select SYS_FSL_DDR_VER_46
467 select SYS_FSL_ERRATUM_A005125
468 select SYS_FSL_ERRATUM_ESDHC111
469 select SYS_FSL_HAS_DDR3
470 select SYS_FSL_HAS_SEC
471 select SYS_FSL_SEC_BE
472 select SYS_FSL_SEC_COMPAT_6
473 select SYS_PPC_E500_USE_DEBUG_TLB
479 select SYS_FSL_ERRATUM_A004508
480 select SYS_FSL_ERRATUM_A005125
481 select SYS_FSL_HAS_DDR2
482 select SYS_FSL_HAS_DDR3
483 select SYS_FSL_HAS_SEC
484 select SYS_FSL_SEC_BE
485 select SYS_FSL_SEC_COMPAT_2
486 select SYS_PPC_E500_USE_DEBUG_TLB
492 select SYS_FSL_HAS_DDR1
497 select SYS_FSL_HAS_DDR1
498 select SYS_FSL_HAS_SEC
499 select SYS_FSL_SEC_BE
500 select SYS_FSL_SEC_COMPAT_2
505 select SYS_FSL_ERRATUM_A005125
506 select SYS_FSL_HAS_DDR2
507 select SYS_FSL_HAS_SEC
508 select SYS_FSL_SEC_BE
509 select SYS_FSL_SEC_COMPAT_2
510 select SYS_PPC_E500_USE_DEBUG_TLB
516 select SYS_FSL_ERRATUM_A005125
517 select SYS_FSL_ERRATUM_NMG_DDR120
518 select SYS_FSL_ERRATUM_NMG_LBC103
519 select SYS_FSL_ERRATUM_NMG_ETSEC129
520 select SYS_FSL_ERRATUM_I2C_A004447
521 select SYS_FSL_HAS_DDR2
522 select SYS_FSL_HAS_DDR1
523 select SYS_FSL_HAS_SEC
524 select SYS_FSL_SEC_BE
525 select SYS_FSL_SEC_COMPAT_2
526 select SYS_PPC_E500_USE_DEBUG_TLB
531 select SYS_FSL_HAS_DDR1
532 select SYS_FSL_HAS_SEC
533 select SYS_FSL_SEC_BE
534 select SYS_FSL_SEC_COMPAT_2
539 select SYS_FSL_HAS_DDR1
544 select SYS_FSL_HAS_DDR2
545 select SYS_FSL_HAS_SEC
546 select SYS_FSL_SEC_BE
547 select SYS_FSL_SEC_COMPAT_2
552 select SYS_FSL_ERRATUM_A004508
553 select SYS_FSL_ERRATUM_A005125
554 select SYS_FSL_HAS_DDR3
555 select SYS_FSL_HAS_SEC
556 select SYS_FSL_SEC_BE
557 select SYS_FSL_SEC_COMPAT_2
563 select SYS_FSL_ERRATUM_A004508
564 select SYS_FSL_ERRATUM_A005125
565 select SYS_FSL_ERRATUM_DDR_115
566 select SYS_FSL_ERRATUM_DDR111_DDR134
567 select SYS_FSL_HAS_DDR2
568 select SYS_FSL_HAS_DDR3
569 select SYS_FSL_HAS_SEC
570 select SYS_FSL_SEC_BE
571 select SYS_FSL_SEC_COMPAT_2
572 select SYS_PPC_E500_USE_DEBUG_TLB
578 select SYS_FSL_ERRATUM_A004477
579 select SYS_FSL_ERRATUM_A004508
580 select SYS_FSL_ERRATUM_A005125
581 select SYS_FSL_ERRATUM_A006261
582 select SYS_FSL_ERRATUM_A007075
583 select SYS_FSL_ERRATUM_ESDHC111
584 select SYS_FSL_ERRATUM_I2C_A004447
585 select SYS_FSL_ERRATUM_IFC_A002769
586 select SYS_FSL_ERRATUM_P1010_A003549
587 select SYS_FSL_ERRATUM_SEC_A003571
588 select SYS_FSL_ERRATUM_IFC_A003399
589 select SYS_FSL_HAS_DDR3
590 select SYS_FSL_HAS_SEC
591 select SYS_FSL_SEC_BE
592 select SYS_FSL_SEC_COMPAT_4
593 select SYS_PPC_E500_USE_DEBUG_TLB
600 select SYS_FSL_ERRATUM_A004508
601 select SYS_FSL_ERRATUM_A005125
602 select SYS_FSL_ERRATUM_ELBC_A001
603 select SYS_FSL_ERRATUM_ESDHC111
604 select SYS_FSL_HAS_DDR3
605 select SYS_FSL_HAS_SEC
606 select SYS_FSL_SEC_BE
607 select SYS_FSL_SEC_COMPAT_2
608 select SYS_PPC_E500_USE_DEBUG_TLB
614 select SYS_FSL_ERRATUM_A004508
615 select SYS_FSL_ERRATUM_A005125
616 select SYS_FSL_ERRATUM_ELBC_A001
617 select SYS_FSL_ERRATUM_ESDHC111
618 select SYS_FSL_HAS_DDR3
619 select SYS_FSL_HAS_SEC
620 select SYS_FSL_SEC_BE
621 select SYS_FSL_SEC_COMPAT_2
622 select SYS_PPC_E500_USE_DEBUG_TLB
628 select SYS_FSL_ERRATUM_A004508
629 select SYS_FSL_ERRATUM_A005125
630 select SYS_FSL_ERRATUM_ELBC_A001
631 select SYS_FSL_ERRATUM_ESDHC111
632 select SYS_FSL_HAS_DDR3
633 select SYS_FSL_HAS_SEC
634 select SYS_FSL_SEC_BE
635 select SYS_FSL_SEC_COMPAT_2
636 select SYS_PPC_E500_USE_DEBUG_TLB
642 select SYS_FSL_ERRATUM_A004477
643 select SYS_FSL_ERRATUM_A004508
644 select SYS_FSL_ERRATUM_A005125
645 select SYS_FSL_ERRATUM_ELBC_A001
646 select SYS_FSL_ERRATUM_ESDHC111
647 select SYS_FSL_ERRATUM_SATA_A001
648 select SYS_FSL_HAS_DDR3
649 select SYS_FSL_HAS_SEC
650 select SYS_FSL_SEC_BE
651 select SYS_FSL_SEC_COMPAT_2
652 select SYS_PPC_E500_USE_DEBUG_TLB
658 select SYS_FSL_ERRATUM_A004508
659 select SYS_FSL_ERRATUM_A005125
660 select SYS_FSL_ERRATUM_I2C_A004447
661 select SYS_FSL_HAS_DDR3
662 select SYS_FSL_HAS_SEC
663 select SYS_FSL_SEC_BE
664 select SYS_FSL_SEC_COMPAT_4
670 select SYS_FSL_ERRATUM_A004508
671 select SYS_FSL_ERRATUM_A005125
672 select SYS_FSL_ERRATUM_ELBC_A001
673 select SYS_FSL_ERRATUM_ESDHC111
674 select SYS_FSL_HAS_DDR3
675 select SYS_FSL_HAS_SEC
676 select SYS_FSL_SEC_BE
677 select SYS_FSL_SEC_COMPAT_2
678 select SYS_PPC_E500_USE_DEBUG_TLB
685 select SYS_FSL_ERRATUM_A004508
686 select SYS_FSL_ERRATUM_A005125
687 select SYS_FSL_ERRATUM_ELBC_A001
688 select SYS_FSL_ERRATUM_ESDHC111
689 select SYS_FSL_HAS_DDR3
690 select SYS_FSL_HAS_SEC
691 select SYS_FSL_SEC_BE
692 select SYS_FSL_SEC_COMPAT_2
693 select SYS_PPC_E500_USE_DEBUG_TLB
699 select SYS_FSL_ERRATUM_A004477
700 select SYS_FSL_ERRATUM_A004508
701 select SYS_FSL_ERRATUM_A005125
702 select SYS_FSL_ERRATUM_ESDHC111
703 select SYS_FSL_ERRATUM_ESDHC_A001
704 select SYS_FSL_HAS_DDR3
705 select SYS_FSL_HAS_SEC
706 select SYS_FSL_SEC_BE
707 select SYS_FSL_SEC_COMPAT_2
708 select SYS_PPC_E500_USE_DEBUG_TLB
716 select SYS_FSL_ERRATUM_A004510
717 select SYS_FSL_ERRATUM_A004849
718 select SYS_FSL_ERRATUM_A006261
719 select SYS_FSL_ERRATUM_CPU_A003999
720 select SYS_FSL_ERRATUM_DDR_A003
721 select SYS_FSL_ERRATUM_DDR_A003474
722 select SYS_FSL_ERRATUM_ESDHC111
723 select SYS_FSL_ERRATUM_I2C_A004447
724 select SYS_FSL_ERRATUM_NMG_CPU_A011
725 select SYS_FSL_ERRATUM_SRIO_A004034
726 select SYS_FSL_ERRATUM_USB14
727 select SYS_FSL_HAS_DDR3
728 select SYS_FSL_HAS_SEC
729 select SYS_FSL_QORIQ_CHASSIS1
730 select SYS_FSL_SEC_BE
731 select SYS_FSL_SEC_COMPAT_4
738 select SYS_FSL_DDR_VER_44
739 select SYS_FSL_ERRATUM_A004510
740 select SYS_FSL_ERRATUM_A004849
741 select SYS_FSL_ERRATUM_A005812
742 select SYS_FSL_ERRATUM_A006261
743 select SYS_FSL_ERRATUM_CPU_A003999
744 select SYS_FSL_ERRATUM_DDR_A003
745 select SYS_FSL_ERRATUM_DDR_A003474
746 select SYS_FSL_ERRATUM_ESDHC111
747 select SYS_FSL_ERRATUM_I2C_A004447
748 select SYS_FSL_ERRATUM_NMG_CPU_A011
749 select SYS_FSL_ERRATUM_SRIO_A004034
750 select SYS_FSL_ERRATUM_USB14
751 select SYS_FSL_HAS_DDR3
752 select SYS_FSL_HAS_SEC
753 select SYS_FSL_QORIQ_CHASSIS1
754 select SYS_FSL_SEC_BE
755 select SYS_FSL_SEC_COMPAT_4
762 select SYS_FSL_DDR_VER_44
763 select SYS_FSL_ERRATUM_A004510
764 select SYS_FSL_ERRATUM_A004580
765 select SYS_FSL_ERRATUM_A004849
766 select SYS_FSL_ERRATUM_A005812
767 select SYS_FSL_ERRATUM_A007075
768 select SYS_FSL_ERRATUM_CPC_A002
769 select SYS_FSL_ERRATUM_CPC_A003
770 select SYS_FSL_ERRATUM_CPU_A003999
771 select SYS_FSL_ERRATUM_DDR_A003
772 select SYS_FSL_ERRATUM_DDR_A003474
773 select SYS_FSL_ERRATUM_ELBC_A001
774 select SYS_FSL_ERRATUM_ESDHC111
775 select SYS_FSL_ERRATUM_ESDHC13
776 select SYS_FSL_ERRATUM_ESDHC135
777 select SYS_FSL_ERRATUM_I2C_A004447
778 select SYS_FSL_ERRATUM_NMG_CPU_A011
779 select SYS_FSL_ERRATUM_SRIO_A004034
780 select SYS_P4080_ERRATUM_CPU22
781 select SYS_P4080_ERRATUM_PCIE_A003
782 select SYS_P4080_ERRATUM_SERDES8
783 select SYS_P4080_ERRATUM_SERDES9
784 select SYS_P4080_ERRATUM_SERDES_A001
785 select SYS_P4080_ERRATUM_SERDES_A005
786 select SYS_FSL_HAS_DDR3
787 select SYS_FSL_HAS_SEC
788 select SYS_FSL_QORIQ_CHASSIS1
789 select SYS_FSL_SEC_BE
790 select SYS_FSL_SEC_COMPAT_4
797 select SYS_FSL_DDR_VER_44
798 select SYS_FSL_ERRATUM_A004510
799 select SYS_FSL_ERRATUM_A006261
800 select SYS_FSL_ERRATUM_DDR_A003
801 select SYS_FSL_ERRATUM_DDR_A003474
802 select SYS_FSL_ERRATUM_ESDHC111
803 select SYS_FSL_ERRATUM_I2C_A004447
804 select SYS_FSL_ERRATUM_SRIO_A004034
805 select SYS_FSL_ERRATUM_USB14
806 select SYS_FSL_HAS_DDR3
807 select SYS_FSL_HAS_SEC
808 select SYS_FSL_QORIQ_CHASSIS1
809 select SYS_FSL_SEC_BE
810 select SYS_FSL_SEC_COMPAT_4
818 select SYS_FSL_DDR_VER_44
819 select SYS_FSL_ERRATUM_A004510
820 select SYS_FSL_ERRATUM_A004699
821 select SYS_FSL_ERRATUM_A005812
822 select SYS_FSL_ERRATUM_A006261
823 select SYS_FSL_ERRATUM_DDR_A003
824 select SYS_FSL_ERRATUM_DDR_A003474
825 select SYS_FSL_ERRATUM_ESDHC111
826 select SYS_FSL_ERRATUM_USB14
827 select SYS_FSL_HAS_DDR3
828 select SYS_FSL_HAS_SEC
829 select SYS_FSL_QORIQ_CHASSIS1
830 select SYS_FSL_SEC_BE
831 select SYS_FSL_SEC_COMPAT_4
835 config ARCH_QEMU_E500
842 select SYS_FSL_DDR_VER_50
843 select SYS_FSL_ERRATUM_A008378
844 select SYS_FSL_ERRATUM_A009663
845 select SYS_FSL_ERRATUM_A009942
846 select SYS_FSL_ERRATUM_ESDHC111
847 select SYS_FSL_HAS_DDR3
848 select SYS_FSL_HAS_DDR4
849 select SYS_FSL_HAS_SEC
850 select SYS_FSL_QORIQ_CHASSIS2
851 select SYS_FSL_SEC_BE
852 select SYS_FSL_SEC_COMPAT_5
860 select SYS_FSL_DDR_VER_50
861 select SYS_FSL_ERRATUM_A008378
862 select SYS_FSL_ERRATUM_A009663
863 select SYS_FSL_ERRATUM_A009942
864 select SYS_FSL_ERRATUM_ESDHC111
865 select SYS_FSL_HAS_DDR3
866 select SYS_FSL_HAS_DDR4
867 select SYS_FSL_HAS_SEC
868 select SYS_FSL_QORIQ_CHASSIS2
869 select SYS_FSL_SEC_BE
870 select SYS_FSL_SEC_COMPAT_5
878 select SYS_FSL_DDR_VER_50
879 select SYS_FSL_ERRATUM_A008044
880 select SYS_FSL_ERRATUM_A008378
881 select SYS_FSL_ERRATUM_A009663
882 select SYS_FSL_ERRATUM_A009942
883 select SYS_FSL_ERRATUM_ESDHC111
884 select SYS_FSL_HAS_DDR3
885 select SYS_FSL_HAS_DDR4
886 select SYS_FSL_HAS_SEC
887 select SYS_FSL_QORIQ_CHASSIS2
888 select SYS_FSL_SEC_BE
889 select SYS_FSL_SEC_COMPAT_5
896 select SYS_FSL_DDR_VER_50
897 select SYS_FSL_ERRATUM_A008044
898 select SYS_FSL_ERRATUM_A008378
899 select SYS_FSL_ERRATUM_A009663
900 select SYS_FSL_ERRATUM_A009942
901 select SYS_FSL_ERRATUM_ESDHC111
902 select SYS_FSL_HAS_DDR3
903 select SYS_FSL_HAS_DDR4
904 select SYS_FSL_HAS_SEC
905 select SYS_FSL_QORIQ_CHASSIS2
906 select SYS_FSL_SEC_BE
907 select SYS_FSL_SEC_COMPAT_5
915 select SYS_FSL_DDR_VER_47
916 select SYS_FSL_ERRATUM_A006379
917 select SYS_FSL_ERRATUM_A006593
918 select SYS_FSL_ERRATUM_A007186
919 select SYS_FSL_ERRATUM_A007212
920 select SYS_FSL_ERRATUM_A007815
921 select SYS_FSL_ERRATUM_A007907
922 select SYS_FSL_ERRATUM_A009942
923 select SYS_FSL_ERRATUM_ESDHC111
924 select SYS_FSL_HAS_DDR3
925 select SYS_FSL_HAS_SEC
926 select SYS_FSL_QORIQ_CHASSIS2
927 select SYS_FSL_SEC_BE
928 select SYS_FSL_SEC_COMPAT_4
937 select SYS_FSL_DDR_VER_47
938 select SYS_FSL_ERRATUM_A006379
939 select SYS_FSL_ERRATUM_A006593
940 select SYS_FSL_ERRATUM_A007186
941 select SYS_FSL_ERRATUM_A007212
942 select SYS_FSL_ERRATUM_A009942
943 select SYS_FSL_ERRATUM_ESDHC111
944 select SYS_FSL_HAS_DDR3
945 select SYS_FSL_HAS_SEC
946 select SYS_FSL_QORIQ_CHASSIS2
947 select SYS_FSL_SEC_BE
948 select SYS_FSL_SEC_COMPAT_4
957 select SYS_FSL_DDR_VER_47
958 select SYS_FSL_ERRATUM_A004468
959 select SYS_FSL_ERRATUM_A005871
960 select SYS_FSL_ERRATUM_A006379
961 select SYS_FSL_ERRATUM_A006593
962 select SYS_FSL_ERRATUM_A007186
963 select SYS_FSL_ERRATUM_A007798
964 select SYS_FSL_ERRATUM_A009942
965 select SYS_FSL_HAS_DDR3
966 select SYS_FSL_HAS_SEC
967 select SYS_FSL_QORIQ_CHASSIS2
968 select SYS_FSL_SEC_BE
969 select SYS_FSL_SEC_COMPAT_4
978 select SYS_FSL_DDR_VER_47
979 select SYS_FSL_ERRATUM_A004468
980 select SYS_FSL_ERRATUM_A005871
981 select SYS_FSL_ERRATUM_A006261
982 select SYS_FSL_ERRATUM_A006379
983 select SYS_FSL_ERRATUM_A006593
984 select SYS_FSL_ERRATUM_A007186
985 select SYS_FSL_ERRATUM_A007798
986 select SYS_FSL_ERRATUM_A007815
987 select SYS_FSL_ERRATUM_A007907
988 select SYS_FSL_ERRATUM_A009942
989 select SYS_FSL_HAS_DDR3
990 select SYS_FSL_HAS_SEC
991 select SYS_FSL_QORIQ_CHASSIS2
992 select SYS_FSL_SEC_BE
993 select SYS_FSL_SEC_COMPAT_4
1005 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1010 Enble PowerPC E500MC core
1015 Enable PowerPC E6500 core
1020 Use Freescale common code for Local Access Window
1025 Enable Freescale Secure Boot feature. Normally selected
1026 by defconfig. If unsure, do not change.
1029 int "Maximum number of CPUs permitted for MPC85xx"
1030 default 12 if ARCH_T4240
1031 default 8 if ARCH_P4080 || \
1033 default 4 if ARCH_B4860 || \
1041 default 2 if ARCH_B4420 || \
1056 Set this number to the maximum number of possible CPUs in the SoC.
1057 SoCs may have multiple clusters with each cluster may have multiple
1058 ports. If some ports are reserved but higher ports are used for
1059 cores, count the reserved ports. This will allocate enough memory
1060 in spin table to properly handle all cores.
1062 config SYS_CCSRBAR_DEFAULT
1063 hex "Default CCSRBAR address"
1064 default 0xff700000 if ARCH_BSC9131 || \
1085 default 0xff600000 if ARCH_P1023
1086 default 0xfe000000 if ARCH_B4420 || \
1101 default 0xe0000000 if ARCH_QEMU_E500
1103 Default value of CCSRBAR comes from power-on-reset. It
1104 is fixed on each SoC. Some SoCs can have different value
1105 if changed by pre-boot regime. The value here must match
1106 the current value in SoC. If not sure, do not change.
1108 config SYS_FSL_ERRATUM_A004468
1111 config SYS_FSL_ERRATUM_A004477
1114 config SYS_FSL_ERRATUM_A004508
1117 config SYS_FSL_ERRATUM_A004580
1120 config SYS_FSL_ERRATUM_A004699
1123 config SYS_FSL_ERRATUM_A004849
1126 config SYS_FSL_ERRATUM_A004510
1129 config SYS_FSL_ERRATUM_A004510_SVR_REV
1131 depends on SYS_FSL_ERRATUM_A004510
1132 default 0x20 if ARCH_P4080
1135 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1137 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1140 config SYS_FSL_ERRATUM_A005125
1143 config SYS_FSL_ERRATUM_A005434
1146 config SYS_FSL_ERRATUM_A005812
1149 config SYS_FSL_ERRATUM_A005871
1152 config SYS_FSL_ERRATUM_A006261
1155 config SYS_FSL_ERRATUM_A006379
1158 config SYS_FSL_ERRATUM_A006384
1161 config SYS_FSL_ERRATUM_A006475
1164 config SYS_FSL_ERRATUM_A006593
1167 config SYS_FSL_ERRATUM_A007075
1170 config SYS_FSL_ERRATUM_A007186
1173 config SYS_FSL_ERRATUM_A007212
1176 config SYS_FSL_ERRATUM_A007815
1179 config SYS_FSL_ERRATUM_A007798
1182 config SYS_FSL_ERRATUM_A007907
1185 config SYS_FSL_ERRATUM_A008044
1188 config SYS_FSL_ERRATUM_CPC_A002
1191 config SYS_FSL_ERRATUM_CPC_A003
1194 config SYS_FSL_ERRATUM_CPU_A003999
1197 config SYS_FSL_ERRATUM_ELBC_A001
1200 config SYS_FSL_ERRATUM_I2C_A004447
1203 config SYS_FSL_A004447_SVR_REV
1205 depends on SYS_FSL_ERRATUM_I2C_A004447
1206 default 0x00 if ARCH_MPC8548
1207 default 0x10 if ARCH_P1010
1208 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1209 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1211 config SYS_FSL_ERRATUM_IFC_A002769
1214 config SYS_FSL_ERRATUM_IFC_A003399
1217 config SYS_FSL_ERRATUM_NMG_CPU_A011
1220 config SYS_FSL_ERRATUM_NMG_ETSEC129
1223 config SYS_FSL_ERRATUM_NMG_LBC103
1226 config SYS_FSL_ERRATUM_P1010_A003549
1229 config SYS_FSL_ERRATUM_SATA_A001
1232 config SYS_FSL_ERRATUM_SEC_A003571
1235 config SYS_FSL_ERRATUM_SRIO_A004034
1238 config SYS_FSL_ERRATUM_USB14
1241 config SYS_P4080_ERRATUM_CPU22
1244 config SYS_P4080_ERRATUM_PCIE_A003
1247 config SYS_P4080_ERRATUM_SERDES8
1250 config SYS_P4080_ERRATUM_SERDES9
1253 config SYS_P4080_ERRATUM_SERDES_A001
1256 config SYS_P4080_ERRATUM_SERDES_A005
1259 config SYS_FSL_QORIQ_CHASSIS1
1262 config SYS_FSL_QORIQ_CHASSIS2
1265 config SYS_FSL_NUM_LAWS
1266 int "Number of local access windows"
1268 default 32 if ARCH_B4420 || \
1279 default 16 if ARCH_T1023 || \
1283 default 12 if ARCH_BSC9131 || \
1297 default 10 if ARCH_MPC8544 || \
1301 default 8 if ARCH_MPC8540 || \
1306 Number of local access windows. This is fixed per SoC.
1307 If not sure, do not change.
1309 config SYS_FSL_THREADS_PER_CORE
1314 config SYS_NUM_TLBCAMS
1315 int "Number of TLB CAM entries"
1316 default 64 if E500MC
1319 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1320 16 for other E500 SoCs.
1325 config SYS_PPC_E500_USE_DEBUG_TLB
1334 config SYS_PPC_E500_DEBUG_TLB
1335 int "Temporary TLB entry for external debugger"
1336 depends on SYS_PPC_E500_USE_DEBUG_TLB
1337 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1338 default 1 if ARCH_MPC8536
1339 default 2 if ARCH_MPC8572 || \
1347 default 3 if ARCH_P1010 || \
1351 Select a temporary TLB entry to be used during boot to work
1352 around limitations in e500v1 and e500v2 external debugger
1353 support. This reduces the portions of the boot code where
1354 breakpoints and single stepping do not work. The value of this
1355 symbol should be set to the TLB1 entry to be used for this
1356 purpose. If unsure, do not change.
1358 config SYS_FSL_IFC_CLK_DIV
1359 int "Divider of platform clock"
1361 default 2 if ARCH_B4420 || \
1371 Defines divider of platform clock(clock input to
1374 config SYS_FSL_LBC_CLK_DIV
1375 int "Divider of platform clock"
1376 depends on FSL_ELBC || ARCH_MPC8540 || \
1377 ARCH_MPC8548 || ARCH_MPC8541 || \
1378 ARCH_MPC8555 || ARCH_MPC8560 || \
1381 default 2 if ARCH_P2041 || \
1389 Defines divider of platform clock(clock input to
1392 source "board/freescale/b4860qds/Kconfig"
1393 source "board/freescale/bsc9131rdb/Kconfig"
1394 source "board/freescale/bsc9132qds/Kconfig"
1395 source "board/freescale/c29xpcie/Kconfig"
1396 source "board/freescale/corenet_ds/Kconfig"
1397 source "board/freescale/mpc8536ds/Kconfig"
1398 source "board/freescale/mpc8540ads/Kconfig"
1399 source "board/freescale/mpc8541cds/Kconfig"
1400 source "board/freescale/mpc8544ds/Kconfig"
1401 source "board/freescale/mpc8548cds/Kconfig"
1402 source "board/freescale/mpc8555cds/Kconfig"
1403 source "board/freescale/mpc8560ads/Kconfig"
1404 source "board/freescale/mpc8568mds/Kconfig"
1405 source "board/freescale/mpc8569mds/Kconfig"
1406 source "board/freescale/mpc8572ds/Kconfig"
1407 source "board/freescale/p1010rdb/Kconfig"
1408 source "board/freescale/p1022ds/Kconfig"
1409 source "board/freescale/p1023rdb/Kconfig"
1410 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1411 source "board/freescale/p1_twr/Kconfig"
1412 source "board/freescale/p2041rdb/Kconfig"
1413 source "board/freescale/qemu-ppce500/Kconfig"
1414 source "board/freescale/t102xqds/Kconfig"
1415 source "board/freescale/t102xrdb/Kconfig"
1416 source "board/freescale/t1040qds/Kconfig"
1417 source "board/freescale/t104xrdb/Kconfig"
1418 source "board/freescale/t208xqds/Kconfig"
1419 source "board/freescale/t208xrdb/Kconfig"
1420 source "board/freescale/t4qds/Kconfig"
1421 source "board/freescale/t4rdb/Kconfig"
1422 source "board/gdsys/p1022/Kconfig"
1423 source "board/keymile/kmp204x/Kconfig"
1424 source "board/sbc8548/Kconfig"
1425 source "board/socrates/Kconfig"
1426 source "board/varisys/cyrus/Kconfig"
1427 source "board/xes/xpedite520x/Kconfig"
1428 source "board/xes/xpedite537x/Kconfig"
1429 source "board/xes/xpedite550x/Kconfig"
1430 source "board/Arcturus/ucp1020/Kconfig"