12 bool "Support sbc8548"
15 config TARGET_SOCRATES
16 bool "Support socrates"
19 config TARGET_B4420QDS
20 bool "Support B4420QDS"
25 config TARGET_B4860QDS
26 bool "Support B4860QDS"
28 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 config TARGET_BSC9131RDB
33 bool "Support BSC9131RDB"
36 select BOARD_EARLY_INIT_F
38 config TARGET_BSC9132QDS
39 bool "Support BSC9132QDS"
41 select BOARD_LATE_INIT if CHAIN_OF_TRUST
43 select BOARD_EARLY_INIT_F
45 config TARGET_C29XPCIE
46 bool "Support C29XPCIE"
48 select BOARD_LATE_INIT if CHAIN_OF_TRUST
54 bool "Support P3041DS"
57 select BOARD_LATE_INIT if CHAIN_OF_TRUST
60 bool "Support P4080DS"
63 select BOARD_LATE_INIT if CHAIN_OF_TRUST
66 bool "Support P5020DS"
69 select BOARD_LATE_INIT if CHAIN_OF_TRUST
72 bool "Support P5040DS"
75 select BOARD_LATE_INIT if CHAIN_OF_TRUST
77 config TARGET_MPC8536DS
78 bool "Support MPC8536DS"
80 # Use DDR3 controller with DDR2 DIMMs on this board
81 select SYS_FSL_DDRC_GEN3
83 config TARGET_MPC8540ADS
84 bool "Support MPC8540ADS"
87 config TARGET_MPC8541CDS
88 bool "Support MPC8541CDS"
91 config TARGET_MPC8544DS
92 bool "Support MPC8544DS"
95 config TARGET_MPC8548CDS
96 bool "Support MPC8548CDS"
99 config TARGET_MPC8555CDS
100 bool "Support MPC8555CDS"
103 config TARGET_MPC8560ADS
104 bool "Support MPC8560ADS"
107 config TARGET_MPC8568MDS
108 bool "Support MPC8568MDS"
111 config TARGET_MPC8569MDS
112 bool "Support MPC8569MDS"
115 config TARGET_MPC8572DS
116 bool "Support MPC8572DS"
118 # Use DDR3 controller with DDR2 DIMMs on this board
119 select SYS_FSL_DDRC_GEN3
121 config TARGET_P1010RDB_PA
122 bool "Support P1010RDB_PA"
124 select BOARD_LATE_INIT if CHAIN_OF_TRUST
128 config TARGET_P1010RDB_PB
129 bool "Support P1010RDB_PB"
131 select BOARD_LATE_INIT if CHAIN_OF_TRUST
135 config TARGET_P1022DS
136 bool "Support P1022DS"
141 config TARGET_P1023RDB
142 bool "Support P1023RDB"
145 config TARGET_P1020MBG
146 bool "Support P1020MBG-PC"
151 config TARGET_P1020RDB_PC
152 bool "Support P1020RDB-PC"
157 config TARGET_P1020RDB_PD
158 bool "Support P1020RDB-PD"
163 config TARGET_P1020UTM
164 bool "Support P1020UTM"
169 config TARGET_P1021RDB
170 bool "Support P1021RDB"
175 config TARGET_P1024RDB
176 bool "Support P1024RDB"
181 config TARGET_P1025RDB
182 bool "Support P1025RDB"
187 config TARGET_P2020RDB
188 bool "Support P2020RDB-PC"
194 bool "Support p1_twr"
197 config TARGET_P2041RDB
198 bool "Support P2041RDB"
200 select BOARD_LATE_INIT if CHAIN_OF_TRUST
203 config TARGET_QEMU_PPCE500
204 bool "Support qemu-ppce500"
205 select ARCH_QEMU_E500
208 config TARGET_T1024QDS
209 bool "Support T1024QDS"
211 select BOARD_LATE_INIT if CHAIN_OF_TRUST
215 config TARGET_T1023RDB
216 bool "Support T1023RDB"
218 select BOARD_LATE_INIT if CHAIN_OF_TRUST
222 config TARGET_T1024RDB
223 bool "Support T1024RDB"
225 select BOARD_LATE_INIT if CHAIN_OF_TRUST
229 config TARGET_T1040QDS
230 bool "Support T1040QDS"
232 select BOARD_LATE_INIT if CHAIN_OF_TRUST
235 config TARGET_T1040RDB
236 bool "Support T1040RDB"
238 select BOARD_LATE_INIT if CHAIN_OF_TRUST
242 config TARGET_T1040D4RDB
243 bool "Support T1040D4RDB"
245 select BOARD_LATE_INIT if CHAIN_OF_TRUST
249 config TARGET_T1042RDB
250 bool "Support T1042RDB"
252 select BOARD_LATE_INIT if CHAIN_OF_TRUST
256 config TARGET_T1042D4RDB
257 bool "Support T1042D4RDB"
259 select BOARD_LATE_INIT if CHAIN_OF_TRUST
263 config TARGET_T1042RDB_PI
264 bool "Support T1042RDB_PI"
266 select BOARD_LATE_INIT if CHAIN_OF_TRUST
270 config TARGET_T2080QDS
271 bool "Support T2080QDS"
273 select BOARD_LATE_INIT if CHAIN_OF_TRUST
277 config TARGET_T2080RDB
278 bool "Support T2080RDB"
280 select BOARD_LATE_INIT if CHAIN_OF_TRUST
284 config TARGET_T2081QDS
285 bool "Support T2081QDS"
290 config TARGET_T4160QDS
291 bool "Support T4160QDS"
293 select BOARD_LATE_INIT if CHAIN_OF_TRUST
297 config TARGET_T4160RDB
298 bool "Support T4160RDB"
303 config TARGET_T4240QDS
304 bool "Support T4240QDS"
306 select BOARD_LATE_INIT if CHAIN_OF_TRUST
310 config TARGET_T4240RDB
311 bool "Support T4240RDB"
316 config TARGET_CONTROLCENTERD
317 bool "Support controlcenterd"
320 config TARGET_KMP204X
321 bool "Support kmp204x"
325 config TARGET_XPEDITE520X
326 bool "Support xpedite520x"
329 config TARGET_XPEDITE537X
330 bool "Support xpedite537x"
332 # Use DDR3 controller with DDR2 DIMMs on this board
333 select SYS_FSL_DDRC_GEN3
335 config TARGET_XPEDITE550X
336 bool "Support xpedite550x"
339 config TARGET_UCP1020
340 bool "Support uCP1020"
343 config TARGET_CYRUS_P5020
344 bool "Support Varisys Cyrus P5020"
348 config TARGET_CYRUS_P5040
349 bool "Support Varisys Cyrus P5040"
360 select SYS_FSL_DDR_VER_47
361 select SYS_FSL_ERRATUM_A004477
362 select SYS_FSL_ERRATUM_A005871
363 select SYS_FSL_ERRATUM_A006379
364 select SYS_FSL_ERRATUM_A006384
365 select SYS_FSL_ERRATUM_A006475
366 select SYS_FSL_ERRATUM_A006593
367 select SYS_FSL_ERRATUM_A007075
368 select SYS_FSL_ERRATUM_A007186
369 select SYS_FSL_ERRATUM_A007212
370 select SYS_FSL_ERRATUM_A009942
371 select SYS_FSL_HAS_DDR3
372 select SYS_FSL_HAS_SEC
373 select SYS_FSL_QORIQ_CHASSIS2
374 select SYS_FSL_SEC_BE
375 select SYS_FSL_SEC_COMPAT_4
384 select SYS_FSL_DDR_VER_47
385 select SYS_FSL_ERRATUM_A004477
386 select SYS_FSL_ERRATUM_A005871
387 select SYS_FSL_ERRATUM_A006379
388 select SYS_FSL_ERRATUM_A006384
389 select SYS_FSL_ERRATUM_A006475
390 select SYS_FSL_ERRATUM_A006593
391 select SYS_FSL_ERRATUM_A007075
392 select SYS_FSL_ERRATUM_A007186
393 select SYS_FSL_ERRATUM_A007212
394 select SYS_FSL_ERRATUM_A007907
395 select SYS_FSL_ERRATUM_A009942
396 select SYS_FSL_HAS_DDR3
397 select SYS_FSL_HAS_SEC
398 select SYS_FSL_QORIQ_CHASSIS2
399 select SYS_FSL_SEC_BE
400 select SYS_FSL_SEC_COMPAT_4
407 select SYS_FSL_DDR_VER_44
408 select SYS_FSL_ERRATUM_A004477
409 select SYS_FSL_ERRATUM_A005125
410 select SYS_FSL_ERRATUM_ESDHC111
411 select SYS_FSL_HAS_DDR3
412 select SYS_FSL_HAS_SEC
413 select SYS_FSL_SEC_BE
414 select SYS_FSL_SEC_COMPAT_4
420 select SYS_FSL_DDR_VER_46
421 select SYS_FSL_ERRATUM_A004477
422 select SYS_FSL_ERRATUM_A005125
423 select SYS_FSL_ERRATUM_A005434
424 select SYS_FSL_ERRATUM_ESDHC111
425 select SYS_FSL_ERRATUM_I2C_A004447
426 select SYS_FSL_ERRATUM_IFC_A002769
427 select SYS_FSL_HAS_DDR3
428 select SYS_FSL_HAS_SEC
429 select SYS_FSL_SEC_BE
430 select SYS_FSL_SEC_COMPAT_4
431 select SYS_PPC_E500_USE_DEBUG_TLB
437 select SYS_FSL_DDR_VER_46
438 select SYS_FSL_ERRATUM_A005125
439 select SYS_FSL_ERRATUM_ESDHC111
440 select SYS_FSL_HAS_DDR3
441 select SYS_FSL_HAS_SEC
442 select SYS_FSL_SEC_BE
443 select SYS_FSL_SEC_COMPAT_6
444 select SYS_PPC_E500_USE_DEBUG_TLB
450 select SYS_FSL_ERRATUM_A004508
451 select SYS_FSL_ERRATUM_A005125
452 select SYS_FSL_HAS_DDR2
453 select SYS_FSL_HAS_DDR3
454 select SYS_FSL_HAS_SEC
455 select SYS_FSL_SEC_BE
456 select SYS_FSL_SEC_COMPAT_2
457 select SYS_PPC_E500_USE_DEBUG_TLB
462 select SYS_FSL_HAS_DDR1
467 select SYS_FSL_HAS_DDR1
468 select SYS_FSL_HAS_SEC
469 select SYS_FSL_SEC_BE
470 select SYS_FSL_SEC_COMPAT_2
475 select SYS_FSL_ERRATUM_A005125
476 select SYS_FSL_HAS_DDR2
477 select SYS_FSL_HAS_SEC
478 select SYS_FSL_SEC_BE
479 select SYS_FSL_SEC_COMPAT_2
480 select SYS_PPC_E500_USE_DEBUG_TLB
485 select SYS_FSL_ERRATUM_A005125
486 select SYS_FSL_ERRATUM_NMG_DDR120
487 select SYS_FSL_ERRATUM_NMG_LBC103
488 select SYS_FSL_ERRATUM_NMG_ETSEC129
489 select SYS_FSL_ERRATUM_I2C_A004447
490 select SYS_FSL_HAS_DDR2
491 select SYS_FSL_HAS_DDR1
492 select SYS_FSL_HAS_SEC
493 select SYS_FSL_SEC_BE
494 select SYS_FSL_SEC_COMPAT_2
495 select SYS_PPC_E500_USE_DEBUG_TLB
500 select SYS_FSL_HAS_DDR1
501 select SYS_FSL_HAS_SEC
502 select SYS_FSL_SEC_BE
503 select SYS_FSL_SEC_COMPAT_2
508 select SYS_FSL_HAS_DDR1
513 select SYS_FSL_HAS_DDR2
514 select SYS_FSL_HAS_SEC
515 select SYS_FSL_SEC_BE
516 select SYS_FSL_SEC_COMPAT_2
521 select SYS_FSL_ERRATUM_A004508
522 select SYS_FSL_ERRATUM_A005125
523 select SYS_FSL_HAS_DDR3
524 select SYS_FSL_HAS_SEC
525 select SYS_FSL_SEC_BE
526 select SYS_FSL_SEC_COMPAT_2
531 select SYS_FSL_ERRATUM_A004508
532 select SYS_FSL_ERRATUM_A005125
533 select SYS_FSL_ERRATUM_DDR_115
534 select SYS_FSL_ERRATUM_DDR111_DDR134
535 select SYS_FSL_HAS_DDR2
536 select SYS_FSL_HAS_DDR3
537 select SYS_FSL_HAS_SEC
538 select SYS_FSL_SEC_BE
539 select SYS_FSL_SEC_COMPAT_2
540 select SYS_PPC_E500_USE_DEBUG_TLB
545 select SYS_FSL_ERRATUM_A004477
546 select SYS_FSL_ERRATUM_A004508
547 select SYS_FSL_ERRATUM_A005125
548 select SYS_FSL_ERRATUM_A006261
549 select SYS_FSL_ERRATUM_A007075
550 select SYS_FSL_ERRATUM_ESDHC111
551 select SYS_FSL_ERRATUM_I2C_A004447
552 select SYS_FSL_ERRATUM_IFC_A002769
553 select SYS_FSL_ERRATUM_P1010_A003549
554 select SYS_FSL_ERRATUM_SEC_A003571
555 select SYS_FSL_ERRATUM_IFC_A003399
556 select SYS_FSL_HAS_DDR3
557 select SYS_FSL_HAS_SEC
558 select SYS_FSL_SEC_BE
559 select SYS_FSL_SEC_COMPAT_4
560 select SYS_PPC_E500_USE_DEBUG_TLB
566 select SYS_FSL_ERRATUM_A004508
567 select SYS_FSL_ERRATUM_A005125
568 select SYS_FSL_ERRATUM_ELBC_A001
569 select SYS_FSL_ERRATUM_ESDHC111
570 select SYS_FSL_HAS_DDR3
571 select SYS_FSL_HAS_SEC
572 select SYS_FSL_SEC_BE
573 select SYS_FSL_SEC_COMPAT_2
574 select SYS_PPC_E500_USE_DEBUG_TLB
579 select SYS_FSL_ERRATUM_A004508
580 select SYS_FSL_ERRATUM_A005125
581 select SYS_FSL_ERRATUM_ELBC_A001
582 select SYS_FSL_ERRATUM_ESDHC111
583 select SYS_FSL_HAS_DDR3
584 select SYS_FSL_HAS_SEC
585 select SYS_FSL_SEC_BE
586 select SYS_FSL_SEC_COMPAT_2
587 select SYS_PPC_E500_USE_DEBUG_TLB
592 select SYS_FSL_ERRATUM_A004508
593 select SYS_FSL_ERRATUM_A005125
594 select SYS_FSL_ERRATUM_ELBC_A001
595 select SYS_FSL_ERRATUM_ESDHC111
596 select SYS_FSL_HAS_DDR3
597 select SYS_FSL_HAS_SEC
598 select SYS_FSL_SEC_BE
599 select SYS_FSL_SEC_COMPAT_2
600 select SYS_PPC_E500_USE_DEBUG_TLB
605 select SYS_FSL_ERRATUM_A004477
606 select SYS_FSL_ERRATUM_A004508
607 select SYS_FSL_ERRATUM_A005125
608 select SYS_FSL_ERRATUM_ELBC_A001
609 select SYS_FSL_ERRATUM_ESDHC111
610 select SYS_FSL_ERRATUM_SATA_A001
611 select SYS_FSL_HAS_DDR3
612 select SYS_FSL_HAS_SEC
613 select SYS_FSL_SEC_BE
614 select SYS_FSL_SEC_COMPAT_2
615 select SYS_PPC_E500_USE_DEBUG_TLB
620 select SYS_FSL_ERRATUM_A004508
621 select SYS_FSL_ERRATUM_A005125
622 select SYS_FSL_ERRATUM_I2C_A004447
623 select SYS_FSL_HAS_DDR3
624 select SYS_FSL_HAS_SEC
625 select SYS_FSL_SEC_BE
626 select SYS_FSL_SEC_COMPAT_4
631 select SYS_FSL_ERRATUM_A004508
632 select SYS_FSL_ERRATUM_A005125
633 select SYS_FSL_ERRATUM_ELBC_A001
634 select SYS_FSL_ERRATUM_ESDHC111
635 select SYS_FSL_HAS_DDR3
636 select SYS_FSL_HAS_SEC
637 select SYS_FSL_SEC_BE
638 select SYS_FSL_SEC_COMPAT_2
639 select SYS_PPC_E500_USE_DEBUG_TLB
644 select SYS_FSL_ERRATUM_A004508
645 select SYS_FSL_ERRATUM_A005125
646 select SYS_FSL_ERRATUM_ELBC_A001
647 select SYS_FSL_ERRATUM_ESDHC111
648 select SYS_FSL_HAS_DDR3
649 select SYS_FSL_HAS_SEC
650 select SYS_FSL_SEC_BE
651 select SYS_FSL_SEC_COMPAT_2
652 select SYS_PPC_E500_USE_DEBUG_TLB
657 select SYS_FSL_ERRATUM_A004477
658 select SYS_FSL_ERRATUM_A004508
659 select SYS_FSL_ERRATUM_A005125
660 select SYS_FSL_ERRATUM_ESDHC111
661 select SYS_FSL_ERRATUM_ESDHC_A001
662 select SYS_FSL_HAS_DDR3
663 select SYS_FSL_HAS_SEC
664 select SYS_FSL_SEC_BE
665 select SYS_FSL_SEC_COMPAT_2
666 select SYS_PPC_E500_USE_DEBUG_TLB
672 select SYS_FSL_ERRATUM_A004510
673 select SYS_FSL_ERRATUM_A004849
674 select SYS_FSL_ERRATUM_A006261
675 select SYS_FSL_ERRATUM_CPU_A003999
676 select SYS_FSL_ERRATUM_DDR_A003
677 select SYS_FSL_ERRATUM_DDR_A003474
678 select SYS_FSL_ERRATUM_ESDHC111
679 select SYS_FSL_ERRATUM_I2C_A004447
680 select SYS_FSL_ERRATUM_NMG_CPU_A011
681 select SYS_FSL_ERRATUM_SRIO_A004034
682 select SYS_FSL_ERRATUM_USB14
683 select SYS_FSL_HAS_DDR3
684 select SYS_FSL_HAS_SEC
685 select SYS_FSL_QORIQ_CHASSIS1
686 select SYS_FSL_SEC_BE
687 select SYS_FSL_SEC_COMPAT_4
693 select SYS_FSL_DDR_VER_44
694 select SYS_FSL_ERRATUM_A004510
695 select SYS_FSL_ERRATUM_A004849
696 select SYS_FSL_ERRATUM_A005812
697 select SYS_FSL_ERRATUM_A006261
698 select SYS_FSL_ERRATUM_CPU_A003999
699 select SYS_FSL_ERRATUM_DDR_A003
700 select SYS_FSL_ERRATUM_DDR_A003474
701 select SYS_FSL_ERRATUM_ESDHC111
702 select SYS_FSL_ERRATUM_I2C_A004447
703 select SYS_FSL_ERRATUM_NMG_CPU_A011
704 select SYS_FSL_ERRATUM_SRIO_A004034
705 select SYS_FSL_ERRATUM_USB14
706 select SYS_FSL_HAS_DDR3
707 select SYS_FSL_HAS_SEC
708 select SYS_FSL_QORIQ_CHASSIS1
709 select SYS_FSL_SEC_BE
710 select SYS_FSL_SEC_COMPAT_4
716 select SYS_FSL_DDR_VER_44
717 select SYS_FSL_ERRATUM_A004510
718 select SYS_FSL_ERRATUM_A004580
719 select SYS_FSL_ERRATUM_A004849
720 select SYS_FSL_ERRATUM_A005812
721 select SYS_FSL_ERRATUM_A007075
722 select SYS_FSL_ERRATUM_CPC_A002
723 select SYS_FSL_ERRATUM_CPC_A003
724 select SYS_FSL_ERRATUM_CPU_A003999
725 select SYS_FSL_ERRATUM_DDR_A003
726 select SYS_FSL_ERRATUM_DDR_A003474
727 select SYS_FSL_ERRATUM_ELBC_A001
728 select SYS_FSL_ERRATUM_ESDHC111
729 select SYS_FSL_ERRATUM_ESDHC13
730 select SYS_FSL_ERRATUM_ESDHC135
731 select SYS_FSL_ERRATUM_I2C_A004447
732 select SYS_FSL_ERRATUM_NMG_CPU_A011
733 select SYS_FSL_ERRATUM_SRIO_A004034
734 select SYS_P4080_ERRATUM_CPU22
735 select SYS_P4080_ERRATUM_PCIE_A003
736 select SYS_P4080_ERRATUM_SERDES8
737 select SYS_P4080_ERRATUM_SERDES9
738 select SYS_P4080_ERRATUM_SERDES_A001
739 select SYS_P4080_ERRATUM_SERDES_A005
740 select SYS_FSL_HAS_DDR3
741 select SYS_FSL_HAS_SEC
742 select SYS_FSL_QORIQ_CHASSIS1
743 select SYS_FSL_SEC_BE
744 select SYS_FSL_SEC_COMPAT_4
750 select SYS_FSL_DDR_VER_44
751 select SYS_FSL_ERRATUM_A004510
752 select SYS_FSL_ERRATUM_A006261
753 select SYS_FSL_ERRATUM_DDR_A003
754 select SYS_FSL_ERRATUM_DDR_A003474
755 select SYS_FSL_ERRATUM_ESDHC111
756 select SYS_FSL_ERRATUM_I2C_A004447
757 select SYS_FSL_ERRATUM_SRIO_A004034
758 select SYS_FSL_ERRATUM_USB14
759 select SYS_FSL_HAS_DDR3
760 select SYS_FSL_HAS_SEC
761 select SYS_FSL_QORIQ_CHASSIS1
762 select SYS_FSL_SEC_BE
763 select SYS_FSL_SEC_COMPAT_4
770 select SYS_FSL_DDR_VER_44
771 select SYS_FSL_ERRATUM_A004510
772 select SYS_FSL_ERRATUM_A004699
773 select SYS_FSL_ERRATUM_A005812
774 select SYS_FSL_ERRATUM_A006261
775 select SYS_FSL_ERRATUM_DDR_A003
776 select SYS_FSL_ERRATUM_DDR_A003474
777 select SYS_FSL_ERRATUM_ESDHC111
778 select SYS_FSL_ERRATUM_USB14
779 select SYS_FSL_HAS_DDR3
780 select SYS_FSL_HAS_SEC
781 select SYS_FSL_QORIQ_CHASSIS1
782 select SYS_FSL_SEC_BE
783 select SYS_FSL_SEC_COMPAT_4
786 config ARCH_QEMU_E500
793 select SYS_FSL_DDR_VER_50
794 select SYS_FSL_ERRATUM_A008378
795 select SYS_FSL_ERRATUM_A009663
796 select SYS_FSL_ERRATUM_A009942
797 select SYS_FSL_ERRATUM_ESDHC111
798 select SYS_FSL_HAS_DDR3
799 select SYS_FSL_HAS_DDR4
800 select SYS_FSL_HAS_SEC
801 select SYS_FSL_QORIQ_CHASSIS2
802 select SYS_FSL_SEC_BE
803 select SYS_FSL_SEC_COMPAT_5
810 select SYS_FSL_DDR_VER_50
811 select SYS_FSL_ERRATUM_A008378
812 select SYS_FSL_ERRATUM_A009663
813 select SYS_FSL_ERRATUM_A009942
814 select SYS_FSL_ERRATUM_ESDHC111
815 select SYS_FSL_HAS_DDR3
816 select SYS_FSL_HAS_DDR4
817 select SYS_FSL_HAS_SEC
818 select SYS_FSL_QORIQ_CHASSIS2
819 select SYS_FSL_SEC_BE
820 select SYS_FSL_SEC_COMPAT_5
827 select SYS_FSL_DDR_VER_50
828 select SYS_FSL_ERRATUM_A008044
829 select SYS_FSL_ERRATUM_A008378
830 select SYS_FSL_ERRATUM_A009663
831 select SYS_FSL_ERRATUM_A009942
832 select SYS_FSL_ERRATUM_ESDHC111
833 select SYS_FSL_HAS_DDR3
834 select SYS_FSL_HAS_DDR4
835 select SYS_FSL_HAS_SEC
836 select SYS_FSL_QORIQ_CHASSIS2
837 select SYS_FSL_SEC_BE
838 select SYS_FSL_SEC_COMPAT_5
845 select SYS_FSL_DDR_VER_50
846 select SYS_FSL_ERRATUM_A008044
847 select SYS_FSL_ERRATUM_A008378
848 select SYS_FSL_ERRATUM_A009663
849 select SYS_FSL_ERRATUM_A009942
850 select SYS_FSL_ERRATUM_ESDHC111
851 select SYS_FSL_HAS_DDR3
852 select SYS_FSL_HAS_DDR4
853 select SYS_FSL_HAS_SEC
854 select SYS_FSL_QORIQ_CHASSIS2
855 select SYS_FSL_SEC_BE
856 select SYS_FSL_SEC_COMPAT_5
864 select SYS_FSL_DDR_VER_47
865 select SYS_FSL_ERRATUM_A006379
866 select SYS_FSL_ERRATUM_A006593
867 select SYS_FSL_ERRATUM_A007186
868 select SYS_FSL_ERRATUM_A007212
869 select SYS_FSL_ERRATUM_A007815
870 select SYS_FSL_ERRATUM_A007907
871 select SYS_FSL_ERRATUM_A009942
872 select SYS_FSL_ERRATUM_ESDHC111
873 select SYS_FSL_HAS_DDR3
874 select SYS_FSL_HAS_SEC
875 select SYS_FSL_QORIQ_CHASSIS2
876 select SYS_FSL_SEC_BE
877 select SYS_FSL_SEC_COMPAT_4
886 select SYS_FSL_DDR_VER_47
887 select SYS_FSL_ERRATUM_A006379
888 select SYS_FSL_ERRATUM_A006593
889 select SYS_FSL_ERRATUM_A007186
890 select SYS_FSL_ERRATUM_A007212
891 select SYS_FSL_ERRATUM_A009942
892 select SYS_FSL_ERRATUM_ESDHC111
893 select SYS_FSL_HAS_DDR3
894 select SYS_FSL_HAS_SEC
895 select SYS_FSL_QORIQ_CHASSIS2
896 select SYS_FSL_SEC_BE
897 select SYS_FSL_SEC_COMPAT_4
906 select SYS_FSL_DDR_VER_47
907 select SYS_FSL_ERRATUM_A004468
908 select SYS_FSL_ERRATUM_A005871
909 select SYS_FSL_ERRATUM_A006379
910 select SYS_FSL_ERRATUM_A006593
911 select SYS_FSL_ERRATUM_A007186
912 select SYS_FSL_ERRATUM_A007798
913 select SYS_FSL_ERRATUM_A009942
914 select SYS_FSL_HAS_DDR3
915 select SYS_FSL_HAS_SEC
916 select SYS_FSL_QORIQ_CHASSIS2
917 select SYS_FSL_SEC_BE
918 select SYS_FSL_SEC_COMPAT_4
927 select SYS_FSL_DDR_VER_47
928 select SYS_FSL_ERRATUM_A004468
929 select SYS_FSL_ERRATUM_A005871
930 select SYS_FSL_ERRATUM_A006261
931 select SYS_FSL_ERRATUM_A006379
932 select SYS_FSL_ERRATUM_A006593
933 select SYS_FSL_ERRATUM_A007186
934 select SYS_FSL_ERRATUM_A007798
935 select SYS_FSL_ERRATUM_A007815
936 select SYS_FSL_ERRATUM_A007907
937 select SYS_FSL_ERRATUM_A009942
938 select SYS_FSL_HAS_DDR3
939 select SYS_FSL_HAS_SEC
940 select SYS_FSL_QORIQ_CHASSIS2
941 select SYS_FSL_SEC_BE
942 select SYS_FSL_SEC_COMPAT_4
954 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
959 Enble PowerPC E500MC core
964 Enable PowerPC E6500 core
969 Use Freescale common code for Local Access Window
974 Enable Freescale Secure Boot feature. Normally selected
975 by defconfig. If unsure, do not change.
978 int "Maximum number of CPUs permitted for MPC85xx"
979 default 12 if ARCH_T4240
980 default 8 if ARCH_P4080 || \
982 default 4 if ARCH_B4860 || \
990 default 2 if ARCH_B4420 || \
1005 Set this number to the maximum number of possible CPUs in the SoC.
1006 SoCs may have multiple clusters with each cluster may have multiple
1007 ports. If some ports are reserved but higher ports are used for
1008 cores, count the reserved ports. This will allocate enough memory
1009 in spin table to properly handle all cores.
1011 config SYS_CCSRBAR_DEFAULT
1012 hex "Default CCSRBAR address"
1013 default 0xff700000 if ARCH_BSC9131 || \
1034 default 0xff600000 if ARCH_P1023
1035 default 0xfe000000 if ARCH_B4420 || \
1050 default 0xe0000000 if ARCH_QEMU_E500
1052 Default value of CCSRBAR comes from power-on-reset. It
1053 is fixed on each SoC. Some SoCs can have different value
1054 if changed by pre-boot regime. The value here must match
1055 the current value in SoC. If not sure, do not change.
1057 config SYS_FSL_ERRATUM_A004468
1060 config SYS_FSL_ERRATUM_A004477
1063 config SYS_FSL_ERRATUM_A004508
1066 config SYS_FSL_ERRATUM_A004580
1069 config SYS_FSL_ERRATUM_A004699
1072 config SYS_FSL_ERRATUM_A004849
1075 config SYS_FSL_ERRATUM_A004510
1078 config SYS_FSL_ERRATUM_A004510_SVR_REV
1080 depends on SYS_FSL_ERRATUM_A004510
1081 default 0x20 if ARCH_P4080
1084 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1086 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1089 config SYS_FSL_ERRATUM_A005125
1092 config SYS_FSL_ERRATUM_A005434
1095 config SYS_FSL_ERRATUM_A005812
1098 config SYS_FSL_ERRATUM_A005871
1101 config SYS_FSL_ERRATUM_A006261
1104 config SYS_FSL_ERRATUM_A006379
1107 config SYS_FSL_ERRATUM_A006384
1110 config SYS_FSL_ERRATUM_A006475
1113 config SYS_FSL_ERRATUM_A006593
1116 config SYS_FSL_ERRATUM_A007075
1119 config SYS_FSL_ERRATUM_A007186
1122 config SYS_FSL_ERRATUM_A007212
1125 config SYS_FSL_ERRATUM_A007815
1128 config SYS_FSL_ERRATUM_A007798
1131 config SYS_FSL_ERRATUM_A007907
1134 config SYS_FSL_ERRATUM_A008044
1137 config SYS_FSL_ERRATUM_CPC_A002
1140 config SYS_FSL_ERRATUM_CPC_A003
1143 config SYS_FSL_ERRATUM_CPU_A003999
1146 config SYS_FSL_ERRATUM_ELBC_A001
1149 config SYS_FSL_ERRATUM_I2C_A004447
1152 config SYS_FSL_A004447_SVR_REV
1154 depends on SYS_FSL_ERRATUM_I2C_A004447
1155 default 0x00 if ARCH_MPC8548
1156 default 0x10 if ARCH_P1010
1157 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1158 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1160 config SYS_FSL_ERRATUM_IFC_A002769
1163 config SYS_FSL_ERRATUM_IFC_A003399
1166 config SYS_FSL_ERRATUM_NMG_CPU_A011
1169 config SYS_FSL_ERRATUM_NMG_ETSEC129
1172 config SYS_FSL_ERRATUM_NMG_LBC103
1175 config SYS_FSL_ERRATUM_P1010_A003549
1178 config SYS_FSL_ERRATUM_SATA_A001
1181 config SYS_FSL_ERRATUM_SEC_A003571
1184 config SYS_FSL_ERRATUM_SRIO_A004034
1187 config SYS_FSL_ERRATUM_USB14
1190 config SYS_P4080_ERRATUM_CPU22
1193 config SYS_P4080_ERRATUM_PCIE_A003
1196 config SYS_P4080_ERRATUM_SERDES8
1199 config SYS_P4080_ERRATUM_SERDES9
1202 config SYS_P4080_ERRATUM_SERDES_A001
1205 config SYS_P4080_ERRATUM_SERDES_A005
1208 config SYS_FSL_QORIQ_CHASSIS1
1211 config SYS_FSL_QORIQ_CHASSIS2
1214 config SYS_FSL_NUM_LAWS
1215 int "Number of local access windows"
1217 default 32 if ARCH_B4420 || \
1228 default 16 if ARCH_T1023 || \
1232 default 12 if ARCH_BSC9131 || \
1246 default 10 if ARCH_MPC8544 || \
1250 default 8 if ARCH_MPC8540 || \
1255 Number of local access windows. This is fixed per SoC.
1256 If not sure, do not change.
1258 config SYS_FSL_THREADS_PER_CORE
1263 config SYS_NUM_TLBCAMS
1264 int "Number of TLB CAM entries"
1265 default 64 if E500MC
1268 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1269 16 for other E500 SoCs.
1274 config SYS_PPC_E500_USE_DEBUG_TLB
1280 config SYS_PPC_E500_DEBUG_TLB
1281 int "Temporary TLB entry for external debugger"
1282 depends on SYS_PPC_E500_USE_DEBUG_TLB
1283 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1284 default 1 if ARCH_MPC8536
1285 default 2 if ARCH_MPC8572 || \
1293 default 3 if ARCH_P1010 || \
1297 Select a temporary TLB entry to be used during boot to work
1298 around limitations in e500v1 and e500v2 external debugger
1299 support. This reduces the portions of the boot code where
1300 breakpoints and single stepping do not work. The value of this
1301 symbol should be set to the TLB1 entry to be used for this
1302 purpose. If unsure, do not change.
1304 config SYS_FSL_IFC_CLK_DIV
1305 int "Divider of platform clock"
1307 default 2 if ARCH_B4420 || \
1317 Defines divider of platform clock(clock input to
1320 source "board/freescale/b4860qds/Kconfig"
1321 source "board/freescale/bsc9131rdb/Kconfig"
1322 source "board/freescale/bsc9132qds/Kconfig"
1323 source "board/freescale/c29xpcie/Kconfig"
1324 source "board/freescale/corenet_ds/Kconfig"
1325 source "board/freescale/mpc8536ds/Kconfig"
1326 source "board/freescale/mpc8540ads/Kconfig"
1327 source "board/freescale/mpc8541cds/Kconfig"
1328 source "board/freescale/mpc8544ds/Kconfig"
1329 source "board/freescale/mpc8548cds/Kconfig"
1330 source "board/freescale/mpc8555cds/Kconfig"
1331 source "board/freescale/mpc8560ads/Kconfig"
1332 source "board/freescale/mpc8568mds/Kconfig"
1333 source "board/freescale/mpc8569mds/Kconfig"
1334 source "board/freescale/mpc8572ds/Kconfig"
1335 source "board/freescale/p1010rdb/Kconfig"
1336 source "board/freescale/p1022ds/Kconfig"
1337 source "board/freescale/p1023rdb/Kconfig"
1338 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1339 source "board/freescale/p1_twr/Kconfig"
1340 source "board/freescale/p2041rdb/Kconfig"
1341 source "board/freescale/qemu-ppce500/Kconfig"
1342 source "board/freescale/t102xqds/Kconfig"
1343 source "board/freescale/t102xrdb/Kconfig"
1344 source "board/freescale/t1040qds/Kconfig"
1345 source "board/freescale/t104xrdb/Kconfig"
1346 source "board/freescale/t208xqds/Kconfig"
1347 source "board/freescale/t208xrdb/Kconfig"
1348 source "board/freescale/t4qds/Kconfig"
1349 source "board/freescale/t4rdb/Kconfig"
1350 source "board/gdsys/p1022/Kconfig"
1351 source "board/keymile/kmp204x/Kconfig"
1352 source "board/sbc8548/Kconfig"
1353 source "board/socrates/Kconfig"
1354 source "board/varisys/cyrus/Kconfig"
1355 source "board/xes/xpedite520x/Kconfig"
1356 source "board/xes/xpedite537x/Kconfig"
1357 source "board/xes/xpedite550x/Kconfig"
1358 source "board/Arcturus/ucp1020/Kconfig"