8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_B4420QDS
28 bool "Support B4420QDS"
34 config TARGET_B4860QDS
35 bool "Support B4860QDS"
37 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 select FSL_DDR_INTERACTIVE if !SPL_BUILD
43 config TARGET_BSC9131RDB
44 bool "Support BSC9131RDB"
47 select BOARD_EARLY_INIT_F
49 config TARGET_BSC9132QDS
50 bool "Support BSC9132QDS"
52 select BOARD_LATE_INIT if CHAIN_OF_TRUST
54 select BOARD_EARLY_INIT_F
55 select FSL_DDR_INTERACTIVE
57 config TARGET_C29XPCIE
58 bool "Support C29XPCIE"
60 select BOARD_LATE_INIT if CHAIN_OF_TRUST
67 bool "Support P3041DS"
70 select BOARD_LATE_INIT if CHAIN_OF_TRUST
75 bool "Support P4080DS"
78 select BOARD_LATE_INIT if CHAIN_OF_TRUST
83 bool "Support P5020DS"
86 select BOARD_LATE_INIT if CHAIN_OF_TRUST
91 bool "Support P5040DS"
94 select BOARD_LATE_INIT if CHAIN_OF_TRUST
98 config TARGET_MPC8536DS
99 bool "Support MPC8536DS"
101 # Use DDR3 controller with DDR2 DIMMs on this board
102 select SYS_FSL_DDRC_GEN3
106 config TARGET_MPC8541CDS
107 bool "Support MPC8541CDS"
110 config TARGET_MPC8544DS
111 bool "Support MPC8544DS"
115 config TARGET_MPC8548CDS
116 bool "Support MPC8548CDS"
119 config TARGET_MPC8555CDS
120 bool "Support MPC8555CDS"
123 config TARGET_MPC8568MDS
124 bool "Support MPC8568MDS"
127 config TARGET_MPC8569MDS
128 bool "Support MPC8569MDS"
131 config TARGET_MPC8572DS
132 bool "Support MPC8572DS"
134 # Use DDR3 controller with DDR2 DIMMs on this board
135 select SYS_FSL_DDRC_GEN3
139 config TARGET_P1010RDB_PA
140 bool "Support P1010RDB_PA"
142 select BOARD_LATE_INIT if CHAIN_OF_TRUST
149 config TARGET_P1010RDB_PB
150 bool "Support P1010RDB_PB"
152 select BOARD_LATE_INIT if CHAIN_OF_TRUST
159 config TARGET_P1022DS
160 bool "Support P1022DS"
167 config TARGET_P1023RDB
168 bool "Support P1023RDB"
170 select FSL_DDR_INTERACTIVE
174 config TARGET_P1020MBG
175 bool "Support P1020MBG-PC"
183 config TARGET_P1020RDB_PC
184 bool "Support P1020RDB-PC"
192 config TARGET_P1020RDB_PD
193 bool "Support P1020RDB-PD"
201 config TARGET_P1020UTM
202 bool "Support P1020UTM"
210 config TARGET_P1021RDB
211 bool "Support P1021RDB"
219 config TARGET_P1024RDB
220 bool "Support P1024RDB"
228 config TARGET_P1025RDB
229 bool "Support P1025RDB"
237 config TARGET_P2020RDB
238 bool "Support P2020RDB-PC"
247 bool "Support p1_twr"
250 config TARGET_P2041RDB
251 bool "Support P2041RDB"
253 select BOARD_LATE_INIT if CHAIN_OF_TRUST
258 config TARGET_QEMU_PPCE500
259 bool "Support qemu-ppce500"
260 select ARCH_QEMU_E500
263 config TARGET_T1024QDS
264 bool "Support T1024QDS"
266 select BOARD_LATE_INIT if CHAIN_OF_TRUST
273 config TARGET_T1023RDB
274 bool "Support T1023RDB"
276 select BOARD_LATE_INIT if CHAIN_OF_TRUST
279 select FSL_DDR_INTERACTIVE
283 config TARGET_T1024RDB
284 bool "Support T1024RDB"
286 select BOARD_LATE_INIT if CHAIN_OF_TRUST
289 select FSL_DDR_INTERACTIVE
293 config TARGET_T1040QDS
294 bool "Support T1040QDS"
296 select BOARD_LATE_INIT if CHAIN_OF_TRUST
298 select FSL_DDR_INTERACTIVE
303 config TARGET_T1040RDB
304 bool "Support T1040RDB"
306 select BOARD_LATE_INIT if CHAIN_OF_TRUST
312 config TARGET_T1040D4RDB
313 bool "Support T1040D4RDB"
315 select BOARD_LATE_INIT if CHAIN_OF_TRUST
321 config TARGET_T1042RDB
322 bool "Support T1042RDB"
324 select BOARD_LATE_INIT if CHAIN_OF_TRUST
329 config TARGET_T1042D4RDB
330 bool "Support T1042D4RDB"
332 select BOARD_LATE_INIT if CHAIN_OF_TRUST
338 config TARGET_T1042RDB_PI
339 bool "Support T1042RDB_PI"
341 select BOARD_LATE_INIT if CHAIN_OF_TRUST
347 config TARGET_T2080QDS
348 bool "Support T2080QDS"
350 select BOARD_LATE_INIT if CHAIN_OF_TRUST
353 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
354 select FSL_DDR_INTERACTIVE
356 config TARGET_T2080RDB
357 bool "Support T2080RDB"
359 select BOARD_LATE_INIT if CHAIN_OF_TRUST
366 config TARGET_T2081QDS
367 bool "Support T2081QDS"
371 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
372 select FSL_DDR_INTERACTIVE
374 config TARGET_T4160QDS
375 bool "Support T4160QDS"
377 select BOARD_LATE_INIT if CHAIN_OF_TRUST
383 config TARGET_T4160RDB
384 bool "Support T4160RDB"
390 config TARGET_T4240QDS
391 bool "Support T4240QDS"
393 select BOARD_LATE_INIT if CHAIN_OF_TRUST
396 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
400 config TARGET_T4240RDB
401 bool "Support T4240RDB"
405 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
409 config TARGET_CONTROLCENTERD
410 bool "Support controlcenterd"
413 config TARGET_KMP204X
414 bool "Support kmp204x"
417 select FSL_DDR_INTERACTIVE
421 config TARGET_XPEDITE520X
422 bool "Support xpedite520x"
425 config TARGET_XPEDITE537X
426 bool "Support xpedite537x"
428 # Use DDR3 controller with DDR2 DIMMs on this board
429 select SYS_FSL_DDRC_GEN3
431 config TARGET_XPEDITE550X
432 bool "Support xpedite550x"
435 config TARGET_UCP1020
436 bool "Support uCP1020"
441 config TARGET_CYRUS_P5020
442 bool "Support Varisys Cyrus P5020"
447 config TARGET_CYRUS_P5040
448 bool "Support Varisys Cyrus P5040"
460 select SYS_FSL_DDR_VER_47
461 select SYS_FSL_ERRATUM_A004477
462 select SYS_FSL_ERRATUM_A005871
463 select SYS_FSL_ERRATUM_A006379
464 select SYS_FSL_ERRATUM_A006384
465 select SYS_FSL_ERRATUM_A006475
466 select SYS_FSL_ERRATUM_A006593
467 select SYS_FSL_ERRATUM_A007075
468 select SYS_FSL_ERRATUM_A007186
469 select SYS_FSL_ERRATUM_A007212
470 select SYS_FSL_ERRATUM_A009942
471 select SYS_FSL_HAS_DDR3
472 select SYS_FSL_HAS_SEC
473 select SYS_FSL_QORIQ_CHASSIS2
474 select SYS_FSL_SEC_BE
475 select SYS_FSL_SEC_COMPAT_4
487 select SYS_FSL_DDR_VER_47
488 select SYS_FSL_ERRATUM_A004477
489 select SYS_FSL_ERRATUM_A005871
490 select SYS_FSL_ERRATUM_A006379
491 select SYS_FSL_ERRATUM_A006384
492 select SYS_FSL_ERRATUM_A006475
493 select SYS_FSL_ERRATUM_A006593
494 select SYS_FSL_ERRATUM_A007075
495 select SYS_FSL_ERRATUM_A007186
496 select SYS_FSL_ERRATUM_A007212
497 select SYS_FSL_ERRATUM_A007907
498 select SYS_FSL_ERRATUM_A009942
499 select SYS_FSL_HAS_DDR3
500 select SYS_FSL_HAS_SEC
501 select SYS_FSL_QORIQ_CHASSIS2
502 select SYS_FSL_SEC_BE
503 select SYS_FSL_SEC_COMPAT_4
513 select SYS_FSL_DDR_VER_44
514 select SYS_FSL_ERRATUM_A004477
515 select SYS_FSL_ERRATUM_A005125
516 select SYS_FSL_ERRATUM_ESDHC111
517 select SYS_FSL_HAS_DDR3
518 select SYS_FSL_HAS_SEC
519 select SYS_FSL_SEC_BE
520 select SYS_FSL_SEC_COMPAT_4
529 select SYS_FSL_DDR_VER_46
530 select SYS_FSL_ERRATUM_A004477
531 select SYS_FSL_ERRATUM_A005125
532 select SYS_FSL_ERRATUM_A005434
533 select SYS_FSL_ERRATUM_ESDHC111
534 select SYS_FSL_ERRATUM_I2C_A004447
535 select SYS_FSL_ERRATUM_IFC_A002769
536 select SYS_FSL_HAS_DDR3
537 select SYS_FSL_HAS_SEC
538 select SYS_FSL_SEC_BE
539 select SYS_FSL_SEC_COMPAT_4
540 select SYS_PPC_E500_USE_DEBUG_TLB
551 select SYS_FSL_DDR_VER_46
552 select SYS_FSL_ERRATUM_A005125
553 select SYS_FSL_ERRATUM_ESDHC111
554 select SYS_FSL_HAS_DDR3
555 select SYS_FSL_HAS_SEC
556 select SYS_FSL_SEC_BE
557 select SYS_FSL_SEC_COMPAT_6
558 select SYS_PPC_E500_USE_DEBUG_TLB
567 select SYS_FSL_ERRATUM_A004508
568 select SYS_FSL_ERRATUM_A005125
569 select SYS_FSL_HAS_DDR2
570 select SYS_FSL_HAS_DDR3
571 select SYS_FSL_HAS_SEC
572 select SYS_FSL_SEC_BE
573 select SYS_FSL_SEC_COMPAT_2
574 select SYS_PPC_E500_USE_DEBUG_TLB
583 select SYS_FSL_HAS_DDR1
588 select SYS_FSL_HAS_DDR1
589 select SYS_FSL_HAS_SEC
590 select SYS_FSL_SEC_BE
591 select SYS_FSL_SEC_COMPAT_2
596 select SYS_FSL_ERRATUM_A005125
597 select SYS_FSL_HAS_DDR2
598 select SYS_FSL_HAS_SEC
599 select SYS_FSL_SEC_BE
600 select SYS_FSL_SEC_COMPAT_2
601 select SYS_PPC_E500_USE_DEBUG_TLB
607 select SYS_FSL_ERRATUM_A005125
608 select SYS_FSL_ERRATUM_NMG_DDR120
609 select SYS_FSL_ERRATUM_NMG_LBC103
610 select SYS_FSL_ERRATUM_NMG_ETSEC129
611 select SYS_FSL_ERRATUM_I2C_A004447
612 select SYS_FSL_HAS_DDR2
613 select SYS_FSL_HAS_DDR1
614 select SYS_FSL_HAS_SEC
615 select SYS_FSL_SEC_BE
616 select SYS_FSL_SEC_COMPAT_2
617 select SYS_PPC_E500_USE_DEBUG_TLB
623 select SYS_FSL_HAS_DDR1
624 select SYS_FSL_HAS_SEC
625 select SYS_FSL_SEC_BE
626 select SYS_FSL_SEC_COMPAT_2
631 select SYS_FSL_HAS_DDR1
636 select SYS_FSL_HAS_DDR2
637 select SYS_FSL_HAS_SEC
638 select SYS_FSL_SEC_BE
639 select SYS_FSL_SEC_COMPAT_2
644 select SYS_FSL_ERRATUM_A004508
645 select SYS_FSL_ERRATUM_A005125
646 select SYS_FSL_HAS_DDR3
647 select SYS_FSL_HAS_SEC
648 select SYS_FSL_SEC_BE
649 select SYS_FSL_SEC_COMPAT_2
656 select SYS_FSL_ERRATUM_A004508
657 select SYS_FSL_ERRATUM_A005125
658 select SYS_FSL_ERRATUM_DDR_115
659 select SYS_FSL_ERRATUM_DDR111_DDR134
660 select SYS_FSL_HAS_DDR2
661 select SYS_FSL_HAS_DDR3
662 select SYS_FSL_HAS_SEC
663 select SYS_FSL_SEC_BE
664 select SYS_FSL_SEC_COMPAT_2
665 select SYS_PPC_E500_USE_DEBUG_TLB
672 select SYS_FSL_ERRATUM_A004477
673 select SYS_FSL_ERRATUM_A004508
674 select SYS_FSL_ERRATUM_A005125
675 select SYS_FSL_ERRATUM_A005275
676 select SYS_FSL_ERRATUM_A006261
677 select SYS_FSL_ERRATUM_A007075
678 select SYS_FSL_ERRATUM_ESDHC111
679 select SYS_FSL_ERRATUM_I2C_A004447
680 select SYS_FSL_ERRATUM_IFC_A002769
681 select SYS_FSL_ERRATUM_P1010_A003549
682 select SYS_FSL_ERRATUM_SEC_A003571
683 select SYS_FSL_ERRATUM_IFC_A003399
684 select SYS_FSL_HAS_DDR3
685 select SYS_FSL_HAS_SEC
686 select SYS_FSL_SEC_BE
687 select SYS_FSL_SEC_COMPAT_4
688 select SYS_PPC_E500_USE_DEBUG_TLB
701 select SYS_FSL_ERRATUM_A004508
702 select SYS_FSL_ERRATUM_A005125
703 select SYS_FSL_ERRATUM_ELBC_A001
704 select SYS_FSL_ERRATUM_ESDHC111
705 select FSL_PCIE_DISABLE_ASPM
706 select SYS_FSL_HAS_DDR3
707 select SYS_FSL_HAS_SEC
708 select SYS_FSL_SEC_BE
709 select SYS_FSL_SEC_COMPAT_2
710 select SYS_PPC_E500_USE_DEBUG_TLB
716 select SYS_FSL_ERRATUM_A004508
717 select SYS_FSL_ERRATUM_A005125
718 select SYS_FSL_ERRATUM_ELBC_A001
719 select SYS_FSL_ERRATUM_ESDHC111
720 select FSL_PCIE_DISABLE_ASPM
721 select SYS_FSL_HAS_DDR3
722 select SYS_FSL_HAS_SEC
723 select SYS_FSL_SEC_BE
724 select SYS_FSL_SEC_COMPAT_2
725 select SYS_PPC_E500_USE_DEBUG_TLB
736 select SYS_FSL_ERRATUM_A004508
737 select SYS_FSL_ERRATUM_A005125
738 select SYS_FSL_ERRATUM_ELBC_A001
739 select SYS_FSL_ERRATUM_ESDHC111
740 select FSL_PCIE_DISABLE_ASPM
741 select SYS_FSL_HAS_DDR3
742 select SYS_FSL_HAS_SEC
743 select SYS_FSL_SEC_BE
744 select SYS_FSL_SEC_COMPAT_2
745 select SYS_PPC_E500_USE_DEBUG_TLB
756 select SYS_FSL_ERRATUM_A004477
757 select SYS_FSL_ERRATUM_A004508
758 select SYS_FSL_ERRATUM_A005125
759 select SYS_FSL_ERRATUM_ELBC_A001
760 select SYS_FSL_ERRATUM_ESDHC111
761 select SYS_FSL_ERRATUM_SATA_A001
762 select SYS_FSL_HAS_DDR3
763 select SYS_FSL_HAS_SEC
764 select SYS_FSL_SEC_BE
765 select SYS_FSL_SEC_COMPAT_2
766 select SYS_PPC_E500_USE_DEBUG_TLB
772 select SYS_FSL_ERRATUM_A004508
773 select SYS_FSL_ERRATUM_A005125
774 select SYS_FSL_ERRATUM_I2C_A004447
775 select SYS_FSL_HAS_DDR3
776 select SYS_FSL_HAS_SEC
777 select SYS_FSL_SEC_BE
778 select SYS_FSL_SEC_COMPAT_4
784 select SYS_FSL_ERRATUM_A004508
785 select SYS_FSL_ERRATUM_A005125
786 select SYS_FSL_ERRATUM_ELBC_A001
787 select SYS_FSL_ERRATUM_ESDHC111
788 select FSL_PCIE_DISABLE_ASPM
789 select SYS_FSL_HAS_DDR3
790 select SYS_FSL_HAS_SEC
791 select SYS_FSL_SEC_BE
792 select SYS_FSL_SEC_COMPAT_2
793 select SYS_PPC_E500_USE_DEBUG_TLB
805 select SYS_FSL_ERRATUM_A004508
806 select SYS_FSL_ERRATUM_A005125
807 select SYS_FSL_ERRATUM_ELBC_A001
808 select SYS_FSL_ERRATUM_ESDHC111
809 select FSL_PCIE_DISABLE_ASPM
810 select SYS_FSL_HAS_DDR3
811 select SYS_FSL_HAS_SEC
812 select SYS_FSL_SEC_BE
813 select SYS_FSL_SEC_COMPAT_2
814 select SYS_PPC_E500_USE_DEBUG_TLB
822 select SYS_FSL_ERRATUM_A004477
823 select SYS_FSL_ERRATUM_A004508
824 select SYS_FSL_ERRATUM_A005125
825 select SYS_FSL_ERRATUM_ESDHC111
826 select SYS_FSL_ERRATUM_ESDHC_A001
827 select SYS_FSL_HAS_DDR3
828 select SYS_FSL_HAS_SEC
829 select SYS_FSL_SEC_BE
830 select SYS_FSL_SEC_COMPAT_2
831 select SYS_PPC_E500_USE_DEBUG_TLB
841 select SYS_FSL_ERRATUM_A004510
842 select SYS_FSL_ERRATUM_A004849
843 select SYS_FSL_ERRATUM_A005275
844 select SYS_FSL_ERRATUM_A006261
845 select SYS_FSL_ERRATUM_CPU_A003999
846 select SYS_FSL_ERRATUM_DDR_A003
847 select SYS_FSL_ERRATUM_DDR_A003474
848 select SYS_FSL_ERRATUM_ESDHC111
849 select SYS_FSL_ERRATUM_I2C_A004447
850 select SYS_FSL_ERRATUM_NMG_CPU_A011
851 select SYS_FSL_ERRATUM_SRIO_A004034
852 select SYS_FSL_ERRATUM_USB14
853 select SYS_FSL_HAS_DDR3
854 select SYS_FSL_HAS_SEC
855 select SYS_FSL_QORIQ_CHASSIS1
856 select SYS_FSL_SEC_BE
857 select SYS_FSL_SEC_COMPAT_4
865 select SYS_FSL_DDR_VER_44
866 select SYS_FSL_ERRATUM_A004510
867 select SYS_FSL_ERRATUM_A004849
868 select SYS_FSL_ERRATUM_A005275
869 select SYS_FSL_ERRATUM_A005812
870 select SYS_FSL_ERRATUM_A006261
871 select SYS_FSL_ERRATUM_CPU_A003999
872 select SYS_FSL_ERRATUM_DDR_A003
873 select SYS_FSL_ERRATUM_DDR_A003474
874 select SYS_FSL_ERRATUM_ESDHC111
875 select SYS_FSL_ERRATUM_I2C_A004447
876 select SYS_FSL_ERRATUM_NMG_CPU_A011
877 select SYS_FSL_ERRATUM_SRIO_A004034
878 select SYS_FSL_ERRATUM_USB14
879 select SYS_FSL_HAS_DDR3
880 select SYS_FSL_HAS_SEC
881 select SYS_FSL_QORIQ_CHASSIS1
882 select SYS_FSL_SEC_BE
883 select SYS_FSL_SEC_COMPAT_4
894 select SYS_FSL_DDR_VER_44
895 select SYS_FSL_ERRATUM_A004510
896 select SYS_FSL_ERRATUM_A004580
897 select SYS_FSL_ERRATUM_A004849
898 select SYS_FSL_ERRATUM_A005812
899 select SYS_FSL_ERRATUM_A007075
900 select SYS_FSL_ERRATUM_CPC_A002
901 select SYS_FSL_ERRATUM_CPC_A003
902 select SYS_FSL_ERRATUM_CPU_A003999
903 select SYS_FSL_ERRATUM_DDR_A003
904 select SYS_FSL_ERRATUM_DDR_A003474
905 select SYS_FSL_ERRATUM_ELBC_A001
906 select SYS_FSL_ERRATUM_ESDHC111
907 select SYS_FSL_ERRATUM_ESDHC13
908 select SYS_FSL_ERRATUM_ESDHC135
909 select SYS_FSL_ERRATUM_I2C_A004447
910 select SYS_FSL_ERRATUM_NMG_CPU_A011
911 select SYS_FSL_ERRATUM_SRIO_A004034
912 select SYS_P4080_ERRATUM_CPU22
913 select SYS_P4080_ERRATUM_PCIE_A003
914 select SYS_P4080_ERRATUM_SERDES8
915 select SYS_P4080_ERRATUM_SERDES9
916 select SYS_P4080_ERRATUM_SERDES_A001
917 select SYS_P4080_ERRATUM_SERDES_A005
918 select SYS_FSL_HAS_DDR3
919 select SYS_FSL_HAS_SEC
920 select SYS_FSL_QORIQ_CHASSIS1
921 select SYS_FSL_SEC_BE
922 select SYS_FSL_SEC_COMPAT_4
932 select SYS_FSL_DDR_VER_44
933 select SYS_FSL_ERRATUM_A004510
934 select SYS_FSL_ERRATUM_A005275
935 select SYS_FSL_ERRATUM_A006261
936 select SYS_FSL_ERRATUM_DDR_A003
937 select SYS_FSL_ERRATUM_DDR_A003474
938 select SYS_FSL_ERRATUM_ESDHC111
939 select SYS_FSL_ERRATUM_I2C_A004447
940 select SYS_FSL_ERRATUM_SRIO_A004034
941 select SYS_FSL_ERRATUM_USB14
942 select SYS_FSL_HAS_DDR3
943 select SYS_FSL_HAS_SEC
944 select SYS_FSL_QORIQ_CHASSIS1
945 select SYS_FSL_SEC_BE
946 select SYS_FSL_SEC_COMPAT_4
957 select SYS_FSL_DDR_VER_44
958 select SYS_FSL_ERRATUM_A004510
959 select SYS_FSL_ERRATUM_A004699
960 select SYS_FSL_ERRATUM_A005275
961 select SYS_FSL_ERRATUM_A005812
962 select SYS_FSL_ERRATUM_A006261
963 select SYS_FSL_ERRATUM_DDR_A003
964 select SYS_FSL_ERRATUM_DDR_A003474
965 select SYS_FSL_ERRATUM_ESDHC111
966 select SYS_FSL_ERRATUM_USB14
967 select SYS_FSL_HAS_DDR3
968 select SYS_FSL_HAS_SEC
969 select SYS_FSL_QORIQ_CHASSIS1
970 select SYS_FSL_SEC_BE
971 select SYS_FSL_SEC_COMPAT_4
978 config ARCH_QEMU_E500
985 select SYS_FSL_DDR_VER_50
986 select SYS_FSL_ERRATUM_A008378
987 select SYS_FSL_ERRATUM_A009663
988 select SYS_FSL_ERRATUM_A009942
989 select SYS_FSL_ERRATUM_ESDHC111
990 select SYS_FSL_HAS_DDR3
991 select SYS_FSL_HAS_DDR4
992 select SYS_FSL_HAS_SEC
993 select SYS_FSL_QORIQ_CHASSIS2
994 select SYS_FSL_SEC_BE
995 select SYS_FSL_SEC_COMPAT_5
1005 select SYS_FSL_DDR_VER_50
1006 select SYS_FSL_ERRATUM_A008378
1007 select SYS_FSL_ERRATUM_A009663
1008 select SYS_FSL_ERRATUM_A009942
1009 select SYS_FSL_ERRATUM_ESDHC111
1010 select SYS_FSL_HAS_DDR3
1011 select SYS_FSL_HAS_DDR4
1012 select SYS_FSL_HAS_SEC
1013 select SYS_FSL_QORIQ_CHASSIS2
1014 select SYS_FSL_SEC_BE
1015 select SYS_FSL_SEC_COMPAT_5
1026 select SYS_FSL_DDR_VER_50
1027 select SYS_FSL_ERRATUM_A008044
1028 select SYS_FSL_ERRATUM_A008378
1029 select SYS_FSL_ERRATUM_A009663
1030 select SYS_FSL_ERRATUM_A009942
1031 select SYS_FSL_ERRATUM_ESDHC111
1032 select SYS_FSL_HAS_DDR3
1033 select SYS_FSL_HAS_DDR4
1034 select SYS_FSL_HAS_SEC
1035 select SYS_FSL_QORIQ_CHASSIS2
1036 select SYS_FSL_SEC_BE
1037 select SYS_FSL_SEC_COMPAT_5
1049 select SYS_FSL_DDR_VER_50
1050 select SYS_FSL_ERRATUM_A008044
1051 select SYS_FSL_ERRATUM_A008378
1052 select SYS_FSL_ERRATUM_A009663
1053 select SYS_FSL_ERRATUM_A009942
1054 select SYS_FSL_ERRATUM_ESDHC111
1055 select SYS_FSL_HAS_DDR3
1056 select SYS_FSL_HAS_DDR4
1057 select SYS_FSL_HAS_SEC
1058 select SYS_FSL_QORIQ_CHASSIS2
1059 select SYS_FSL_SEC_BE
1060 select SYS_FSL_SEC_COMPAT_5
1073 select SYS_FSL_DDR_VER_47
1074 select SYS_FSL_ERRATUM_A006379
1075 select SYS_FSL_ERRATUM_A006593
1076 select SYS_FSL_ERRATUM_A007186
1077 select SYS_FSL_ERRATUM_A007212
1078 select SYS_FSL_ERRATUM_A007815
1079 select SYS_FSL_ERRATUM_A007907
1080 select SYS_FSL_ERRATUM_A009942
1081 select SYS_FSL_ERRATUM_ESDHC111
1082 select SYS_FSL_HAS_DDR3
1083 select SYS_FSL_HAS_SEC
1084 select SYS_FSL_QORIQ_CHASSIS2
1085 select SYS_FSL_SEC_BE
1086 select SYS_FSL_SEC_COMPAT_4
1097 select SYS_FSL_DDR_VER_47
1098 select SYS_FSL_ERRATUM_A006379
1099 select SYS_FSL_ERRATUM_A006593
1100 select SYS_FSL_ERRATUM_A007186
1101 select SYS_FSL_ERRATUM_A007212
1102 select SYS_FSL_ERRATUM_A009942
1103 select SYS_FSL_ERRATUM_ESDHC111
1104 select SYS_FSL_HAS_DDR3
1105 select SYS_FSL_HAS_SEC
1106 select SYS_FSL_QORIQ_CHASSIS2
1107 select SYS_FSL_SEC_BE
1108 select SYS_FSL_SEC_COMPAT_4
1119 select SYS_FSL_DDR_VER_47
1120 select SYS_FSL_ERRATUM_A004468
1121 select SYS_FSL_ERRATUM_A005871
1122 select SYS_FSL_ERRATUM_A006379
1123 select SYS_FSL_ERRATUM_A006593
1124 select SYS_FSL_ERRATUM_A007186
1125 select SYS_FSL_ERRATUM_A007798
1126 select SYS_FSL_ERRATUM_A009942
1127 select SYS_FSL_HAS_DDR3
1128 select SYS_FSL_HAS_SEC
1129 select SYS_FSL_QORIQ_CHASSIS2
1130 select SYS_FSL_SEC_BE
1131 select SYS_FSL_SEC_COMPAT_4
1144 select SYS_FSL_DDR_VER_47
1145 select SYS_FSL_ERRATUM_A004468
1146 select SYS_FSL_ERRATUM_A005871
1147 select SYS_FSL_ERRATUM_A006261
1148 select SYS_FSL_ERRATUM_A006379
1149 select SYS_FSL_ERRATUM_A006593
1150 select SYS_FSL_ERRATUM_A007186
1151 select SYS_FSL_ERRATUM_A007798
1152 select SYS_FSL_ERRATUM_A007815
1153 select SYS_FSL_ERRATUM_A007907
1154 select SYS_FSL_ERRATUM_A009942
1155 select SYS_FSL_HAS_DDR3
1156 select SYS_FSL_HAS_SEC
1157 select SYS_FSL_QORIQ_CHASSIS2
1158 select SYS_FSL_SEC_BE
1159 select SYS_FSL_SEC_COMPAT_4
1167 config MPC85XX_HAVE_RESET_VECTOR
1168 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1179 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1185 Enble PowerPC E500MC core
1190 Enable PowerPC E6500 core
1195 Use Freescale common code for Local Access Window
1200 Enable Freescale Secure Boot feature. Normally selected
1201 by defconfig. If unsure, do not change.
1204 int "Maximum number of CPUs permitted for MPC85xx"
1205 default 12 if ARCH_T4240
1206 default 8 if ARCH_P4080 || \
1208 default 4 if ARCH_B4860 || \
1216 default 2 if ARCH_B4420 || \
1231 Set this number to the maximum number of possible CPUs in the SoC.
1232 SoCs may have multiple clusters with each cluster may have multiple
1233 ports. If some ports are reserved but higher ports are used for
1234 cores, count the reserved ports. This will allocate enough memory
1235 in spin table to properly handle all cores.
1237 config SYS_CCSRBAR_DEFAULT
1238 hex "Default CCSRBAR address"
1239 default 0xff700000 if ARCH_BSC9131 || \
1260 default 0xff600000 if ARCH_P1023
1261 default 0xfe000000 if ARCH_B4420 || \
1276 default 0xe0000000 if ARCH_QEMU_E500
1278 Default value of CCSRBAR comes from power-on-reset. It
1279 is fixed on each SoC. Some SoCs can have different value
1280 if changed by pre-boot regime. The value here must match
1281 the current value in SoC. If not sure, do not change.
1283 config SYS_FSL_ERRATUM_A004468
1286 config SYS_FSL_ERRATUM_A004477
1289 config SYS_FSL_ERRATUM_A004508
1292 config SYS_FSL_ERRATUM_A004580
1295 config SYS_FSL_ERRATUM_A004699
1298 config SYS_FSL_ERRATUM_A004849
1301 config SYS_FSL_ERRATUM_A004510
1304 config SYS_FSL_ERRATUM_A004510_SVR_REV
1306 depends on SYS_FSL_ERRATUM_A004510
1307 default 0x20 if ARCH_P4080
1310 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1312 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1315 config SYS_FSL_ERRATUM_A005125
1318 config SYS_FSL_ERRATUM_A005434
1321 config SYS_FSL_ERRATUM_A005812
1324 config SYS_FSL_ERRATUM_A005871
1327 config SYS_FSL_ERRATUM_A005275
1330 config SYS_FSL_ERRATUM_A006261
1333 config SYS_FSL_ERRATUM_A006379
1336 config SYS_FSL_ERRATUM_A006384
1339 config SYS_FSL_ERRATUM_A006475
1342 config SYS_FSL_ERRATUM_A006593
1345 config SYS_FSL_ERRATUM_A007075
1348 config SYS_FSL_ERRATUM_A007186
1351 config SYS_FSL_ERRATUM_A007212
1354 config SYS_FSL_ERRATUM_A007815
1357 config SYS_FSL_ERRATUM_A007798
1360 config SYS_FSL_ERRATUM_A007907
1363 config SYS_FSL_ERRATUM_A008044
1366 config SYS_FSL_ERRATUM_CPC_A002
1369 config SYS_FSL_ERRATUM_CPC_A003
1372 config SYS_FSL_ERRATUM_CPU_A003999
1375 config SYS_FSL_ERRATUM_ELBC_A001
1378 config SYS_FSL_ERRATUM_I2C_A004447
1381 config SYS_FSL_A004447_SVR_REV
1383 depends on SYS_FSL_ERRATUM_I2C_A004447
1384 default 0x00 if ARCH_MPC8548
1385 default 0x10 if ARCH_P1010
1386 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1387 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1389 config SYS_FSL_ERRATUM_IFC_A002769
1392 config SYS_FSL_ERRATUM_IFC_A003399
1395 config SYS_FSL_ERRATUM_NMG_CPU_A011
1398 config SYS_FSL_ERRATUM_NMG_ETSEC129
1401 config SYS_FSL_ERRATUM_NMG_LBC103
1404 config SYS_FSL_ERRATUM_P1010_A003549
1407 config SYS_FSL_ERRATUM_SATA_A001
1410 config SYS_FSL_ERRATUM_SEC_A003571
1413 config SYS_FSL_ERRATUM_SRIO_A004034
1416 config SYS_FSL_ERRATUM_USB14
1419 config SYS_P4080_ERRATUM_CPU22
1422 config SYS_P4080_ERRATUM_PCIE_A003
1425 config SYS_P4080_ERRATUM_SERDES8
1428 config SYS_P4080_ERRATUM_SERDES9
1431 config SYS_P4080_ERRATUM_SERDES_A001
1434 config SYS_P4080_ERRATUM_SERDES_A005
1437 config FSL_PCIE_DISABLE_ASPM
1440 config SYS_FSL_QORIQ_CHASSIS1
1443 config SYS_FSL_QORIQ_CHASSIS2
1446 config SYS_FSL_NUM_LAWS
1447 int "Number of local access windows"
1449 default 32 if ARCH_B4420 || \
1460 default 16 if ARCH_T1023 || \
1464 default 12 if ARCH_BSC9131 || \
1478 default 10 if ARCH_MPC8544 || \
1482 default 8 if ARCH_MPC8540 || \
1487 Number of local access windows. This is fixed per SoC.
1488 If not sure, do not change.
1490 config SYS_FSL_THREADS_PER_CORE
1495 config SYS_NUM_TLBCAMS
1496 int "Number of TLB CAM entries"
1497 default 64 if E500MC
1500 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1501 16 for other E500 SoCs.
1506 config SYS_PPC_E500_USE_DEBUG_TLB
1515 config SYS_PPC_E500_DEBUG_TLB
1516 int "Temporary TLB entry for external debugger"
1517 depends on SYS_PPC_E500_USE_DEBUG_TLB
1518 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1519 default 1 if ARCH_MPC8536
1520 default 2 if ARCH_MPC8572 || \
1528 default 3 if ARCH_P1010 || \
1532 Select a temporary TLB entry to be used during boot to work
1533 around limitations in e500v1 and e500v2 external debugger
1534 support. This reduces the portions of the boot code where
1535 breakpoints and single stepping do not work. The value of this
1536 symbol should be set to the TLB1 entry to be used for this
1537 purpose. If unsure, do not change.
1539 config SYS_FSL_IFC_CLK_DIV
1540 int "Divider of platform clock"
1542 default 2 if ARCH_B4420 || \
1552 Defines divider of platform clock(clock input to
1555 config SYS_FSL_LBC_CLK_DIV
1556 int "Divider of platform clock"
1557 depends on FSL_ELBC || ARCH_MPC8540 || \
1558 ARCH_MPC8548 || ARCH_MPC8541 || \
1559 ARCH_MPC8555 || ARCH_MPC8560 || \
1562 default 2 if ARCH_P2041 || \
1570 Defines divider of platform clock(clock input to
1573 source "board/freescale/b4860qds/Kconfig"
1574 source "board/freescale/bsc9131rdb/Kconfig"
1575 source "board/freescale/bsc9132qds/Kconfig"
1576 source "board/freescale/c29xpcie/Kconfig"
1577 source "board/freescale/corenet_ds/Kconfig"
1578 source "board/freescale/mpc8536ds/Kconfig"
1579 source "board/freescale/mpc8541cds/Kconfig"
1580 source "board/freescale/mpc8544ds/Kconfig"
1581 source "board/freescale/mpc8548cds/Kconfig"
1582 source "board/freescale/mpc8555cds/Kconfig"
1583 source "board/freescale/mpc8568mds/Kconfig"
1584 source "board/freescale/mpc8569mds/Kconfig"
1585 source "board/freescale/mpc8572ds/Kconfig"
1586 source "board/freescale/p1010rdb/Kconfig"
1587 source "board/freescale/p1022ds/Kconfig"
1588 source "board/freescale/p1023rdb/Kconfig"
1589 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1590 source "board/freescale/p1_twr/Kconfig"
1591 source "board/freescale/p2041rdb/Kconfig"
1592 source "board/freescale/qemu-ppce500/Kconfig"
1593 source "board/freescale/t102xqds/Kconfig"
1594 source "board/freescale/t102xrdb/Kconfig"
1595 source "board/freescale/t1040qds/Kconfig"
1596 source "board/freescale/t104xrdb/Kconfig"
1597 source "board/freescale/t208xqds/Kconfig"
1598 source "board/freescale/t208xrdb/Kconfig"
1599 source "board/freescale/t4qds/Kconfig"
1600 source "board/freescale/t4rdb/Kconfig"
1601 source "board/gdsys/p1022/Kconfig"
1602 source "board/keymile/kmp204x/Kconfig"
1603 source "board/sbc8548/Kconfig"
1604 source "board/socrates/Kconfig"
1605 source "board/varisys/cyrus/Kconfig"
1606 source "board/xes/xpedite520x/Kconfig"
1607 source "board/xes/xpedite537x/Kconfig"
1608 source "board/xes/xpedite550x/Kconfig"
1609 source "board/Arcturus/ucp1020/Kconfig"