8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_B4420QDS
28 bool "Support B4420QDS"
33 config TARGET_B4860QDS
34 bool "Support B4860QDS"
36 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 config TARGET_BSC9131RDB
41 bool "Support BSC9131RDB"
44 select BOARD_EARLY_INIT_F
46 config TARGET_BSC9132QDS
47 bool "Support BSC9132QDS"
49 select BOARD_LATE_INIT if CHAIN_OF_TRUST
51 select BOARD_EARLY_INIT_F
53 config TARGET_C29XPCIE
54 bool "Support C29XPCIE"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
62 bool "Support P3041DS"
65 select BOARD_LATE_INIT if CHAIN_OF_TRUST
68 bool "Support P4080DS"
71 select BOARD_LATE_INIT if CHAIN_OF_TRUST
74 bool "Support P5020DS"
77 select BOARD_LATE_INIT if CHAIN_OF_TRUST
80 bool "Support P5040DS"
83 select BOARD_LATE_INIT if CHAIN_OF_TRUST
85 config TARGET_MPC8536DS
86 bool "Support MPC8536DS"
88 # Use DDR3 controller with DDR2 DIMMs on this board
89 select SYS_FSL_DDRC_GEN3
91 config TARGET_MPC8541CDS
92 bool "Support MPC8541CDS"
95 config TARGET_MPC8544DS
96 bool "Support MPC8544DS"
99 config TARGET_MPC8548CDS
100 bool "Support MPC8548CDS"
103 config TARGET_MPC8555CDS
104 bool "Support MPC8555CDS"
107 config TARGET_MPC8568MDS
108 bool "Support MPC8568MDS"
111 config TARGET_MPC8569MDS
112 bool "Support MPC8569MDS"
115 config TARGET_MPC8572DS
116 bool "Support MPC8572DS"
118 # Use DDR3 controller with DDR2 DIMMs on this board
119 select SYS_FSL_DDRC_GEN3
121 config TARGET_P1010RDB_PA
122 bool "Support P1010RDB_PA"
124 select BOARD_LATE_INIT if CHAIN_OF_TRUST
129 config TARGET_P1010RDB_PB
130 bool "Support P1010RDB_PB"
132 select BOARD_LATE_INIT if CHAIN_OF_TRUST
137 config TARGET_P1022DS
138 bool "Support P1022DS"
143 config TARGET_P1023RDB
144 bool "Support P1023RDB"
148 config TARGET_P1020MBG
149 bool "Support P1020MBG-PC"
155 config TARGET_P1020RDB_PC
156 bool "Support P1020RDB-PC"
162 config TARGET_P1020RDB_PD
163 bool "Support P1020RDB-PD"
169 config TARGET_P1020UTM
170 bool "Support P1020UTM"
176 config TARGET_P1021RDB
177 bool "Support P1021RDB"
183 config TARGET_P1024RDB
184 bool "Support P1024RDB"
190 config TARGET_P1025RDB
191 bool "Support P1025RDB"
197 config TARGET_P2020RDB
198 bool "Support P2020RDB-PC"
205 bool "Support p1_twr"
208 config TARGET_P2041RDB
209 bool "Support P2041RDB"
211 select BOARD_LATE_INIT if CHAIN_OF_TRUST
214 config TARGET_QEMU_PPCE500
215 bool "Support qemu-ppce500"
216 select ARCH_QEMU_E500
219 config TARGET_T1024QDS
220 bool "Support T1024QDS"
222 select BOARD_LATE_INIT if CHAIN_OF_TRUST
227 config TARGET_T1023RDB
228 bool "Support T1023RDB"
230 select BOARD_LATE_INIT if CHAIN_OF_TRUST
235 config TARGET_T1024RDB
236 bool "Support T1024RDB"
238 select BOARD_LATE_INIT if CHAIN_OF_TRUST
243 config TARGET_T1040QDS
244 bool "Support T1040QDS"
246 select BOARD_LATE_INIT if CHAIN_OF_TRUST
250 config TARGET_T1040RDB
251 bool "Support T1040RDB"
253 select BOARD_LATE_INIT if CHAIN_OF_TRUST
257 config TARGET_T1040D4RDB
258 bool "Support T1040D4RDB"
260 select BOARD_LATE_INIT if CHAIN_OF_TRUST
264 config TARGET_T1042RDB
265 bool "Support T1042RDB"
267 select BOARD_LATE_INIT if CHAIN_OF_TRUST
271 config TARGET_T1042D4RDB
272 bool "Support T1042D4RDB"
274 select BOARD_LATE_INIT if CHAIN_OF_TRUST
278 config TARGET_T1042RDB_PI
279 bool "Support T1042RDB_PI"
281 select BOARD_LATE_INIT if CHAIN_OF_TRUST
285 config TARGET_T2080QDS
286 bool "Support T2080QDS"
288 select BOARD_LATE_INIT if CHAIN_OF_TRUST
292 config TARGET_T2080RDB
293 bool "Support T2080RDB"
295 select BOARD_LATE_INIT if CHAIN_OF_TRUST
299 config TARGET_T2081QDS
300 bool "Support T2081QDS"
305 config TARGET_T4160QDS
306 bool "Support T4160QDS"
308 select BOARD_LATE_INIT if CHAIN_OF_TRUST
312 config TARGET_T4160RDB
313 bool "Support T4160RDB"
318 config TARGET_T4240QDS
319 bool "Support T4240QDS"
321 select BOARD_LATE_INIT if CHAIN_OF_TRUST
325 config TARGET_T4240RDB
326 bool "Support T4240RDB"
331 config TARGET_CONTROLCENTERD
332 bool "Support controlcenterd"
335 config TARGET_KMP204X
336 bool "Support kmp204x"
342 config TARGET_XPEDITE520X
343 bool "Support xpedite520x"
346 config TARGET_XPEDITE537X
347 bool "Support xpedite537x"
349 # Use DDR3 controller with DDR2 DIMMs on this board
350 select SYS_FSL_DDRC_GEN3
352 config TARGET_XPEDITE550X
353 bool "Support xpedite550x"
356 config TARGET_UCP1020
357 bool "Support uCP1020"
360 config TARGET_CYRUS_P5020
361 bool "Support Varisys Cyrus P5020"
365 config TARGET_CYRUS_P5040
366 bool "Support Varisys Cyrus P5040"
377 select SYS_FSL_DDR_VER_47
378 select SYS_FSL_ERRATUM_A004477
379 select SYS_FSL_ERRATUM_A005871
380 select SYS_FSL_ERRATUM_A006379
381 select SYS_FSL_ERRATUM_A006384
382 select SYS_FSL_ERRATUM_A006475
383 select SYS_FSL_ERRATUM_A006593
384 select SYS_FSL_ERRATUM_A007075
385 select SYS_FSL_ERRATUM_A007186
386 select SYS_FSL_ERRATUM_A007212
387 select SYS_FSL_ERRATUM_A009942
388 select SYS_FSL_HAS_DDR3
389 select SYS_FSL_HAS_SEC
390 select SYS_FSL_QORIQ_CHASSIS2
391 select SYS_FSL_SEC_BE
392 select SYS_FSL_SEC_COMPAT_4
402 select SYS_FSL_DDR_VER_47
403 select SYS_FSL_ERRATUM_A004477
404 select SYS_FSL_ERRATUM_A005871
405 select SYS_FSL_ERRATUM_A006379
406 select SYS_FSL_ERRATUM_A006384
407 select SYS_FSL_ERRATUM_A006475
408 select SYS_FSL_ERRATUM_A006593
409 select SYS_FSL_ERRATUM_A007075
410 select SYS_FSL_ERRATUM_A007186
411 select SYS_FSL_ERRATUM_A007212
412 select SYS_FSL_ERRATUM_A007907
413 select SYS_FSL_ERRATUM_A009942
414 select SYS_FSL_HAS_DDR3
415 select SYS_FSL_HAS_SEC
416 select SYS_FSL_QORIQ_CHASSIS2
417 select SYS_FSL_SEC_BE
418 select SYS_FSL_SEC_COMPAT_4
426 select SYS_FSL_DDR_VER_44
427 select SYS_FSL_ERRATUM_A004477
428 select SYS_FSL_ERRATUM_A005125
429 select SYS_FSL_ERRATUM_ESDHC111
430 select SYS_FSL_HAS_DDR3
431 select SYS_FSL_HAS_SEC
432 select SYS_FSL_SEC_BE
433 select SYS_FSL_SEC_COMPAT_4
440 select SYS_FSL_DDR_VER_46
441 select SYS_FSL_ERRATUM_A004477
442 select SYS_FSL_ERRATUM_A005125
443 select SYS_FSL_ERRATUM_A005434
444 select SYS_FSL_ERRATUM_ESDHC111
445 select SYS_FSL_ERRATUM_I2C_A004447
446 select SYS_FSL_ERRATUM_IFC_A002769
447 select SYS_FSL_HAS_DDR3
448 select SYS_FSL_HAS_SEC
449 select SYS_FSL_SEC_BE
450 select SYS_FSL_SEC_COMPAT_4
451 select SYS_PPC_E500_USE_DEBUG_TLB
458 select SYS_FSL_DDR_VER_46
459 select SYS_FSL_ERRATUM_A005125
460 select SYS_FSL_ERRATUM_ESDHC111
461 select SYS_FSL_HAS_DDR3
462 select SYS_FSL_HAS_SEC
463 select SYS_FSL_SEC_BE
464 select SYS_FSL_SEC_COMPAT_6
465 select SYS_PPC_E500_USE_DEBUG_TLB
471 select SYS_FSL_ERRATUM_A004508
472 select SYS_FSL_ERRATUM_A005125
473 select SYS_FSL_HAS_DDR2
474 select SYS_FSL_HAS_DDR3
475 select SYS_FSL_HAS_SEC
476 select SYS_FSL_SEC_BE
477 select SYS_FSL_SEC_COMPAT_2
478 select SYS_PPC_E500_USE_DEBUG_TLB
484 select SYS_FSL_HAS_DDR1
489 select SYS_FSL_HAS_DDR1
490 select SYS_FSL_HAS_SEC
491 select SYS_FSL_SEC_BE
492 select SYS_FSL_SEC_COMPAT_2
497 select SYS_FSL_ERRATUM_A005125
498 select SYS_FSL_HAS_DDR2
499 select SYS_FSL_HAS_SEC
500 select SYS_FSL_SEC_BE
501 select SYS_FSL_SEC_COMPAT_2
502 select SYS_PPC_E500_USE_DEBUG_TLB
508 select SYS_FSL_ERRATUM_A005125
509 select SYS_FSL_ERRATUM_NMG_DDR120
510 select SYS_FSL_ERRATUM_NMG_LBC103
511 select SYS_FSL_ERRATUM_NMG_ETSEC129
512 select SYS_FSL_ERRATUM_I2C_A004447
513 select SYS_FSL_HAS_DDR2
514 select SYS_FSL_HAS_DDR1
515 select SYS_FSL_HAS_SEC
516 select SYS_FSL_SEC_BE
517 select SYS_FSL_SEC_COMPAT_2
518 select SYS_PPC_E500_USE_DEBUG_TLB
523 select SYS_FSL_HAS_DDR1
524 select SYS_FSL_HAS_SEC
525 select SYS_FSL_SEC_BE
526 select SYS_FSL_SEC_COMPAT_2
531 select SYS_FSL_HAS_DDR1
536 select SYS_FSL_HAS_DDR2
537 select SYS_FSL_HAS_SEC
538 select SYS_FSL_SEC_BE
539 select SYS_FSL_SEC_COMPAT_2
544 select SYS_FSL_ERRATUM_A004508
545 select SYS_FSL_ERRATUM_A005125
546 select SYS_FSL_HAS_DDR3
547 select SYS_FSL_HAS_SEC
548 select SYS_FSL_SEC_BE
549 select SYS_FSL_SEC_COMPAT_2
555 select SYS_FSL_ERRATUM_A004508
556 select SYS_FSL_ERRATUM_A005125
557 select SYS_FSL_ERRATUM_DDR_115
558 select SYS_FSL_ERRATUM_DDR111_DDR134
559 select SYS_FSL_HAS_DDR2
560 select SYS_FSL_HAS_DDR3
561 select SYS_FSL_HAS_SEC
562 select SYS_FSL_SEC_BE
563 select SYS_FSL_SEC_COMPAT_2
564 select SYS_PPC_E500_USE_DEBUG_TLB
570 select SYS_FSL_ERRATUM_A004477
571 select SYS_FSL_ERRATUM_A004508
572 select SYS_FSL_ERRATUM_A005125
573 select SYS_FSL_ERRATUM_A006261
574 select SYS_FSL_ERRATUM_A007075
575 select SYS_FSL_ERRATUM_ESDHC111
576 select SYS_FSL_ERRATUM_I2C_A004447
577 select SYS_FSL_ERRATUM_IFC_A002769
578 select SYS_FSL_ERRATUM_P1010_A003549
579 select SYS_FSL_ERRATUM_SEC_A003571
580 select SYS_FSL_ERRATUM_IFC_A003399
581 select SYS_FSL_HAS_DDR3
582 select SYS_FSL_HAS_SEC
583 select SYS_FSL_SEC_BE
584 select SYS_FSL_SEC_COMPAT_4
585 select SYS_PPC_E500_USE_DEBUG_TLB
592 select SYS_FSL_ERRATUM_A004508
593 select SYS_FSL_ERRATUM_A005125
594 select SYS_FSL_ERRATUM_ELBC_A001
595 select SYS_FSL_ERRATUM_ESDHC111
596 select SYS_FSL_HAS_DDR3
597 select SYS_FSL_HAS_SEC
598 select SYS_FSL_SEC_BE
599 select SYS_FSL_SEC_COMPAT_2
600 select SYS_PPC_E500_USE_DEBUG_TLB
606 select SYS_FSL_ERRATUM_A004508
607 select SYS_FSL_ERRATUM_A005125
608 select SYS_FSL_ERRATUM_ELBC_A001
609 select SYS_FSL_ERRATUM_ESDHC111
610 select SYS_FSL_HAS_DDR3
611 select SYS_FSL_HAS_SEC
612 select SYS_FSL_SEC_BE
613 select SYS_FSL_SEC_COMPAT_2
614 select SYS_PPC_E500_USE_DEBUG_TLB
620 select SYS_FSL_ERRATUM_A004508
621 select SYS_FSL_ERRATUM_A005125
622 select SYS_FSL_ERRATUM_ELBC_A001
623 select SYS_FSL_ERRATUM_ESDHC111
624 select SYS_FSL_HAS_DDR3
625 select SYS_FSL_HAS_SEC
626 select SYS_FSL_SEC_BE
627 select SYS_FSL_SEC_COMPAT_2
628 select SYS_PPC_E500_USE_DEBUG_TLB
634 select SYS_FSL_ERRATUM_A004477
635 select SYS_FSL_ERRATUM_A004508
636 select SYS_FSL_ERRATUM_A005125
637 select SYS_FSL_ERRATUM_ELBC_A001
638 select SYS_FSL_ERRATUM_ESDHC111
639 select SYS_FSL_ERRATUM_SATA_A001
640 select SYS_FSL_HAS_DDR3
641 select SYS_FSL_HAS_SEC
642 select SYS_FSL_SEC_BE
643 select SYS_FSL_SEC_COMPAT_2
644 select SYS_PPC_E500_USE_DEBUG_TLB
650 select SYS_FSL_ERRATUM_A004508
651 select SYS_FSL_ERRATUM_A005125
652 select SYS_FSL_ERRATUM_I2C_A004447
653 select SYS_FSL_HAS_DDR3
654 select SYS_FSL_HAS_SEC
655 select SYS_FSL_SEC_BE
656 select SYS_FSL_SEC_COMPAT_4
662 select SYS_FSL_ERRATUM_A004508
663 select SYS_FSL_ERRATUM_A005125
664 select SYS_FSL_ERRATUM_ELBC_A001
665 select SYS_FSL_ERRATUM_ESDHC111
666 select SYS_FSL_HAS_DDR3
667 select SYS_FSL_HAS_SEC
668 select SYS_FSL_SEC_BE
669 select SYS_FSL_SEC_COMPAT_2
670 select SYS_PPC_E500_USE_DEBUG_TLB
677 select SYS_FSL_ERRATUM_A004508
678 select SYS_FSL_ERRATUM_A005125
679 select SYS_FSL_ERRATUM_ELBC_A001
680 select SYS_FSL_ERRATUM_ESDHC111
681 select SYS_FSL_HAS_DDR3
682 select SYS_FSL_HAS_SEC
683 select SYS_FSL_SEC_BE
684 select SYS_FSL_SEC_COMPAT_2
685 select SYS_PPC_E500_USE_DEBUG_TLB
691 select SYS_FSL_ERRATUM_A004477
692 select SYS_FSL_ERRATUM_A004508
693 select SYS_FSL_ERRATUM_A005125
694 select SYS_FSL_ERRATUM_ESDHC111
695 select SYS_FSL_ERRATUM_ESDHC_A001
696 select SYS_FSL_HAS_DDR3
697 select SYS_FSL_HAS_SEC
698 select SYS_FSL_SEC_BE
699 select SYS_FSL_SEC_COMPAT_2
700 select SYS_PPC_E500_USE_DEBUG_TLB
708 select SYS_FSL_ERRATUM_A004510
709 select SYS_FSL_ERRATUM_A004849
710 select SYS_FSL_ERRATUM_A006261
711 select SYS_FSL_ERRATUM_CPU_A003999
712 select SYS_FSL_ERRATUM_DDR_A003
713 select SYS_FSL_ERRATUM_DDR_A003474
714 select SYS_FSL_ERRATUM_ESDHC111
715 select SYS_FSL_ERRATUM_I2C_A004447
716 select SYS_FSL_ERRATUM_NMG_CPU_A011
717 select SYS_FSL_ERRATUM_SRIO_A004034
718 select SYS_FSL_ERRATUM_USB14
719 select SYS_FSL_HAS_DDR3
720 select SYS_FSL_HAS_SEC
721 select SYS_FSL_QORIQ_CHASSIS1
722 select SYS_FSL_SEC_BE
723 select SYS_FSL_SEC_COMPAT_4
730 select SYS_FSL_DDR_VER_44
731 select SYS_FSL_ERRATUM_A004510
732 select SYS_FSL_ERRATUM_A004849
733 select SYS_FSL_ERRATUM_A005812
734 select SYS_FSL_ERRATUM_A006261
735 select SYS_FSL_ERRATUM_CPU_A003999
736 select SYS_FSL_ERRATUM_DDR_A003
737 select SYS_FSL_ERRATUM_DDR_A003474
738 select SYS_FSL_ERRATUM_ESDHC111
739 select SYS_FSL_ERRATUM_I2C_A004447
740 select SYS_FSL_ERRATUM_NMG_CPU_A011
741 select SYS_FSL_ERRATUM_SRIO_A004034
742 select SYS_FSL_ERRATUM_USB14
743 select SYS_FSL_HAS_DDR3
744 select SYS_FSL_HAS_SEC
745 select SYS_FSL_QORIQ_CHASSIS1
746 select SYS_FSL_SEC_BE
747 select SYS_FSL_SEC_COMPAT_4
754 select SYS_FSL_DDR_VER_44
755 select SYS_FSL_ERRATUM_A004510
756 select SYS_FSL_ERRATUM_A004580
757 select SYS_FSL_ERRATUM_A004849
758 select SYS_FSL_ERRATUM_A005812
759 select SYS_FSL_ERRATUM_A007075
760 select SYS_FSL_ERRATUM_CPC_A002
761 select SYS_FSL_ERRATUM_CPC_A003
762 select SYS_FSL_ERRATUM_CPU_A003999
763 select SYS_FSL_ERRATUM_DDR_A003
764 select SYS_FSL_ERRATUM_DDR_A003474
765 select SYS_FSL_ERRATUM_ELBC_A001
766 select SYS_FSL_ERRATUM_ESDHC111
767 select SYS_FSL_ERRATUM_ESDHC13
768 select SYS_FSL_ERRATUM_ESDHC135
769 select SYS_FSL_ERRATUM_I2C_A004447
770 select SYS_FSL_ERRATUM_NMG_CPU_A011
771 select SYS_FSL_ERRATUM_SRIO_A004034
772 select SYS_P4080_ERRATUM_CPU22
773 select SYS_P4080_ERRATUM_PCIE_A003
774 select SYS_P4080_ERRATUM_SERDES8
775 select SYS_P4080_ERRATUM_SERDES9
776 select SYS_P4080_ERRATUM_SERDES_A001
777 select SYS_P4080_ERRATUM_SERDES_A005
778 select SYS_FSL_HAS_DDR3
779 select SYS_FSL_HAS_SEC
780 select SYS_FSL_QORIQ_CHASSIS1
781 select SYS_FSL_SEC_BE
782 select SYS_FSL_SEC_COMPAT_4
789 select SYS_FSL_DDR_VER_44
790 select SYS_FSL_ERRATUM_A004510
791 select SYS_FSL_ERRATUM_A006261
792 select SYS_FSL_ERRATUM_DDR_A003
793 select SYS_FSL_ERRATUM_DDR_A003474
794 select SYS_FSL_ERRATUM_ESDHC111
795 select SYS_FSL_ERRATUM_I2C_A004447
796 select SYS_FSL_ERRATUM_SRIO_A004034
797 select SYS_FSL_ERRATUM_USB14
798 select SYS_FSL_HAS_DDR3
799 select SYS_FSL_HAS_SEC
800 select SYS_FSL_QORIQ_CHASSIS1
801 select SYS_FSL_SEC_BE
802 select SYS_FSL_SEC_COMPAT_4
810 select SYS_FSL_DDR_VER_44
811 select SYS_FSL_ERRATUM_A004510
812 select SYS_FSL_ERRATUM_A004699
813 select SYS_FSL_ERRATUM_A005812
814 select SYS_FSL_ERRATUM_A006261
815 select SYS_FSL_ERRATUM_DDR_A003
816 select SYS_FSL_ERRATUM_DDR_A003474
817 select SYS_FSL_ERRATUM_ESDHC111
818 select SYS_FSL_ERRATUM_USB14
819 select SYS_FSL_HAS_DDR3
820 select SYS_FSL_HAS_SEC
821 select SYS_FSL_QORIQ_CHASSIS1
822 select SYS_FSL_SEC_BE
823 select SYS_FSL_SEC_COMPAT_4
827 config ARCH_QEMU_E500
834 select SYS_FSL_DDR_VER_50
835 select SYS_FSL_ERRATUM_A008378
836 select SYS_FSL_ERRATUM_A009663
837 select SYS_FSL_ERRATUM_A009942
838 select SYS_FSL_ERRATUM_ESDHC111
839 select SYS_FSL_HAS_DDR3
840 select SYS_FSL_HAS_DDR4
841 select SYS_FSL_HAS_SEC
842 select SYS_FSL_QORIQ_CHASSIS2
843 select SYS_FSL_SEC_BE
844 select SYS_FSL_SEC_COMPAT_5
852 select SYS_FSL_DDR_VER_50
853 select SYS_FSL_ERRATUM_A008378
854 select SYS_FSL_ERRATUM_A009663
855 select SYS_FSL_ERRATUM_A009942
856 select SYS_FSL_ERRATUM_ESDHC111
857 select SYS_FSL_HAS_DDR3
858 select SYS_FSL_HAS_DDR4
859 select SYS_FSL_HAS_SEC
860 select SYS_FSL_QORIQ_CHASSIS2
861 select SYS_FSL_SEC_BE
862 select SYS_FSL_SEC_COMPAT_5
870 select SYS_FSL_DDR_VER_50
871 select SYS_FSL_ERRATUM_A008044
872 select SYS_FSL_ERRATUM_A008378
873 select SYS_FSL_ERRATUM_A009663
874 select SYS_FSL_ERRATUM_A009942
875 select SYS_FSL_ERRATUM_ESDHC111
876 select SYS_FSL_HAS_DDR3
877 select SYS_FSL_HAS_DDR4
878 select SYS_FSL_HAS_SEC
879 select SYS_FSL_QORIQ_CHASSIS2
880 select SYS_FSL_SEC_BE
881 select SYS_FSL_SEC_COMPAT_5
888 select SYS_FSL_DDR_VER_50
889 select SYS_FSL_ERRATUM_A008044
890 select SYS_FSL_ERRATUM_A008378
891 select SYS_FSL_ERRATUM_A009663
892 select SYS_FSL_ERRATUM_A009942
893 select SYS_FSL_ERRATUM_ESDHC111
894 select SYS_FSL_HAS_DDR3
895 select SYS_FSL_HAS_DDR4
896 select SYS_FSL_HAS_SEC
897 select SYS_FSL_QORIQ_CHASSIS2
898 select SYS_FSL_SEC_BE
899 select SYS_FSL_SEC_COMPAT_5
907 select SYS_FSL_DDR_VER_47
908 select SYS_FSL_ERRATUM_A006379
909 select SYS_FSL_ERRATUM_A006593
910 select SYS_FSL_ERRATUM_A007186
911 select SYS_FSL_ERRATUM_A007212
912 select SYS_FSL_ERRATUM_A007815
913 select SYS_FSL_ERRATUM_A007907
914 select SYS_FSL_ERRATUM_A009942
915 select SYS_FSL_ERRATUM_ESDHC111
916 select SYS_FSL_HAS_DDR3
917 select SYS_FSL_HAS_SEC
918 select SYS_FSL_QORIQ_CHASSIS2
919 select SYS_FSL_SEC_BE
920 select SYS_FSL_SEC_COMPAT_4
929 select SYS_FSL_DDR_VER_47
930 select SYS_FSL_ERRATUM_A006379
931 select SYS_FSL_ERRATUM_A006593
932 select SYS_FSL_ERRATUM_A007186
933 select SYS_FSL_ERRATUM_A007212
934 select SYS_FSL_ERRATUM_A009942
935 select SYS_FSL_ERRATUM_ESDHC111
936 select SYS_FSL_HAS_DDR3
937 select SYS_FSL_HAS_SEC
938 select SYS_FSL_QORIQ_CHASSIS2
939 select SYS_FSL_SEC_BE
940 select SYS_FSL_SEC_COMPAT_4
949 select SYS_FSL_DDR_VER_47
950 select SYS_FSL_ERRATUM_A004468
951 select SYS_FSL_ERRATUM_A005871
952 select SYS_FSL_ERRATUM_A006379
953 select SYS_FSL_ERRATUM_A006593
954 select SYS_FSL_ERRATUM_A007186
955 select SYS_FSL_ERRATUM_A007798
956 select SYS_FSL_ERRATUM_A009942
957 select SYS_FSL_HAS_DDR3
958 select SYS_FSL_HAS_SEC
959 select SYS_FSL_QORIQ_CHASSIS2
960 select SYS_FSL_SEC_BE
961 select SYS_FSL_SEC_COMPAT_4
970 select SYS_FSL_DDR_VER_47
971 select SYS_FSL_ERRATUM_A004468
972 select SYS_FSL_ERRATUM_A005871
973 select SYS_FSL_ERRATUM_A006261
974 select SYS_FSL_ERRATUM_A006379
975 select SYS_FSL_ERRATUM_A006593
976 select SYS_FSL_ERRATUM_A007186
977 select SYS_FSL_ERRATUM_A007798
978 select SYS_FSL_ERRATUM_A007815
979 select SYS_FSL_ERRATUM_A007907
980 select SYS_FSL_ERRATUM_A009942
981 select SYS_FSL_HAS_DDR3
982 select SYS_FSL_HAS_SEC
983 select SYS_FSL_QORIQ_CHASSIS2
984 select SYS_FSL_SEC_BE
985 select SYS_FSL_SEC_COMPAT_4
997 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1002 Enble PowerPC E500MC core
1007 Enable PowerPC E6500 core
1012 Use Freescale common code for Local Access Window
1017 Enable Freescale Secure Boot feature. Normally selected
1018 by defconfig. If unsure, do not change.
1021 int "Maximum number of CPUs permitted for MPC85xx"
1022 default 12 if ARCH_T4240
1023 default 8 if ARCH_P4080 || \
1025 default 4 if ARCH_B4860 || \
1033 default 2 if ARCH_B4420 || \
1048 Set this number to the maximum number of possible CPUs in the SoC.
1049 SoCs may have multiple clusters with each cluster may have multiple
1050 ports. If some ports are reserved but higher ports are used for
1051 cores, count the reserved ports. This will allocate enough memory
1052 in spin table to properly handle all cores.
1054 config SYS_CCSRBAR_DEFAULT
1055 hex "Default CCSRBAR address"
1056 default 0xff700000 if ARCH_BSC9131 || \
1077 default 0xff600000 if ARCH_P1023
1078 default 0xfe000000 if ARCH_B4420 || \
1093 default 0xe0000000 if ARCH_QEMU_E500
1095 Default value of CCSRBAR comes from power-on-reset. It
1096 is fixed on each SoC. Some SoCs can have different value
1097 if changed by pre-boot regime. The value here must match
1098 the current value in SoC. If not sure, do not change.
1100 config SYS_FSL_ERRATUM_A004468
1103 config SYS_FSL_ERRATUM_A004477
1106 config SYS_FSL_ERRATUM_A004508
1109 config SYS_FSL_ERRATUM_A004580
1112 config SYS_FSL_ERRATUM_A004699
1115 config SYS_FSL_ERRATUM_A004849
1118 config SYS_FSL_ERRATUM_A004510
1121 config SYS_FSL_ERRATUM_A004510_SVR_REV
1123 depends on SYS_FSL_ERRATUM_A004510
1124 default 0x20 if ARCH_P4080
1127 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1129 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1132 config SYS_FSL_ERRATUM_A005125
1135 config SYS_FSL_ERRATUM_A005434
1138 config SYS_FSL_ERRATUM_A005812
1141 config SYS_FSL_ERRATUM_A005871
1144 config SYS_FSL_ERRATUM_A006261
1147 config SYS_FSL_ERRATUM_A006379
1150 config SYS_FSL_ERRATUM_A006384
1153 config SYS_FSL_ERRATUM_A006475
1156 config SYS_FSL_ERRATUM_A006593
1159 config SYS_FSL_ERRATUM_A007075
1162 config SYS_FSL_ERRATUM_A007186
1165 config SYS_FSL_ERRATUM_A007212
1168 config SYS_FSL_ERRATUM_A007815
1171 config SYS_FSL_ERRATUM_A007798
1174 config SYS_FSL_ERRATUM_A007907
1177 config SYS_FSL_ERRATUM_A008044
1180 config SYS_FSL_ERRATUM_CPC_A002
1183 config SYS_FSL_ERRATUM_CPC_A003
1186 config SYS_FSL_ERRATUM_CPU_A003999
1189 config SYS_FSL_ERRATUM_ELBC_A001
1192 config SYS_FSL_ERRATUM_I2C_A004447
1195 config SYS_FSL_A004447_SVR_REV
1197 depends on SYS_FSL_ERRATUM_I2C_A004447
1198 default 0x00 if ARCH_MPC8548
1199 default 0x10 if ARCH_P1010
1200 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1201 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1203 config SYS_FSL_ERRATUM_IFC_A002769
1206 config SYS_FSL_ERRATUM_IFC_A003399
1209 config SYS_FSL_ERRATUM_NMG_CPU_A011
1212 config SYS_FSL_ERRATUM_NMG_ETSEC129
1215 config SYS_FSL_ERRATUM_NMG_LBC103
1218 config SYS_FSL_ERRATUM_P1010_A003549
1221 config SYS_FSL_ERRATUM_SATA_A001
1224 config SYS_FSL_ERRATUM_SEC_A003571
1227 config SYS_FSL_ERRATUM_SRIO_A004034
1230 config SYS_FSL_ERRATUM_USB14
1233 config SYS_P4080_ERRATUM_CPU22
1236 config SYS_P4080_ERRATUM_PCIE_A003
1239 config SYS_P4080_ERRATUM_SERDES8
1242 config SYS_P4080_ERRATUM_SERDES9
1245 config SYS_P4080_ERRATUM_SERDES_A001
1248 config SYS_P4080_ERRATUM_SERDES_A005
1251 config SYS_FSL_QORIQ_CHASSIS1
1254 config SYS_FSL_QORIQ_CHASSIS2
1257 config SYS_FSL_NUM_LAWS
1258 int "Number of local access windows"
1260 default 32 if ARCH_B4420 || \
1271 default 16 if ARCH_T1023 || \
1275 default 12 if ARCH_BSC9131 || \
1289 default 10 if ARCH_MPC8544 || \
1293 default 8 if ARCH_MPC8540 || \
1298 Number of local access windows. This is fixed per SoC.
1299 If not sure, do not change.
1301 config SYS_FSL_THREADS_PER_CORE
1306 config SYS_NUM_TLBCAMS
1307 int "Number of TLB CAM entries"
1308 default 64 if E500MC
1311 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1312 16 for other E500 SoCs.
1317 config SYS_PPC_E500_USE_DEBUG_TLB
1326 config SYS_PPC_E500_DEBUG_TLB
1327 int "Temporary TLB entry for external debugger"
1328 depends on SYS_PPC_E500_USE_DEBUG_TLB
1329 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1330 default 1 if ARCH_MPC8536
1331 default 2 if ARCH_MPC8572 || \
1339 default 3 if ARCH_P1010 || \
1343 Select a temporary TLB entry to be used during boot to work
1344 around limitations in e500v1 and e500v2 external debugger
1345 support. This reduces the portions of the boot code where
1346 breakpoints and single stepping do not work. The value of this
1347 symbol should be set to the TLB1 entry to be used for this
1348 purpose. If unsure, do not change.
1350 config SYS_FSL_IFC_CLK_DIV
1351 int "Divider of platform clock"
1353 default 2 if ARCH_B4420 || \
1363 Defines divider of platform clock(clock input to
1366 config SYS_FSL_LBC_CLK_DIV
1367 int "Divider of platform clock"
1368 depends on FSL_ELBC || ARCH_MPC8540 || \
1369 ARCH_MPC8548 || ARCH_MPC8541 || \
1370 ARCH_MPC8555 || ARCH_MPC8560 || \
1373 default 2 if ARCH_P2041 || \
1381 Defines divider of platform clock(clock input to
1384 source "board/freescale/b4860qds/Kconfig"
1385 source "board/freescale/bsc9131rdb/Kconfig"
1386 source "board/freescale/bsc9132qds/Kconfig"
1387 source "board/freescale/c29xpcie/Kconfig"
1388 source "board/freescale/corenet_ds/Kconfig"
1389 source "board/freescale/mpc8536ds/Kconfig"
1390 source "board/freescale/mpc8541cds/Kconfig"
1391 source "board/freescale/mpc8544ds/Kconfig"
1392 source "board/freescale/mpc8548cds/Kconfig"
1393 source "board/freescale/mpc8555cds/Kconfig"
1394 source "board/freescale/mpc8568mds/Kconfig"
1395 source "board/freescale/mpc8569mds/Kconfig"
1396 source "board/freescale/mpc8572ds/Kconfig"
1397 source "board/freescale/p1010rdb/Kconfig"
1398 source "board/freescale/p1022ds/Kconfig"
1399 source "board/freescale/p1023rdb/Kconfig"
1400 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1401 source "board/freescale/p1_twr/Kconfig"
1402 source "board/freescale/p2041rdb/Kconfig"
1403 source "board/freescale/qemu-ppce500/Kconfig"
1404 source "board/freescale/t102xqds/Kconfig"
1405 source "board/freescale/t102xrdb/Kconfig"
1406 source "board/freescale/t1040qds/Kconfig"
1407 source "board/freescale/t104xrdb/Kconfig"
1408 source "board/freescale/t208xqds/Kconfig"
1409 source "board/freescale/t208xrdb/Kconfig"
1410 source "board/freescale/t4qds/Kconfig"
1411 source "board/freescale/t4rdb/Kconfig"
1412 source "board/gdsys/p1022/Kconfig"
1413 source "board/keymile/kmp204x/Kconfig"
1414 source "board/sbc8548/Kconfig"
1415 source "board/socrates/Kconfig"
1416 source "board/varisys/cyrus/Kconfig"
1417 source "board/xes/xpedite520x/Kconfig"
1418 source "board/xes/xpedite537x/Kconfig"
1419 source "board/xes/xpedite550x/Kconfig"
1420 source "board/Arcturus/ucp1020/Kconfig"