12 bool "Support sbc8548"
15 config TARGET_SOCRATES
16 bool "Support socrates"
19 config TARGET_B4420QDS
20 bool "Support B4420QDS"
25 config TARGET_B4860QDS
26 bool "Support B4860QDS"
28 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 config TARGET_BSC9131RDB
33 bool "Support BSC9131RDB"
36 select BOARD_EARLY_INIT_F
38 config TARGET_BSC9132QDS
39 bool "Support BSC9132QDS"
41 select BOARD_LATE_INIT if CHAIN_OF_TRUST
43 select BOARD_EARLY_INIT_F
45 config TARGET_C29XPCIE
46 bool "Support C29XPCIE"
48 select BOARD_LATE_INIT if CHAIN_OF_TRUST
54 bool "Support P3041DS"
57 select BOARD_LATE_INIT if CHAIN_OF_TRUST
60 bool "Support P4080DS"
63 select BOARD_LATE_INIT if CHAIN_OF_TRUST
66 bool "Support P5020DS"
69 select BOARD_LATE_INIT if CHAIN_OF_TRUST
72 bool "Support P5040DS"
75 select BOARD_LATE_INIT if CHAIN_OF_TRUST
77 config TARGET_MPC8536DS
78 bool "Support MPC8536DS"
80 # Use DDR3 controller with DDR2 DIMMs on this board
81 select SYS_FSL_DDRC_GEN3
83 config TARGET_MPC8540ADS
84 bool "Support MPC8540ADS"
87 config TARGET_MPC8541CDS
88 bool "Support MPC8541CDS"
91 config TARGET_MPC8544DS
92 bool "Support MPC8544DS"
95 config TARGET_MPC8548CDS
96 bool "Support MPC8548CDS"
99 config TARGET_MPC8555CDS
100 bool "Support MPC8555CDS"
103 config TARGET_MPC8560ADS
104 bool "Support MPC8560ADS"
107 config TARGET_MPC8568MDS
108 bool "Support MPC8568MDS"
111 config TARGET_MPC8569MDS
112 bool "Support MPC8569MDS"
115 config TARGET_MPC8572DS
116 bool "Support MPC8572DS"
118 # Use DDR3 controller with DDR2 DIMMs on this board
119 select SYS_FSL_DDRC_GEN3
121 config TARGET_P1010RDB_PA
122 bool "Support P1010RDB_PA"
124 select BOARD_LATE_INIT if CHAIN_OF_TRUST
128 config TARGET_P1010RDB_PB
129 bool "Support P1010RDB_PB"
131 select BOARD_LATE_INIT if CHAIN_OF_TRUST
135 config TARGET_P1022DS
136 bool "Support P1022DS"
141 config TARGET_P1023RDB
142 bool "Support P1023RDB"
145 config TARGET_P1020MBG
146 bool "Support P1020MBG-PC"
151 config TARGET_P1020RDB_PC
152 bool "Support P1020RDB-PC"
157 config TARGET_P1020RDB_PD
158 bool "Support P1020RDB-PD"
163 config TARGET_P1020UTM
164 bool "Support P1020UTM"
169 config TARGET_P1021RDB
170 bool "Support P1021RDB"
175 config TARGET_P1024RDB
176 bool "Support P1024RDB"
181 config TARGET_P1025RDB
182 bool "Support P1025RDB"
187 config TARGET_P2020RDB
188 bool "Support P2020RDB-PC"
194 bool "Support p1_twr"
197 config TARGET_P2041RDB
198 bool "Support P2041RDB"
200 select BOARD_LATE_INIT if CHAIN_OF_TRUST
203 config TARGET_QEMU_PPCE500
204 bool "Support qemu-ppce500"
205 select ARCH_QEMU_E500
208 config TARGET_T1024QDS
209 bool "Support T1024QDS"
211 select BOARD_LATE_INIT if CHAIN_OF_TRUST
215 config TARGET_T1023RDB
216 bool "Support T1023RDB"
218 select BOARD_LATE_INIT if CHAIN_OF_TRUST
222 config TARGET_T1024RDB
223 bool "Support T1024RDB"
225 select BOARD_LATE_INIT if CHAIN_OF_TRUST
229 config TARGET_T1040QDS
230 bool "Support T1040QDS"
232 select BOARD_LATE_INIT if CHAIN_OF_TRUST
235 config TARGET_T1040RDB
236 bool "Support T1040RDB"
238 select BOARD_LATE_INIT if CHAIN_OF_TRUST
242 config TARGET_T1040D4RDB
243 bool "Support T1040D4RDB"
245 select BOARD_LATE_INIT if CHAIN_OF_TRUST
249 config TARGET_T1042RDB
250 bool "Support T1042RDB"
252 select BOARD_LATE_INIT if CHAIN_OF_TRUST
256 config TARGET_T1042D4RDB
257 bool "Support T1042D4RDB"
259 select BOARD_LATE_INIT if CHAIN_OF_TRUST
263 config TARGET_T1042RDB_PI
264 bool "Support T1042RDB_PI"
266 select BOARD_LATE_INIT if CHAIN_OF_TRUST
270 config TARGET_T2080QDS
271 bool "Support T2080QDS"
273 select BOARD_LATE_INIT if CHAIN_OF_TRUST
277 config TARGET_T2080RDB
278 bool "Support T2080RDB"
280 select BOARD_LATE_INIT if CHAIN_OF_TRUST
284 config TARGET_T2081QDS
285 bool "Support T2081QDS"
290 config TARGET_T4160QDS
291 bool "Support T4160QDS"
293 select BOARD_LATE_INIT if CHAIN_OF_TRUST
297 config TARGET_T4160RDB
298 bool "Support T4160RDB"
303 config TARGET_T4240QDS
304 bool "Support T4240QDS"
306 select BOARD_LATE_INIT if CHAIN_OF_TRUST
310 config TARGET_T4240RDB
311 bool "Support T4240RDB"
316 config TARGET_CONTROLCENTERD
317 bool "Support controlcenterd"
320 config TARGET_KMP204X
321 bool "Support kmp204x"
327 config TARGET_XPEDITE520X
328 bool "Support xpedite520x"
331 config TARGET_XPEDITE537X
332 bool "Support xpedite537x"
334 # Use DDR3 controller with DDR2 DIMMs on this board
335 select SYS_FSL_DDRC_GEN3
337 config TARGET_XPEDITE550X
338 bool "Support xpedite550x"
341 config TARGET_UCP1020
342 bool "Support uCP1020"
345 config TARGET_CYRUS_P5020
346 bool "Support Varisys Cyrus P5020"
350 config TARGET_CYRUS_P5040
351 bool "Support Varisys Cyrus P5040"
362 select SYS_FSL_DDR_VER_47
363 select SYS_FSL_ERRATUM_A004477
364 select SYS_FSL_ERRATUM_A005871
365 select SYS_FSL_ERRATUM_A006379
366 select SYS_FSL_ERRATUM_A006384
367 select SYS_FSL_ERRATUM_A006475
368 select SYS_FSL_ERRATUM_A006593
369 select SYS_FSL_ERRATUM_A007075
370 select SYS_FSL_ERRATUM_A007186
371 select SYS_FSL_ERRATUM_A007212
372 select SYS_FSL_ERRATUM_A009942
373 select SYS_FSL_HAS_DDR3
374 select SYS_FSL_HAS_SEC
375 select SYS_FSL_QORIQ_CHASSIS2
376 select SYS_FSL_SEC_BE
377 select SYS_FSL_SEC_COMPAT_4
386 select SYS_FSL_DDR_VER_47
387 select SYS_FSL_ERRATUM_A004477
388 select SYS_FSL_ERRATUM_A005871
389 select SYS_FSL_ERRATUM_A006379
390 select SYS_FSL_ERRATUM_A006384
391 select SYS_FSL_ERRATUM_A006475
392 select SYS_FSL_ERRATUM_A006593
393 select SYS_FSL_ERRATUM_A007075
394 select SYS_FSL_ERRATUM_A007186
395 select SYS_FSL_ERRATUM_A007212
396 select SYS_FSL_ERRATUM_A007907
397 select SYS_FSL_ERRATUM_A009942
398 select SYS_FSL_HAS_DDR3
399 select SYS_FSL_HAS_SEC
400 select SYS_FSL_QORIQ_CHASSIS2
401 select SYS_FSL_SEC_BE
402 select SYS_FSL_SEC_COMPAT_4
409 select SYS_FSL_DDR_VER_44
410 select SYS_FSL_ERRATUM_A004477
411 select SYS_FSL_ERRATUM_A005125
412 select SYS_FSL_ERRATUM_ESDHC111
413 select SYS_FSL_HAS_DDR3
414 select SYS_FSL_HAS_SEC
415 select SYS_FSL_SEC_BE
416 select SYS_FSL_SEC_COMPAT_4
422 select SYS_FSL_DDR_VER_46
423 select SYS_FSL_ERRATUM_A004477
424 select SYS_FSL_ERRATUM_A005125
425 select SYS_FSL_ERRATUM_A005434
426 select SYS_FSL_ERRATUM_ESDHC111
427 select SYS_FSL_ERRATUM_I2C_A004447
428 select SYS_FSL_ERRATUM_IFC_A002769
429 select SYS_FSL_HAS_DDR3
430 select SYS_FSL_HAS_SEC
431 select SYS_FSL_SEC_BE
432 select SYS_FSL_SEC_COMPAT_4
433 select SYS_PPC_E500_USE_DEBUG_TLB
439 select SYS_FSL_DDR_VER_46
440 select SYS_FSL_ERRATUM_A005125
441 select SYS_FSL_ERRATUM_ESDHC111
442 select SYS_FSL_HAS_DDR3
443 select SYS_FSL_HAS_SEC
444 select SYS_FSL_SEC_BE
445 select SYS_FSL_SEC_COMPAT_6
446 select SYS_PPC_E500_USE_DEBUG_TLB
452 select SYS_FSL_ERRATUM_A004508
453 select SYS_FSL_ERRATUM_A005125
454 select SYS_FSL_HAS_DDR2
455 select SYS_FSL_HAS_DDR3
456 select SYS_FSL_HAS_SEC
457 select SYS_FSL_SEC_BE
458 select SYS_FSL_SEC_COMPAT_2
459 select SYS_PPC_E500_USE_DEBUG_TLB
465 select SYS_FSL_HAS_DDR1
470 select SYS_FSL_HAS_DDR1
471 select SYS_FSL_HAS_SEC
472 select SYS_FSL_SEC_BE
473 select SYS_FSL_SEC_COMPAT_2
478 select SYS_FSL_ERRATUM_A005125
479 select SYS_FSL_HAS_DDR2
480 select SYS_FSL_HAS_SEC
481 select SYS_FSL_SEC_BE
482 select SYS_FSL_SEC_COMPAT_2
483 select SYS_PPC_E500_USE_DEBUG_TLB
489 select SYS_FSL_ERRATUM_A005125
490 select SYS_FSL_ERRATUM_NMG_DDR120
491 select SYS_FSL_ERRATUM_NMG_LBC103
492 select SYS_FSL_ERRATUM_NMG_ETSEC129
493 select SYS_FSL_ERRATUM_I2C_A004447
494 select SYS_FSL_HAS_DDR2
495 select SYS_FSL_HAS_DDR1
496 select SYS_FSL_HAS_SEC
497 select SYS_FSL_SEC_BE
498 select SYS_FSL_SEC_COMPAT_2
499 select SYS_PPC_E500_USE_DEBUG_TLB
504 select SYS_FSL_HAS_DDR1
505 select SYS_FSL_HAS_SEC
506 select SYS_FSL_SEC_BE
507 select SYS_FSL_SEC_COMPAT_2
512 select SYS_FSL_HAS_DDR1
517 select SYS_FSL_HAS_DDR2
518 select SYS_FSL_HAS_SEC
519 select SYS_FSL_SEC_BE
520 select SYS_FSL_SEC_COMPAT_2
525 select SYS_FSL_ERRATUM_A004508
526 select SYS_FSL_ERRATUM_A005125
527 select SYS_FSL_HAS_DDR3
528 select SYS_FSL_HAS_SEC
529 select SYS_FSL_SEC_BE
530 select SYS_FSL_SEC_COMPAT_2
536 select SYS_FSL_ERRATUM_A004508
537 select SYS_FSL_ERRATUM_A005125
538 select SYS_FSL_ERRATUM_DDR_115
539 select SYS_FSL_ERRATUM_DDR111_DDR134
540 select SYS_FSL_HAS_DDR2
541 select SYS_FSL_HAS_DDR3
542 select SYS_FSL_HAS_SEC
543 select SYS_FSL_SEC_BE
544 select SYS_FSL_SEC_COMPAT_2
545 select SYS_PPC_E500_USE_DEBUG_TLB
551 select SYS_FSL_ERRATUM_A004477
552 select SYS_FSL_ERRATUM_A004508
553 select SYS_FSL_ERRATUM_A005125
554 select SYS_FSL_ERRATUM_A006261
555 select SYS_FSL_ERRATUM_A007075
556 select SYS_FSL_ERRATUM_ESDHC111
557 select SYS_FSL_ERRATUM_I2C_A004447
558 select SYS_FSL_ERRATUM_IFC_A002769
559 select SYS_FSL_ERRATUM_P1010_A003549
560 select SYS_FSL_ERRATUM_SEC_A003571
561 select SYS_FSL_ERRATUM_IFC_A003399
562 select SYS_FSL_HAS_DDR3
563 select SYS_FSL_HAS_SEC
564 select SYS_FSL_SEC_BE
565 select SYS_FSL_SEC_COMPAT_4
566 select SYS_PPC_E500_USE_DEBUG_TLB
572 select SYS_FSL_ERRATUM_A004508
573 select SYS_FSL_ERRATUM_A005125
574 select SYS_FSL_ERRATUM_ELBC_A001
575 select SYS_FSL_ERRATUM_ESDHC111
576 select SYS_FSL_HAS_DDR3
577 select SYS_FSL_HAS_SEC
578 select SYS_FSL_SEC_BE
579 select SYS_FSL_SEC_COMPAT_2
580 select SYS_PPC_E500_USE_DEBUG_TLB
586 select SYS_FSL_ERRATUM_A004508
587 select SYS_FSL_ERRATUM_A005125
588 select SYS_FSL_ERRATUM_ELBC_A001
589 select SYS_FSL_ERRATUM_ESDHC111
590 select SYS_FSL_HAS_DDR3
591 select SYS_FSL_HAS_SEC
592 select SYS_FSL_SEC_BE
593 select SYS_FSL_SEC_COMPAT_2
594 select SYS_PPC_E500_USE_DEBUG_TLB
600 select SYS_FSL_ERRATUM_A004508
601 select SYS_FSL_ERRATUM_A005125
602 select SYS_FSL_ERRATUM_ELBC_A001
603 select SYS_FSL_ERRATUM_ESDHC111
604 select SYS_FSL_HAS_DDR3
605 select SYS_FSL_HAS_SEC
606 select SYS_FSL_SEC_BE
607 select SYS_FSL_SEC_COMPAT_2
608 select SYS_PPC_E500_USE_DEBUG_TLB
614 select SYS_FSL_ERRATUM_A004477
615 select SYS_FSL_ERRATUM_A004508
616 select SYS_FSL_ERRATUM_A005125
617 select SYS_FSL_ERRATUM_ELBC_A001
618 select SYS_FSL_ERRATUM_ESDHC111
619 select SYS_FSL_ERRATUM_SATA_A001
620 select SYS_FSL_HAS_DDR3
621 select SYS_FSL_HAS_SEC
622 select SYS_FSL_SEC_BE
623 select SYS_FSL_SEC_COMPAT_2
624 select SYS_PPC_E500_USE_DEBUG_TLB
630 select SYS_FSL_ERRATUM_A004508
631 select SYS_FSL_ERRATUM_A005125
632 select SYS_FSL_ERRATUM_I2C_A004447
633 select SYS_FSL_HAS_DDR3
634 select SYS_FSL_HAS_SEC
635 select SYS_FSL_SEC_BE
636 select SYS_FSL_SEC_COMPAT_4
642 select SYS_FSL_ERRATUM_A004508
643 select SYS_FSL_ERRATUM_A005125
644 select SYS_FSL_ERRATUM_ELBC_A001
645 select SYS_FSL_ERRATUM_ESDHC111
646 select SYS_FSL_HAS_DDR3
647 select SYS_FSL_HAS_SEC
648 select SYS_FSL_SEC_BE
649 select SYS_FSL_SEC_COMPAT_2
650 select SYS_PPC_E500_USE_DEBUG_TLB
656 select SYS_FSL_ERRATUM_A004508
657 select SYS_FSL_ERRATUM_A005125
658 select SYS_FSL_ERRATUM_ELBC_A001
659 select SYS_FSL_ERRATUM_ESDHC111
660 select SYS_FSL_HAS_DDR3
661 select SYS_FSL_HAS_SEC
662 select SYS_FSL_SEC_BE
663 select SYS_FSL_SEC_COMPAT_2
664 select SYS_PPC_E500_USE_DEBUG_TLB
670 select SYS_FSL_ERRATUM_A004477
671 select SYS_FSL_ERRATUM_A004508
672 select SYS_FSL_ERRATUM_A005125
673 select SYS_FSL_ERRATUM_ESDHC111
674 select SYS_FSL_ERRATUM_ESDHC_A001
675 select SYS_FSL_HAS_DDR3
676 select SYS_FSL_HAS_SEC
677 select SYS_FSL_SEC_BE
678 select SYS_FSL_SEC_COMPAT_2
679 select SYS_PPC_E500_USE_DEBUG_TLB
686 select SYS_FSL_ERRATUM_A004510
687 select SYS_FSL_ERRATUM_A004849
688 select SYS_FSL_ERRATUM_A006261
689 select SYS_FSL_ERRATUM_CPU_A003999
690 select SYS_FSL_ERRATUM_DDR_A003
691 select SYS_FSL_ERRATUM_DDR_A003474
692 select SYS_FSL_ERRATUM_ESDHC111
693 select SYS_FSL_ERRATUM_I2C_A004447
694 select SYS_FSL_ERRATUM_NMG_CPU_A011
695 select SYS_FSL_ERRATUM_SRIO_A004034
696 select SYS_FSL_ERRATUM_USB14
697 select SYS_FSL_HAS_DDR3
698 select SYS_FSL_HAS_SEC
699 select SYS_FSL_QORIQ_CHASSIS1
700 select SYS_FSL_SEC_BE
701 select SYS_FSL_SEC_COMPAT_4
708 select SYS_FSL_DDR_VER_44
709 select SYS_FSL_ERRATUM_A004510
710 select SYS_FSL_ERRATUM_A004849
711 select SYS_FSL_ERRATUM_A005812
712 select SYS_FSL_ERRATUM_A006261
713 select SYS_FSL_ERRATUM_CPU_A003999
714 select SYS_FSL_ERRATUM_DDR_A003
715 select SYS_FSL_ERRATUM_DDR_A003474
716 select SYS_FSL_ERRATUM_ESDHC111
717 select SYS_FSL_ERRATUM_I2C_A004447
718 select SYS_FSL_ERRATUM_NMG_CPU_A011
719 select SYS_FSL_ERRATUM_SRIO_A004034
720 select SYS_FSL_ERRATUM_USB14
721 select SYS_FSL_HAS_DDR3
722 select SYS_FSL_HAS_SEC
723 select SYS_FSL_QORIQ_CHASSIS1
724 select SYS_FSL_SEC_BE
725 select SYS_FSL_SEC_COMPAT_4
732 select SYS_FSL_DDR_VER_44
733 select SYS_FSL_ERRATUM_A004510
734 select SYS_FSL_ERRATUM_A004580
735 select SYS_FSL_ERRATUM_A004849
736 select SYS_FSL_ERRATUM_A005812
737 select SYS_FSL_ERRATUM_A007075
738 select SYS_FSL_ERRATUM_CPC_A002
739 select SYS_FSL_ERRATUM_CPC_A003
740 select SYS_FSL_ERRATUM_CPU_A003999
741 select SYS_FSL_ERRATUM_DDR_A003
742 select SYS_FSL_ERRATUM_DDR_A003474
743 select SYS_FSL_ERRATUM_ELBC_A001
744 select SYS_FSL_ERRATUM_ESDHC111
745 select SYS_FSL_ERRATUM_ESDHC13
746 select SYS_FSL_ERRATUM_ESDHC135
747 select SYS_FSL_ERRATUM_I2C_A004447
748 select SYS_FSL_ERRATUM_NMG_CPU_A011
749 select SYS_FSL_ERRATUM_SRIO_A004034
750 select SYS_P4080_ERRATUM_CPU22
751 select SYS_P4080_ERRATUM_PCIE_A003
752 select SYS_P4080_ERRATUM_SERDES8
753 select SYS_P4080_ERRATUM_SERDES9
754 select SYS_P4080_ERRATUM_SERDES_A001
755 select SYS_P4080_ERRATUM_SERDES_A005
756 select SYS_FSL_HAS_DDR3
757 select SYS_FSL_HAS_SEC
758 select SYS_FSL_QORIQ_CHASSIS1
759 select SYS_FSL_SEC_BE
760 select SYS_FSL_SEC_COMPAT_4
767 select SYS_FSL_DDR_VER_44
768 select SYS_FSL_ERRATUM_A004510
769 select SYS_FSL_ERRATUM_A006261
770 select SYS_FSL_ERRATUM_DDR_A003
771 select SYS_FSL_ERRATUM_DDR_A003474
772 select SYS_FSL_ERRATUM_ESDHC111
773 select SYS_FSL_ERRATUM_I2C_A004447
774 select SYS_FSL_ERRATUM_SRIO_A004034
775 select SYS_FSL_ERRATUM_USB14
776 select SYS_FSL_HAS_DDR3
777 select SYS_FSL_HAS_SEC
778 select SYS_FSL_QORIQ_CHASSIS1
779 select SYS_FSL_SEC_BE
780 select SYS_FSL_SEC_COMPAT_4
788 select SYS_FSL_DDR_VER_44
789 select SYS_FSL_ERRATUM_A004510
790 select SYS_FSL_ERRATUM_A004699
791 select SYS_FSL_ERRATUM_A005812
792 select SYS_FSL_ERRATUM_A006261
793 select SYS_FSL_ERRATUM_DDR_A003
794 select SYS_FSL_ERRATUM_DDR_A003474
795 select SYS_FSL_ERRATUM_ESDHC111
796 select SYS_FSL_ERRATUM_USB14
797 select SYS_FSL_HAS_DDR3
798 select SYS_FSL_HAS_SEC
799 select SYS_FSL_QORIQ_CHASSIS1
800 select SYS_FSL_SEC_BE
801 select SYS_FSL_SEC_COMPAT_4
805 config ARCH_QEMU_E500
812 select SYS_FSL_DDR_VER_50
813 select SYS_FSL_ERRATUM_A008378
814 select SYS_FSL_ERRATUM_A009663
815 select SYS_FSL_ERRATUM_A009942
816 select SYS_FSL_ERRATUM_ESDHC111
817 select SYS_FSL_HAS_DDR3
818 select SYS_FSL_HAS_DDR4
819 select SYS_FSL_HAS_SEC
820 select SYS_FSL_QORIQ_CHASSIS2
821 select SYS_FSL_SEC_BE
822 select SYS_FSL_SEC_COMPAT_5
829 select SYS_FSL_DDR_VER_50
830 select SYS_FSL_ERRATUM_A008378
831 select SYS_FSL_ERRATUM_A009663
832 select SYS_FSL_ERRATUM_A009942
833 select SYS_FSL_ERRATUM_ESDHC111
834 select SYS_FSL_HAS_DDR3
835 select SYS_FSL_HAS_DDR4
836 select SYS_FSL_HAS_SEC
837 select SYS_FSL_QORIQ_CHASSIS2
838 select SYS_FSL_SEC_BE
839 select SYS_FSL_SEC_COMPAT_5
846 select SYS_FSL_DDR_VER_50
847 select SYS_FSL_ERRATUM_A008044
848 select SYS_FSL_ERRATUM_A008378
849 select SYS_FSL_ERRATUM_A009663
850 select SYS_FSL_ERRATUM_A009942
851 select SYS_FSL_ERRATUM_ESDHC111
852 select SYS_FSL_HAS_DDR3
853 select SYS_FSL_HAS_DDR4
854 select SYS_FSL_HAS_SEC
855 select SYS_FSL_QORIQ_CHASSIS2
856 select SYS_FSL_SEC_BE
857 select SYS_FSL_SEC_COMPAT_5
864 select SYS_FSL_DDR_VER_50
865 select SYS_FSL_ERRATUM_A008044
866 select SYS_FSL_ERRATUM_A008378
867 select SYS_FSL_ERRATUM_A009663
868 select SYS_FSL_ERRATUM_A009942
869 select SYS_FSL_ERRATUM_ESDHC111
870 select SYS_FSL_HAS_DDR3
871 select SYS_FSL_HAS_DDR4
872 select SYS_FSL_HAS_SEC
873 select SYS_FSL_QORIQ_CHASSIS2
874 select SYS_FSL_SEC_BE
875 select SYS_FSL_SEC_COMPAT_5
883 select SYS_FSL_DDR_VER_47
884 select SYS_FSL_ERRATUM_A006379
885 select SYS_FSL_ERRATUM_A006593
886 select SYS_FSL_ERRATUM_A007186
887 select SYS_FSL_ERRATUM_A007212
888 select SYS_FSL_ERRATUM_A007815
889 select SYS_FSL_ERRATUM_A007907
890 select SYS_FSL_ERRATUM_A009942
891 select SYS_FSL_ERRATUM_ESDHC111
892 select SYS_FSL_HAS_DDR3
893 select SYS_FSL_HAS_SEC
894 select SYS_FSL_QORIQ_CHASSIS2
895 select SYS_FSL_SEC_BE
896 select SYS_FSL_SEC_COMPAT_4
905 select SYS_FSL_DDR_VER_47
906 select SYS_FSL_ERRATUM_A006379
907 select SYS_FSL_ERRATUM_A006593
908 select SYS_FSL_ERRATUM_A007186
909 select SYS_FSL_ERRATUM_A007212
910 select SYS_FSL_ERRATUM_A009942
911 select SYS_FSL_ERRATUM_ESDHC111
912 select SYS_FSL_HAS_DDR3
913 select SYS_FSL_HAS_SEC
914 select SYS_FSL_QORIQ_CHASSIS2
915 select SYS_FSL_SEC_BE
916 select SYS_FSL_SEC_COMPAT_4
925 select SYS_FSL_DDR_VER_47
926 select SYS_FSL_ERRATUM_A004468
927 select SYS_FSL_ERRATUM_A005871
928 select SYS_FSL_ERRATUM_A006379
929 select SYS_FSL_ERRATUM_A006593
930 select SYS_FSL_ERRATUM_A007186
931 select SYS_FSL_ERRATUM_A007798
932 select SYS_FSL_ERRATUM_A009942
933 select SYS_FSL_HAS_DDR3
934 select SYS_FSL_HAS_SEC
935 select SYS_FSL_QORIQ_CHASSIS2
936 select SYS_FSL_SEC_BE
937 select SYS_FSL_SEC_COMPAT_4
946 select SYS_FSL_DDR_VER_47
947 select SYS_FSL_ERRATUM_A004468
948 select SYS_FSL_ERRATUM_A005871
949 select SYS_FSL_ERRATUM_A006261
950 select SYS_FSL_ERRATUM_A006379
951 select SYS_FSL_ERRATUM_A006593
952 select SYS_FSL_ERRATUM_A007186
953 select SYS_FSL_ERRATUM_A007798
954 select SYS_FSL_ERRATUM_A007815
955 select SYS_FSL_ERRATUM_A007907
956 select SYS_FSL_ERRATUM_A009942
957 select SYS_FSL_HAS_DDR3
958 select SYS_FSL_HAS_SEC
959 select SYS_FSL_QORIQ_CHASSIS2
960 select SYS_FSL_SEC_BE
961 select SYS_FSL_SEC_COMPAT_4
973 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
978 Enble PowerPC E500MC core
983 Enable PowerPC E6500 core
988 Use Freescale common code for Local Access Window
993 Enable Freescale Secure Boot feature. Normally selected
994 by defconfig. If unsure, do not change.
997 int "Maximum number of CPUs permitted for MPC85xx"
998 default 12 if ARCH_T4240
999 default 8 if ARCH_P4080 || \
1001 default 4 if ARCH_B4860 || \
1009 default 2 if ARCH_B4420 || \
1024 Set this number to the maximum number of possible CPUs in the SoC.
1025 SoCs may have multiple clusters with each cluster may have multiple
1026 ports. If some ports are reserved but higher ports are used for
1027 cores, count the reserved ports. This will allocate enough memory
1028 in spin table to properly handle all cores.
1030 config SYS_CCSRBAR_DEFAULT
1031 hex "Default CCSRBAR address"
1032 default 0xff700000 if ARCH_BSC9131 || \
1053 default 0xff600000 if ARCH_P1023
1054 default 0xfe000000 if ARCH_B4420 || \
1069 default 0xe0000000 if ARCH_QEMU_E500
1071 Default value of CCSRBAR comes from power-on-reset. It
1072 is fixed on each SoC. Some SoCs can have different value
1073 if changed by pre-boot regime. The value here must match
1074 the current value in SoC. If not sure, do not change.
1076 config SYS_FSL_ERRATUM_A004468
1079 config SYS_FSL_ERRATUM_A004477
1082 config SYS_FSL_ERRATUM_A004508
1085 config SYS_FSL_ERRATUM_A004580
1088 config SYS_FSL_ERRATUM_A004699
1091 config SYS_FSL_ERRATUM_A004849
1094 config SYS_FSL_ERRATUM_A004510
1097 config SYS_FSL_ERRATUM_A004510_SVR_REV
1099 depends on SYS_FSL_ERRATUM_A004510
1100 default 0x20 if ARCH_P4080
1103 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1105 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1108 config SYS_FSL_ERRATUM_A005125
1111 config SYS_FSL_ERRATUM_A005434
1114 config SYS_FSL_ERRATUM_A005812
1117 config SYS_FSL_ERRATUM_A005871
1120 config SYS_FSL_ERRATUM_A006261
1123 config SYS_FSL_ERRATUM_A006379
1126 config SYS_FSL_ERRATUM_A006384
1129 config SYS_FSL_ERRATUM_A006475
1132 config SYS_FSL_ERRATUM_A006593
1135 config SYS_FSL_ERRATUM_A007075
1138 config SYS_FSL_ERRATUM_A007186
1141 config SYS_FSL_ERRATUM_A007212
1144 config SYS_FSL_ERRATUM_A007815
1147 config SYS_FSL_ERRATUM_A007798
1150 config SYS_FSL_ERRATUM_A007907
1153 config SYS_FSL_ERRATUM_A008044
1156 config SYS_FSL_ERRATUM_CPC_A002
1159 config SYS_FSL_ERRATUM_CPC_A003
1162 config SYS_FSL_ERRATUM_CPU_A003999
1165 config SYS_FSL_ERRATUM_ELBC_A001
1168 config SYS_FSL_ERRATUM_I2C_A004447
1171 config SYS_FSL_A004447_SVR_REV
1173 depends on SYS_FSL_ERRATUM_I2C_A004447
1174 default 0x00 if ARCH_MPC8548
1175 default 0x10 if ARCH_P1010
1176 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1177 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1179 config SYS_FSL_ERRATUM_IFC_A002769
1182 config SYS_FSL_ERRATUM_IFC_A003399
1185 config SYS_FSL_ERRATUM_NMG_CPU_A011
1188 config SYS_FSL_ERRATUM_NMG_ETSEC129
1191 config SYS_FSL_ERRATUM_NMG_LBC103
1194 config SYS_FSL_ERRATUM_P1010_A003549
1197 config SYS_FSL_ERRATUM_SATA_A001
1200 config SYS_FSL_ERRATUM_SEC_A003571
1203 config SYS_FSL_ERRATUM_SRIO_A004034
1206 config SYS_FSL_ERRATUM_USB14
1209 config SYS_P4080_ERRATUM_CPU22
1212 config SYS_P4080_ERRATUM_PCIE_A003
1215 config SYS_P4080_ERRATUM_SERDES8
1218 config SYS_P4080_ERRATUM_SERDES9
1221 config SYS_P4080_ERRATUM_SERDES_A001
1224 config SYS_P4080_ERRATUM_SERDES_A005
1227 config SYS_FSL_QORIQ_CHASSIS1
1230 config SYS_FSL_QORIQ_CHASSIS2
1233 config SYS_FSL_NUM_LAWS
1234 int "Number of local access windows"
1236 default 32 if ARCH_B4420 || \
1247 default 16 if ARCH_T1023 || \
1251 default 12 if ARCH_BSC9131 || \
1265 default 10 if ARCH_MPC8544 || \
1269 default 8 if ARCH_MPC8540 || \
1274 Number of local access windows. This is fixed per SoC.
1275 If not sure, do not change.
1277 config SYS_FSL_THREADS_PER_CORE
1282 config SYS_NUM_TLBCAMS
1283 int "Number of TLB CAM entries"
1284 default 64 if E500MC
1287 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1288 16 for other E500 SoCs.
1293 config SYS_PPC_E500_USE_DEBUG_TLB
1302 config SYS_PPC_E500_DEBUG_TLB
1303 int "Temporary TLB entry for external debugger"
1304 depends on SYS_PPC_E500_USE_DEBUG_TLB
1305 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1306 default 1 if ARCH_MPC8536
1307 default 2 if ARCH_MPC8572 || \
1315 default 3 if ARCH_P1010 || \
1319 Select a temporary TLB entry to be used during boot to work
1320 around limitations in e500v1 and e500v2 external debugger
1321 support. This reduces the portions of the boot code where
1322 breakpoints and single stepping do not work. The value of this
1323 symbol should be set to the TLB1 entry to be used for this
1324 purpose. If unsure, do not change.
1326 config SYS_FSL_IFC_CLK_DIV
1327 int "Divider of platform clock"
1329 default 2 if ARCH_B4420 || \
1339 Defines divider of platform clock(clock input to
1342 config SYS_FSL_LBC_CLK_DIV
1343 int "Divider of platform clock"
1344 depends on FSL_ELBC || ARCH_MPC8540 || \
1345 ARCH_MPC8548 || ARCH_MPC8541 || \
1346 ARCH_MPC8555 || ARCH_MPC8560 || \
1349 default 2 if ARCH_P2041 || \
1357 Defines divider of platform clock(clock input to
1360 source "board/freescale/b4860qds/Kconfig"
1361 source "board/freescale/bsc9131rdb/Kconfig"
1362 source "board/freescale/bsc9132qds/Kconfig"
1363 source "board/freescale/c29xpcie/Kconfig"
1364 source "board/freescale/corenet_ds/Kconfig"
1365 source "board/freescale/mpc8536ds/Kconfig"
1366 source "board/freescale/mpc8540ads/Kconfig"
1367 source "board/freescale/mpc8541cds/Kconfig"
1368 source "board/freescale/mpc8544ds/Kconfig"
1369 source "board/freescale/mpc8548cds/Kconfig"
1370 source "board/freescale/mpc8555cds/Kconfig"
1371 source "board/freescale/mpc8560ads/Kconfig"
1372 source "board/freescale/mpc8568mds/Kconfig"
1373 source "board/freescale/mpc8569mds/Kconfig"
1374 source "board/freescale/mpc8572ds/Kconfig"
1375 source "board/freescale/p1010rdb/Kconfig"
1376 source "board/freescale/p1022ds/Kconfig"
1377 source "board/freescale/p1023rdb/Kconfig"
1378 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1379 source "board/freescale/p1_twr/Kconfig"
1380 source "board/freescale/p2041rdb/Kconfig"
1381 source "board/freescale/qemu-ppce500/Kconfig"
1382 source "board/freescale/t102xqds/Kconfig"
1383 source "board/freescale/t102xrdb/Kconfig"
1384 source "board/freescale/t1040qds/Kconfig"
1385 source "board/freescale/t104xrdb/Kconfig"
1386 source "board/freescale/t208xqds/Kconfig"
1387 source "board/freescale/t208xrdb/Kconfig"
1388 source "board/freescale/t4qds/Kconfig"
1389 source "board/freescale/t4rdb/Kconfig"
1390 source "board/gdsys/p1022/Kconfig"
1391 source "board/keymile/kmp204x/Kconfig"
1392 source "board/sbc8548/Kconfig"
1393 source "board/socrates/Kconfig"
1394 source "board/varisys/cyrus/Kconfig"
1395 source "board/xes/xpedite520x/Kconfig"
1396 source "board/xes/xpedite537x/Kconfig"
1397 source "board/xes/xpedite550x/Kconfig"
1398 source "board/Arcturus/ucp1020/Kconfig"