1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
9 DECLARE_GLOBAL_DATA_PTR;
12 * Breathe some life into the CPU...
14 * Set up the memory map,
15 * initialize a bunch of registers,
16 * initialize the UPM's
18 void cpu_init_f (volatile immap_t * im)
20 /* Pointer is writable since we allocated a register for it */
21 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
23 /* global data region was cleared in start.S */
25 /* system performance tweaking */
27 #ifdef CONFIG_SYS_ACR_PIPE_DEP
28 /* Arbiter pipeline depth */
29 im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
30 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
33 #ifdef CONFIG_SYS_ACR_RPTCNT
34 /* Arbiter repeat count */
35 im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
36 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
39 #ifdef CONFIG_SYS_SPCR_OPT
40 /* Optimize transactions between CSB and other devices */
41 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
42 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
45 /* Enable Time Base & Decrementer (so we will have udelay()) */
46 im->sysconf.spcr |= SPCR_TBEN;
48 /* DDR control driver register */
49 #ifdef CONFIG_SYS_DDRCDR
50 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
52 /* Output buffer impedance register */
53 #ifdef CONFIG_SYS_OBIR
54 im->sysconf.obir = CONFIG_SYS_OBIR;
61 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
62 * addresses - these have to be modified later when FLASH size
66 #if defined(CONFIG_SYS_NAND_BR_PRELIM) \
67 && defined(CONFIG_SYS_NAND_OR_PRELIM) \
68 && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
69 && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
70 set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
71 set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
72 im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
73 im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
75 #error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
80 * Get timebase clock frequency (like cpu_clk in Hz)
82 unsigned long get_tbclk(void)
84 return (gd->bus_clk + 3L) / 4L;
87 void puts(const char *str)
93 ulong get_bus_freq(ulong dummy)
95 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
96 u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
98 return CONFIG_83XX_CLKIN * spmf;