1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
9 #ifndef CONFIG_CLK_MPC83XX
15 #include <asm/processor.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 /* ----------------------------------------------------------------- */
37 mult_t core_csb_ratio;
41 static corecnf_t corecnf_tab[] = {
42 {_byp, _byp}, /* 0x00 */
43 {_byp, _byp}, /* 0x01 */
44 {_byp, _byp}, /* 0x02 */
45 {_byp, _byp}, /* 0x03 */
46 {_byp, _byp}, /* 0x04 */
47 {_byp, _byp}, /* 0x05 */
48 {_byp, _byp}, /* 0x06 */
49 {_byp, _byp}, /* 0x07 */
50 {_1x, _x2}, /* 0x08 */
51 {_1x, _x4}, /* 0x09 */
52 {_1x, _x8}, /* 0x0A */
53 {_1x, _x8}, /* 0x0B */
54 {_1_5x, _x2}, /* 0x0C */
55 {_1_5x, _x4}, /* 0x0D */
56 {_1_5x, _x8}, /* 0x0E */
57 {_1_5x, _x8}, /* 0x0F */
58 {_2x, _x2}, /* 0x10 */
59 {_2x, _x4}, /* 0x11 */
60 {_2x, _x8}, /* 0x12 */
61 {_2x, _x8}, /* 0x13 */
62 {_2_5x, _x2}, /* 0x14 */
63 {_2_5x, _x4}, /* 0x15 */
64 {_2_5x, _x8}, /* 0x16 */
65 {_2_5x, _x8}, /* 0x17 */
66 {_3x, _x2}, /* 0x18 */
67 {_3x, _x4}, /* 0x19 */
68 {_3x, _x8}, /* 0x1A */
69 {_3x, _x8}, /* 0x1B */
72 /* ----------------------------------------------------------------- */
79 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
84 u32 corecnf_tab_index;
89 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
90 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
94 #elif defined(CONFIG_ARCH_MPC8309)
97 #ifdef CONFIG_ARCH_MPC834X
102 #if !defined(CONFIG_ARCH_MPC832X)
105 #if defined(CONFIG_ARCH_MPC8315)
108 #if defined(CONFIG_FSL_ESDHC)
111 #if !defined(CONFIG_ARCH_MPC8309)
117 #if defined(CONFIG_ARCH_MPC8360)
120 #if defined(CONFIG_QE)
126 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
127 defined(CONFIG_ARCH_MPC837X)
131 #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
135 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
138 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
140 if (im->reset.rcwh & HRCWH_PCI_HOST) {
141 #if defined(CONFIG_SYS_CLK_FREQ)
142 pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
144 pci_sync_in = 0xDEADBEEF;
147 #if defined(CONFIG_83XX_PCICLK)
148 pci_sync_in = CONFIG_83XX_PCICLK;
150 pci_sync_in = 0xDEADBEEF;
154 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
155 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
159 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
160 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
161 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
169 tsec1_clk = csb_clk / 2;
172 tsec1_clk = csb_clk / 3;
175 /* unknown SCCR_TSEC1CM value */
180 #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
181 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
182 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
190 usbdr_clk = csb_clk / 2;
193 usbdr_clk = csb_clk / 3;
196 /* unknown SCCR_USBDRCM value */
201 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
202 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
203 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
211 tsec2_clk = csb_clk / 2;
214 tsec2_clk = csb_clk / 3;
217 /* unknown SCCR_TSEC2CM value */
220 #elif defined(CONFIG_ARCH_MPC8313)
221 tsec2_clk = tsec1_clk;
223 if (!(sccr & SCCR_TSEC1ON))
225 if (!(sccr & SCCR_TSEC2ON))
229 #if defined(CONFIG_ARCH_MPC834X)
230 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
235 usbmph_clk = csb_clk;
238 usbmph_clk = csb_clk / 2;
241 usbmph_clk = csb_clk / 3;
244 /* unknown SCCR_USBMPHCM value */
248 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
249 /* if USB MPH clock is not disabled and
250 * USB DR clock is not disabled then
251 * USB MPH & USB DR must have the same rate
256 #if !defined(CONFIG_ARCH_MPC8309)
257 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
265 enc_clk = csb_clk / 2;
268 enc_clk = csb_clk / 3;
271 /* unknown SCCR_ENCCM value */
276 #if defined(CONFIG_FSL_ESDHC)
277 switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
285 sdhc_clk = csb_clk / 2;
288 sdhc_clk = csb_clk / 3;
291 /* unknown SCCR_SDHCCM value */
295 #if defined(CONFIG_ARCH_MPC8315)
296 switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
304 tdm_clk = csb_clk / 2;
307 tdm_clk = csb_clk / 3;
310 /* unknown SCCR_TDMCM value */
315 #if defined(CONFIG_ARCH_MPC834X)
316 i2c1_clk = tsec2_clk;
317 #elif defined(CONFIG_ARCH_MPC8360)
319 #elif defined(CONFIG_ARCH_MPC832X)
321 #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
323 #elif defined(CONFIG_FSL_ESDHC)
325 #elif defined(CONFIG_ARCH_MPC837X)
327 #elif defined(CONFIG_ARCH_MPC8309)
330 #if !defined(CONFIG_ARCH_MPC832X)
331 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
334 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
335 defined(CONFIG_ARCH_MPC837X)
336 switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
341 pciexp1_clk = csb_clk;
344 pciexp1_clk = csb_clk / 2;
347 pciexp1_clk = csb_clk / 3;
350 /* unknown SCCR_PCIEXP1CM value */
354 switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
359 pciexp2_clk = csb_clk;
362 pciexp2_clk = csb_clk / 2;
365 pciexp2_clk = csb_clk / 3;
368 /* unknown SCCR_PCIEXP2CM value */
373 #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
374 switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
382 sata_clk = csb_clk / 2;
385 sata_clk = csb_clk / 3;
388 /* unknown SCCR_SATA1CM value */
394 (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
395 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
400 lclk_clk = lbiu_clk / lcrr;
408 (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
409 corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
411 #if defined(CONFIG_ARCH_MPC8360)
412 mem_sec_clk = csb_clk * (1 +
413 ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
416 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
417 if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
418 /* corecnf_tab_index is too high, possibly wrong value */
421 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
428 core_clk = (3 * csb_clk) / 2;
431 core_clk = 2 * csb_clk;
434 core_clk = (5 * csb_clk) / 2;
437 core_clk = 3 * csb_clk;
440 /* unknown core to csb ratio */
444 #if defined(CONFIG_QE)
445 qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
446 qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
447 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
448 brg_clk = qe_clk / 2;
451 gd->arch.csb_clk = csb_clk;
452 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
453 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
454 gd->arch.tsec1_clk = tsec1_clk;
455 gd->arch.tsec2_clk = tsec2_clk;
456 gd->arch.usbdr_clk = usbdr_clk;
457 #elif defined(CONFIG_ARCH_MPC8309)
458 gd->arch.usbdr_clk = usbdr_clk;
460 #if defined(CONFIG_ARCH_MPC834X)
461 gd->arch.usbmph_clk = usbmph_clk;
463 #if defined(CONFIG_ARCH_MPC8315)
464 gd->arch.tdm_clk = tdm_clk;
466 #if defined(CONFIG_FSL_ESDHC)
467 gd->arch.sdhc_clk = sdhc_clk;
469 gd->arch.core_clk = core_clk;
470 gd->arch.i2c1_clk = i2c1_clk;
471 #if !defined(CONFIG_ARCH_MPC832X)
472 gd->arch.i2c2_clk = i2c2_clk;
474 #if !defined(CONFIG_ARCH_MPC8309)
475 gd->arch.enc_clk = enc_clk;
477 gd->arch.lbiu_clk = lbiu_clk;
478 gd->arch.lclk_clk = lclk_clk;
479 gd->mem_clk = mem_clk;
480 #if defined(CONFIG_ARCH_MPC8360)
481 gd->arch.mem_sec_clk = mem_sec_clk;
483 #if defined(CONFIG_QE)
484 gd->arch.qe_clk = qe_clk;
485 gd->arch.brg_clk = brg_clk;
487 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
488 defined(CONFIG_ARCH_MPC837X)
489 gd->arch.pciexp1_clk = pciexp1_clk;
490 gd->arch.pciexp2_clk = pciexp2_clk;
492 #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
493 gd->arch.sata_clk = sata_clk;
495 gd->pci_clk = pci_sync_in;
496 gd->cpu_clk = gd->arch.core_clk;
497 gd->bus_clk = gd->arch.csb_clk;
502 /********************************************
504 * return system bus freq in Hz
505 *********************************************/
506 ulong get_bus_freq(ulong dummy)
508 return gd->arch.csb_clk;
511 /********************************************
513 * return ddr bus freq in Hz
514 *********************************************/
515 ulong get_ddr_freq(ulong dummy)
520 int get_serial_clock(void)
522 return get_bus_freq(0);
525 static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
529 printf("Clock configuration:\n");
530 printf(" Core: %-4s MHz\n",
531 strmhz(buf, gd->arch.core_clk));
532 printf(" Coherent System Bus: %-4s MHz\n",
533 strmhz(buf, gd->arch.csb_clk));
534 #if defined(CONFIG_QE)
535 printf(" QE: %-4s MHz\n",
536 strmhz(buf, gd->arch.qe_clk));
537 printf(" BRG: %-4s MHz\n",
538 strmhz(buf, gd->arch.brg_clk));
540 printf(" Local Bus Controller:%-4s MHz\n",
541 strmhz(buf, gd->arch.lbiu_clk));
542 printf(" Local Bus: %-4s MHz\n",
543 strmhz(buf, gd->arch.lclk_clk));
544 printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
545 #if defined(CONFIG_ARCH_MPC8360)
546 printf(" DDR Secondary: %-4s MHz\n",
547 strmhz(buf, gd->arch.mem_sec_clk));
549 #if !defined(CONFIG_ARCH_MPC8309)
550 printf(" SEC: %-4s MHz\n",
551 strmhz(buf, gd->arch.enc_clk));
553 printf(" I2C1: %-4s MHz\n",
554 strmhz(buf, gd->arch.i2c1_clk));
555 #if !defined(CONFIG_ARCH_MPC832X)
556 printf(" I2C2: %-4s MHz\n",
557 strmhz(buf, gd->arch.i2c2_clk));
559 #if defined(CONFIG_ARCH_MPC8315)
560 printf(" TDM: %-4s MHz\n",
561 strmhz(buf, gd->arch.tdm_clk));
563 #if defined(CONFIG_FSL_ESDHC)
564 printf(" SDHC: %-4s MHz\n",
565 strmhz(buf, gd->arch.sdhc_clk));
567 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
568 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
569 printf(" TSEC1: %-4s MHz\n",
570 strmhz(buf, gd->arch.tsec1_clk));
571 printf(" TSEC2: %-4s MHz\n",
572 strmhz(buf, gd->arch.tsec2_clk));
573 printf(" USB DR: %-4s MHz\n",
574 strmhz(buf, gd->arch.usbdr_clk));
575 #elif defined(CONFIG_ARCH_MPC8309)
576 printf(" USB DR: %-4s MHz\n",
577 strmhz(buf, gd->arch.usbdr_clk));
579 #if defined(CONFIG_ARCH_MPC834X)
580 printf(" USB MPH: %-4s MHz\n",
581 strmhz(buf, gd->arch.usbmph_clk));
583 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
584 defined(CONFIG_ARCH_MPC837X)
585 printf(" PCIEXP1: %-4s MHz\n",
586 strmhz(buf, gd->arch.pciexp1_clk));
587 printf(" PCIEXP2: %-4s MHz\n",
588 strmhz(buf, gd->arch.pciexp2_clk));
590 #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
591 printf(" SATA: %-4s MHz\n",
592 strmhz(buf, gd->arch.sata_clk));
597 U_BOOT_CMD(clocks, 1, 0, do_clocks,
598 "print clock configuration",