2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 /* ----------------------------------------------------------------- */
51 mult_t core_csb_ratio;
55 static corecnf_t corecnf_tab[] = {
56 {_byp, _byp}, /* 0x00 */
57 {_byp, _byp}, /* 0x01 */
58 {_byp, _byp}, /* 0x02 */
59 {_byp, _byp}, /* 0x03 */
60 {_byp, _byp}, /* 0x04 */
61 {_byp, _byp}, /* 0x05 */
62 {_byp, _byp}, /* 0x06 */
63 {_byp, _byp}, /* 0x07 */
64 {_1x, _x2}, /* 0x08 */
65 {_1x, _x4}, /* 0x09 */
66 {_1x, _x8}, /* 0x0A */
67 {_1x, _x8}, /* 0x0B */
68 {_1_5x, _x2}, /* 0x0C */
69 {_1_5x, _x4}, /* 0x0D */
70 {_1_5x, _x8}, /* 0x0E */
71 {_1_5x, _x8}, /* 0x0F */
72 {_2x, _x2}, /* 0x10 */
73 {_2x, _x4}, /* 0x11 */
74 {_2x, _x8}, /* 0x12 */
75 {_2x, _x8}, /* 0x13 */
76 {_2_5x, _x2}, /* 0x14 */
77 {_2_5x, _x4}, /* 0x15 */
78 {_2_5x, _x8}, /* 0x16 */
79 {_2_5x, _x8}, /* 0x17 */
80 {_3x, _x2}, /* 0x18 */
81 {_3x, _x4}, /* 0x19 */
82 {_3x, _x8}, /* 0x1A */
83 {_3x, _x8}, /* 0x1B */
86 /* ----------------------------------------------------------------- */
93 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
98 u32 corecnf_tab_index;
103 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
104 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
108 #elif defined(CONFIG_MPC8309)
111 #ifdef CONFIG_MPC834x
116 #if !defined(CONFIG_MPC832x)
119 #if defined(CONFIG_MPC8315)
122 #if defined(CONFIG_FSL_ESDHC)
125 #if !defined(CONFIG_MPC8309)
131 #if defined(CONFIG_MPC8360)
134 #if defined(CONFIG_QE)
140 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
141 defined(CONFIG_MPC837x)
145 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
149 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
152 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
154 if (im->reset.rcwh & HRCWH_PCI_HOST) {
155 #if defined(CONFIG_83XX_CLKIN)
156 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
158 pci_sync_in = 0xDEADBEEF;
161 #if defined(CONFIG_83XX_PCICLK)
162 pci_sync_in = CONFIG_83XX_PCICLK;
164 pci_sync_in = 0xDEADBEEF;
168 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
169 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
173 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
174 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
175 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
183 tsec1_clk = csb_clk / 2;
186 tsec1_clk = csb_clk / 3;
189 /* unkown SCCR_TSEC1CM value */
194 #if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
195 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
196 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
204 usbdr_clk = csb_clk / 2;
207 usbdr_clk = csb_clk / 3;
210 /* unkown SCCR_USBDRCM value */
215 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
216 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
217 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
225 tsec2_clk = csb_clk / 2;
228 tsec2_clk = csb_clk / 3;
231 /* unkown SCCR_TSEC2CM value */
234 #elif defined(CONFIG_MPC8313)
235 tsec2_clk = tsec1_clk;
237 if (!(sccr & SCCR_TSEC1ON))
239 if (!(sccr & SCCR_TSEC2ON))
243 #if defined(CONFIG_MPC834x)
244 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
249 usbmph_clk = csb_clk;
252 usbmph_clk = csb_clk / 2;
255 usbmph_clk = csb_clk / 3;
258 /* unkown SCCR_USBMPHCM value */
262 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
263 /* if USB MPH clock is not disabled and
264 * USB DR clock is not disabled then
265 * USB MPH & USB DR must have the same rate
270 #if !defined(CONFIG_MPC8309)
271 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
279 enc_clk = csb_clk / 2;
282 enc_clk = csb_clk / 3;
285 /* unkown SCCR_ENCCM value */
290 #if defined(CONFIG_FSL_ESDHC)
291 switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
299 sdhc_clk = csb_clk / 2;
302 sdhc_clk = csb_clk / 3;
305 /* unkown SCCR_SDHCCM value */
309 #if defined(CONFIG_MPC8315)
310 switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
318 tdm_clk = csb_clk / 2;
321 tdm_clk = csb_clk / 3;
324 /* unkown SCCR_TDMCM value */
329 #if defined(CONFIG_MPC834x)
330 i2c1_clk = tsec2_clk;
331 #elif defined(CONFIG_MPC8360)
333 #elif defined(CONFIG_MPC832x)
335 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
337 #elif defined(CONFIG_FSL_ESDHC)
339 #elif defined(CONFIG_MPC837x)
341 #elif defined(CONFIG_MPC8309)
344 #if !defined(CONFIG_MPC832x)
345 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
348 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
349 defined(CONFIG_MPC837x)
350 switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
355 pciexp1_clk = csb_clk;
358 pciexp1_clk = csb_clk / 2;
361 pciexp1_clk = csb_clk / 3;
364 /* unkown SCCR_PCIEXP1CM value */
368 switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
373 pciexp2_clk = csb_clk;
376 pciexp2_clk = csb_clk / 2;
379 pciexp2_clk = csb_clk / 3;
382 /* unkown SCCR_PCIEXP2CM value */
387 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
388 switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
396 sata_clk = csb_clk / 2;
399 sata_clk = csb_clk / 3;
402 /* unkown SCCR_SATACM value */
408 (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
409 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
414 lclk_clk = lbiu_clk / lcrr;
422 (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
423 corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
425 #if defined(CONFIG_MPC8360)
426 mem_sec_clk = csb_clk * (1 +
427 ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
430 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
431 if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
432 /* corecnf_tab_index is too high, possibly worng value */
435 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
442 core_clk = (3 * csb_clk) / 2;
445 core_clk = 2 * csb_clk;
448 core_clk = (5 * csb_clk) / 2;
451 core_clk = 3 * csb_clk;
454 /* unkown core to csb ratio */
458 #if defined(CONFIG_QE)
459 qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
460 qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
461 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
462 brg_clk = qe_clk / 2;
465 gd->csb_clk = csb_clk;
466 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
467 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
468 gd->tsec1_clk = tsec1_clk;
469 gd->tsec2_clk = tsec2_clk;
470 gd->usbdr_clk = usbdr_clk;
471 #elif defined(CONFIG_MPC8309)
472 gd->usbdr_clk = usbdr_clk;
474 #if defined(CONFIG_MPC834x)
475 gd->usbmph_clk = usbmph_clk;
477 #if defined(CONFIG_MPC8315)
478 gd->tdm_clk = tdm_clk;
480 #if defined(CONFIG_FSL_ESDHC)
481 gd->sdhc_clk = sdhc_clk;
483 gd->core_clk = core_clk;
484 gd->i2c1_clk = i2c1_clk;
485 #if !defined(CONFIG_MPC832x)
486 gd->i2c2_clk = i2c2_clk;
488 #if !defined(CONFIG_MPC8309)
489 gd->enc_clk = enc_clk;
491 gd->lbiu_clk = lbiu_clk;
492 gd->lclk_clk = lclk_clk;
493 gd->mem_clk = mem_clk;
494 #if defined(CONFIG_MPC8360)
495 gd->mem_sec_clk = mem_sec_clk;
497 #if defined(CONFIG_QE)
499 gd->arch.brg_clk = brg_clk;
501 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
502 defined(CONFIG_MPC837x)
503 gd->pciexp1_clk = pciexp1_clk;
504 gd->pciexp2_clk = pciexp2_clk;
506 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
507 gd->sata_clk = sata_clk;
509 gd->pci_clk = pci_sync_in;
510 gd->cpu_clk = gd->core_clk;
511 gd->bus_clk = gd->csb_clk;
516 /********************************************
518 * return system bus freq in Hz
519 *********************************************/
520 ulong get_bus_freq(ulong dummy)
525 /********************************************
527 * return ddr bus freq in Hz
528 *********************************************/
529 ulong get_ddr_freq(ulong dummy)
534 static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
538 printf("Clock configuration:\n");
539 printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk));
540 printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
541 #if defined(CONFIG_QE)
542 printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk));
543 printf(" BRG: %-4s MHz\n",
544 strmhz(buf, gd->arch.brg_clk));
546 printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
547 printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk));
548 printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
549 #if defined(CONFIG_MPC8360)
550 printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
552 #if !defined(CONFIG_MPC8309)
553 printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk));
555 printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
556 #if !defined(CONFIG_MPC832x)
557 printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
559 #if defined(CONFIG_MPC8315)
560 printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk));
562 #if defined(CONFIG_FSL_ESDHC)
563 printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
565 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
566 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
567 printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
568 printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
569 printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
570 #elif defined(CONFIG_MPC8309)
571 printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
573 #if defined(CONFIG_MPC834x)
574 printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
576 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
577 defined(CONFIG_MPC837x)
578 printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
579 printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
581 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
582 printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk));
587 U_BOOT_CMD(clocks, 1, 0, do_clocks,
588 "print clock configuration",