1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) Freescale Semiconductor, Inc. 2007
5 * Author: Scott Wood <scottwood@freescale.com>,
6 * with some bits from older board-specific PCI initialization.
12 #include <asm/bitops.h>
13 #include <linux/delay.h>
15 #if defined(CONFIG_OF_LIBFDT)
16 #include <linux/libfdt.h>
17 #include <fdt_support.h>
20 #include <asm/mpc8349_pci.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 static struct pci_controller pci_hose[MAX_BUSES];
27 static int pci_num_buses;
29 static void pci_init_bus(int bus, struct pci_region *reg)
31 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
32 volatile pot83xx_t *pot = immr->ios.pot;
33 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
34 struct pci_controller *hose = &pci_hose[bus];
42 /* Setup outbound translation windows */
43 for (i = 0; i < 3; i++, reg++, pot++) {
47 hose->regions[i] = *reg;
50 pot->potar = reg->bus_start >> 12;
51 pot->pobar = reg->phys_start >> 12;
52 pot->pocmr = ~(reg->size - 1) >> 12;
54 if (reg->flags & PCI_REGION_IO)
55 pot->pocmr |= POCMR_IO;
56 #ifdef CONFIG_83XX_PCI_STREAMING
57 else if (reg->flags & PCI_REGION_PREFETCH)
58 pot->pocmr |= POCMR_SE;
62 pot->pocmr |= POCMR_DST;
64 pot->pocmr |= POCMR_EN;
67 /* Point inbound translation at RAM */
70 pci_ctrl->piebar1 = 0;
71 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
72 PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
74 i = hose->region_count++;
75 hose->regions[i].bus_start = 0;
76 hose->regions[i].phys_start = 0;
77 hose->regions[i].size = gd->ram_size;
78 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
80 hose->first_busno = pci_last_busno() + 1;
81 hose->last_busno = 0xff;
83 pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
84 CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
86 pci_register_hose(hose);
89 * Write to Command register
92 dev = PCI_BDF(hose->first_busno, 0, 0);
93 pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
94 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
95 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
98 * Clear non-reserved bits in status register.
100 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
101 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
102 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
104 #ifdef CONFIG_PCI_SCAN_SHOW
105 printf("PCI: Bus Dev VenId DevId Class Int\n");
107 #ifndef CONFIG_PCISLAVE
111 hose->last_busno = pci_hose_scan(hose);
116 * The caller must have already set OCCR, and the PCI_LAW BARs
117 * must have been set to cover all of the requested regions.
119 * If fewer than three regions are requested, then the region
120 * list is terminated with a region of size 0.
122 void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
124 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
127 if (num_buses > MAX_BUSES) {
128 printf("%d PCI buses requested, %d supported\n",
129 num_buses, MAX_BUSES);
131 num_buses = MAX_BUSES;
134 pci_num_buses = num_buses;
137 * Release PCI RST Output signal.
138 * Power on to RST high must be at least 100 ms as per PCI spec.
139 * On warm boots only 1 ms is required, but we play it safe.
143 for (i = 0; i < num_buses; i++)
144 immr->pci_ctrl[i].gcr = 1;
147 * RST high to first config access must be at least 2^25 cycles
148 * as per PCI spec. This could be cut in half if we know we're
149 * running at 66MHz. This could be insufficiently long if we're
150 * running the PCI bus at significantly less than 33MHz.
154 for (i = 0; i < num_buses; i++)
155 pci_init_bus(i, reg[i]);
158 #ifdef CONFIG_PCISLAVE
160 #define PCI_FUNCTION_CONFIG 0x44
161 #define PCI_FUNCTION_CFG_LOCK 0x20
164 * Unlock the configuration bit so that the host system can begin booting
166 * This should be used after you have:
167 * 1) Called mpc83xx_pci_init()
168 * 2) Set up your inbound translation windows to the appropriate size
170 void mpc83xx_pcislave_unlock(int bus)
172 struct pci_controller *hose = &pci_hose[bus];
176 /* Unlock configuration lock in PCI function configuration register */
177 dev = PCI_BDF(hose->first_busno, 0, 0);
178 pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, ®16);
179 reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
180 pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
182 /* The configuration bit is now unlocked, so we can scan the bus */
183 hose->last_busno = pci_hose_scan(hose);
187 #if defined(CONFIG_OF_LIBFDT)
188 void ft_pci_setup(void *blob, bd_t *bd)
194 if (pci_num_buses < 1)
197 nodeoffset = fdt_path_offset(blob, "/aliases");
198 if (nodeoffset >= 0) {
199 path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
201 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
202 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
203 do_fixup_by_path(blob, path, "bus-range",
204 &tmp, sizeof(tmp), 1);
206 tmp[0] = cpu_to_be32(gd->pci_clk);
207 do_fixup_by_path(blob, path, "clock-frequency",
208 &tmp, sizeof(tmp[0]), 1);
211 if (pci_num_buses < 2)
214 path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
216 tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
217 tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
218 do_fixup_by_path(blob, path, "bus-range",
219 &tmp, sizeof(tmp), 1);
221 tmp[0] = cpu_to_be32(gd->pci_clk);
222 do_fixup_by_path(blob, path, "clock-frequency",
223 &tmp, sizeof(tmp[0]), 1);
227 #endif /* CONFIG_OF_LIBFDT */