arch/powerpc/cpu/mpc83xx/cpu_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <mpc83xx.h>
   8 #include <ioports.h>
   9 #include <asm/io.h>
  10 #include <asm/processor.h>
  11 #ifdef CONFIG_USB_EHCI_FSL
  12 #include <usb/ehci-ci.h>
  13 #endif
  14
  15 #include "lblaw/lblaw.h"
  16 #include "elbc/elbc.h"
  17 #include "sysio/sysio.h"
  18 #include "arbiter/arbiter.h"
  19 #include "initreg/initreg.h"
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #ifdef CONFIG_QE
  24 extern qe_iop_conf_t qe_iop_conf_tab[];
  25 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  26                          int open_drain, int assign);
  27 extern void qe_init(uint qe_base);
  28 extern void qe_reset(void);
  29
  30 static void config_qe_ioports(void)
  31 {
  32         u8      port, pin;
  33         int     dir, open_drain, assign;
  34         int     i;
  35
  36         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  37                 port            = qe_iop_conf_tab[i].port;
  38                 pin             = qe_iop_conf_tab[i].pin;
  39                 dir             = qe_iop_conf_tab[i].dir;
  40                 open_drain      = qe_iop_conf_tab[i].open_drain;
  41                 assign          = qe_iop_conf_tab[i].assign;
  42                 qe_config_iopin(port, pin, dir, open_drain, assign);
  43         }
  44 }
  45 #endif
  46
  47 /*
  48  * Breathe some life into the CPU...
  49  *
  50  * Set up the memory map,
  51  * initialize a bunch of registers,
  52  * initialize the UPM's
  53  */
  54 void cpu_init_f (volatile immap_t * im)
  55 {
  56         __be32 sccr_mask =
  57 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  58                 SCCR_ENCCM |
  59 #endif
  60 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  61                 SCCR_PCICM |
  62 #endif
  63 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
  64                 SCCR_PCIEXP1CM |
  65 #endif
  66 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
  67                 SCCR_PCIEXP2CM |
  68 #endif
  69 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  70                 SCCR_TSECCM |
  71 #endif
  72 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
  73                 SCCR_TSEC1CM |
  74 #endif
  75 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
  76                 SCCR_TSEC2CM |
  77 #endif
  78 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
  79                 SCCR_TSEC1ON |
  80 #endif
  81 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
  82                 SCCR_TSEC2ON |
  83 #endif
  84 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
  85                 SCCR_USBMPHCM |
  86 #endif
  87 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
  88                 SCCR_USBDRCM |
  89 #endif
  90 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
  91                 SCCR_SATACM |
  92 #endif
  93                 0;
  94         __be32 sccr_val =
  95 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  96                 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
  97 #endif
  98 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  99                 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
 100 #endif
 101 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
 102                 (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
 103 #endif
 104 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
 105                 (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
 106 #endif
 107 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 108                 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 109 #endif
 110 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 111                 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 112 #endif
 113 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 114                 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 115 #endif
 116 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 117                 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 118 #endif
 119 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 120                 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 121 #endif
 122 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 123                 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 124 #endif
 125 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 126                 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 127 #endif
 128 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 129                 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 130 #endif
 131                 0;
 132
 133         /* Pointer is writable since we allocated a register for it */
 134         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 135
 136         /* global data region was cleared in start.S */
 137
 138         /* system performance tweaking */
 139         clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
 140
 141         clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
 142
 143         clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 144
 145         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 146         gd->arch.reset_status = __raw_readl(&im->reset.rsr);
 147         __raw_writel(~(RSR_RES), &im->reset.rsr);
 148
 149         /* AER - Arbiter Event Register - store status */
 150         gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
 151         gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 152
 153         /*
 154          * RMR - Reset Mode Register
 155          * contains checkstop reset enable (4.6.1.4)
 156          */
 157         __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 158
 159         /* LCRR - Clock Ratio Register (10.3.1.16)
 160          * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
 161          */
 162         clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
 163         __raw_readl(&im->im_lbc.lcrr);
 164         isync();
 165
 166         /* Enable Time Base & Decrementer ( so we will have udelay() )*/
 167         setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 168
 169         /* System General Purpose Register */
 170 #ifdef CONFIG_SYS_SICRH
 171 #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
 172         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 173         __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
 174                      &im->sysconf.sicrh);
 175 #else
 176         __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
 177 #endif
 178 #endif
 179 #ifdef CONFIG_SYS_SICRL
 180         __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 181 #endif
 182 #ifdef CONFIG_SYS_GPR1
 183         __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
 184 #endif
 185 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
 186         __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 187 #endif
 188 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
 189         __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
 190 #endif
 191
 192 #ifdef CONFIG_QE
 193         /* Config QE ioports */
 194         config_qe_ioports();
 195 #endif
 196         /* Set up preliminary BR/OR regs */
 197         init_early_memctl_regs();
 198
 199         /* Local Access window setup */
 200 #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
 201         im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
 202         im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
 203 #else
 204 #error  CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
 205 #endif
 206
 207 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
 208         im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
 209         im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
 210 #endif
 211 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 212         im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
 213         im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
 214 #endif
 215 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
 216         im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
 217         im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
 218 #endif
 219 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
 220         im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
 221         im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
 222 #endif
 223 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
 224         im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
 225         im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
 226 #endif
 227 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
 228         im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
 229         im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
 230 #endif
 231 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
 232         im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
 233         im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
 234 #endif
 235 #ifdef CONFIG_SYS_GPIO1_PRELIM
 236         im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
 237         im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
 238 #endif
 239 #ifdef CONFIG_SYS_GPIO2_PRELIM
 240         im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 241         im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 242 #endif
 243 #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
 244         uint32_t temp;
 245         struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
 246
 247         /* Configure interface. */
 248         setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
 249
 250         /* Wait for clock to stabilize */
 251         do {
 252                 temp = __raw_readl(&ehci->control);
 253                 udelay(1000);
 254         } while (!(temp & PHY_CLK_VALID));
 255 #endif
 256 }
 257
 258 int cpu_init_r (void)
 259 {
 260 #ifdef CONFIG_QE
 261         uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
 262
 263         qe_init(qe_base);
 264         qe_reset();
 265 #endif
 266         return 0;
 267 }
 268
 269 /*
 270  * Print out the bus arbiter event
 271  */
 272 #if defined(CONFIG_DISPLAY_AER_FULL)
 273 static int print_83xx_arb_event(int force)
 274 {
 275         static char* event[] = {
 276                 "Address Time Out",
 277                 "Data Time Out",
 278                 "Address Only Transfer Type",
 279                 "External Control Word Transfer Type",
 280                 "Reserved Transfer Type",
 281                 "Transfer Error",
 282                 "reserved",
 283                 "reserved"
 284         };
 285         static char* master[] = {
 286                 "e300 Core Data Transaction",
 287                 "reserved",
 288                 "e300 Core Instruction Fetch",
 289                 "reserved",
 290                 "TSEC1",
 291                 "TSEC2",
 292                 "USB MPH",
 293                 "USB DR",
 294                 "Encryption Core",
 295                 "I2C Boot Sequencer",
 296                 "JTAG",
 297                 "reserved",
 298                 "eSDHC",
 299                 "PCI1",
 300                 "PCI2",
 301                 "DMA",
 302                 "QUICC Engine 00",
 303                 "QUICC Engine 01",
 304                 "QUICC Engine 10",
 305                 "QUICC Engine 11",
 306                 "reserved",
 307                 "reserved",
 308                 "reserved",
 309                 "reserved",
 310                 "SATA1",
 311                 "SATA2",
 312                 "SATA3",
 313                 "SATA4",
 314                 "reserved",
 315                 "PCI Express 1",
 316                 "PCI Express 2",
 317                 "TDM-DMAC"
 318         };
 319         static char *transfer[] = {
 320                 "Address-only, Clean Block",
 321                 "Address-only, lwarx reservation set",
 322                 "Single-beat or Burst write",
 323                 "reserved",
 324                 "Address-only, Flush Block",
 325                 "reserved",
 326                 "Burst write",
 327                 "reserved",
 328                 "Address-only, sync",
 329                 "Address-only, tlbsync",
 330                 "Single-beat or Burst read",
 331                 "Single-beat or Burst read",
 332                 "Address-only, Kill Block",
 333                 "Address-only, icbi",
 334                 "Burst read",
 335                 "reserved",
 336                 "Address-only, eieio",
 337                 "reserved",
 338                 "Single-beat write",
 339                 "reserved",
 340                 "ecowx - Illegal single-beat write",
 341                 "reserved",
 342                 "reserved",
 343                 "reserved",
 344                 "Address-only, TLB Invalidate",
 345                 "reserved",
 346                 "Single-beat or Burst read",
 347                 "reserved",
 348                 "eciwx - Illegal single-beat read",
 349                 "reserved",
 350                 "Burst read",
 351                 "reserved"
 352         };
 353
 354         int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
 355                     >> AEATR_EVENT_SHIFT;
 356         int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
 357                       >> AEATR_MSTR_ID_SHIFT;
 358         int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
 359                    >> AEATR_TBST_SHIFT;
 360         int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
 361                     >> AEATR_TSIZE_SHIFT;
 362         int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
 363                     >> AEATR_TTYPE_SHIFT;
 364
 365         if (!force && !gd->arch.arbiter_event_address)
 366                 return 0;
 367
 368         puts("Arbiter Event Status:\n");
 369         printf("       Event Address: 0x%08lX\n",
 370                gd->arch.arbiter_event_address);
 371         printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 372         printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 373         printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 374                                 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 375         printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 376
 377         return gd->arch.arbiter_event_address;
 378 }
 379
 380 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 381
 382 static int print_83xx_arb_event(int force)
 383 {
 384         if (!force && !gd->arch.arbiter_event_address)
 385                 return 0;
 386
 387         printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
 388                 gd->arch.arbiter_event_attributes,
 389                 gd->arch.arbiter_event_address);
 390
 391         return gd->arch.arbiter_event_address;
 392 }
 393 #endif /* CONFIG_DISPLAY_AER_xxxx */
 394
 395 #ifndef CONFIG_CPU_MPC83XX
 396 /*
 397  * Figure out the cause of the reset
 398  */
 399 int prt_83xx_rsr(void)
 400 {
 401         static struct {
 402                 ulong mask;
 403                 char *desc;
 404         } bits[] = {
 405                 {
 406                 RSR_SWSR, "Software Soft"}, {
 407                 RSR_SWHR, "Software Hard"}, {
 408                 RSR_JSRS, "JTAG Soft"}, {
 409                 RSR_CSHR, "Check Stop"}, {
 410                 RSR_SWRS, "Software Watchdog"}, {
 411                 RSR_BMRS, "Bus Monitor"}, {
 412                 RSR_SRS,  "External/Internal Soft"}, {
 413                 RSR_HRS,  "External/Internal Hard"}
 414         };
 415         static int n = ARRAY_SIZE(bits);
 416         ulong rsr = gd->arch.reset_status;
 417         int i;
 418         char *sep;
 419
 420         puts("Reset Status:");
 421
 422         sep = " ";
 423         for (i = 0; i < n; i++)
 424                 if (rsr & bits[i].mask) {
 425                         printf("%s%s", sep, bits[i].desc);
 426                         sep = ", ";
 427                 }
 428         puts("\n");
 429
 430 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
 431         print_83xx_arb_event(rsr & RSR_BMRS);
 432 #endif
 433         puts("\n");
 434
 435         return 0;
 436 }
 437 #endif