2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
37 #include <fsl_esdhc.h>
38 #ifdef CONFIG_BOOTCOUNT_LIMIT
39 #include <asm/immap_qe.h>
43 DECLARE_GLOBAL_DATA_PTR;
47 volatile immap_t *immr;
48 ulong clock = gd->cpu_clk;
54 const struct cpu_type {
57 } cpu_type_list [] = {
67 CPU_TYPE_ENTRY(8347_TBGA_),
68 CPU_TYPE_ENTRY(8347_PBGA_),
70 CPU_TYPE_ENTRY(8358_TBGA_),
71 CPU_TYPE_ENTRY(8358_PBGA_),
78 immr = (immap_t *)CONFIG_SYS_IMMR;
82 switch (pvr & 0xffff0000) {
100 printf("Unknown core, ");
103 spridr = immr->sysconf.spridr;
105 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
106 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
108 puts(cpu_type_list[i].name);
109 if (IS_E_PROCESSOR(spridr))
111 if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
112 SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
113 REVID_MAJOR(spridr) >= 2)
115 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
116 REVID_MINOR(spridr));
120 if (i == ARRAY_SIZE(cpu_type_list))
121 printf("(SPRIDR %08x unknown), ", spridr);
123 printf(" at %s MHz, ", strmhz(buf, clock));
125 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
131 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
134 #ifndef MPC83xx_RESET
138 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
140 puts("Resetting the board.\n");
144 /* Interrupts and MMU off */
145 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
147 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
148 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
150 /* enable Reset Control Reg */
151 immap->reset.rpr = 0x52535445;
152 __asm__ __volatile__ ("sync");
153 __asm__ __volatile__ ("isync");
155 /* confirm Reset Control Reg is enabled */
156 while(!((immap->reset.rcer) & RCER_CRE));
160 /* perform reset, only one bit */
161 immap->reset.rcr = RCR_SWHR;
163 #else /* ! MPC83xx_RESET */
165 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
167 /* Interrupts and MMU off */
168 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
170 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
171 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
174 * Trying to execute the next instruction at a non-existing address
175 * should cause a machine check, resulting in reset
177 addr = CONFIG_SYS_RESET_ADDRESS;
179 ((void (*)(void)) addr) ();
180 #endif /* MPC83xx_RESET */
187 * Get timebase clock frequency (like cpu_clk in Hz)
190 unsigned long get_tbclk(void)
194 tbclk = (gd->bus_clk + 3L) / 4L;
200 #if defined(CONFIG_WATCHDOG)
201 void watchdog_reset (void)
203 int re_enable = disable_interrupts();
205 /* Reset the 83xx watchdog */
206 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
207 immr->wdt.swsrr = 0x556c;
208 immr->wdt.swsrr = 0xaa39;
211 enable_interrupts ();
216 * Initializes on-chip ethernet controllers.
217 * to override, implement board_eth_init()
219 int cpu_eth_init(bd_t *bis)
221 #if defined(CONFIG_UEC_ETH)
222 uec_standard_init(bis);
225 #if defined(CONFIG_TSEC_ENET)
226 tsec_standard_init(bis);
232 * Initializes on-chip MMC controllers.
233 * to override, implement board_mmc_init()
235 int cpu_mmc_init(bd_t *bis)
237 #ifdef CONFIG_FSL_ESDHC
238 return fsl_esdhc_mmc_init(bis);