2 * Copyright (c) 2001 Navin Boppuri / Prashant Patel
3 * <nboppuri@trinetcommunication.com>,
4 * <pmpatel@trinetcommunication.com>
5 * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
6 * Copyright (c) 2001-2003 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
8 * SPDX-License-Identifier: GPL-2.0+
12 * MPC8260 CPM SPI interface.
14 * Parts of this code are probably not portable and/or specific to
15 * the board which I used for the tests. Please send fixes/complaints
21 #include <asm/cpm_8260.h>
22 #include <linux/ctype.h>
27 #if defined(CONFIG_SPI)
30 * You cannot enable DEBUG for early system initalization, i. e. when
31 * this driver is used to read environment parameters like "baudrate"
32 * from EEPROM which are used to initialize the serial port which is
33 * needed to print the debug messages...
37 #define SPI_EEPROM_WREN 0x06
38 #define SPI_EEPROM_RDSR 0x05
39 #define SPI_EEPROM_READ 0x03
40 #define SPI_EEPROM_WRITE 0x02
42 /* ---------------------------------------------------------------
43 * Offset for initial SPI buffers in DPRAM:
44 * We need a 520 byte scratch DPRAM area to use at an early stage.
45 * It is used between the two initialization calls (spi_init_f()
47 * The value 0x2000 makes it far enough from the start of the data
48 * area (as well as from the stack pointer).
49 * --------------------------------------------------------------- */
50 #ifndef CONFIG_SYS_SPI_INIT_OFFSET
51 #define CONFIG_SYS_SPI_INIT_OFFSET 0x2000
54 #define CPM_SPI_BASE 0x100
58 #define DPRINT(a) printf a;
59 /* -----------------------------------------------
60 * Helper functions to peek into tx and rx buffers
61 * ----------------------------------------------- */
62 static const char * const hex_digit = "0123456789ABCDEF";
64 static char quickhex (int i)
69 static void memdump (void *pv, int num)
72 unsigned char *pc = (unsigned char *) pv;
74 for (i = 0; i < num; i++)
75 printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f));
77 for (i = 0; i < num; i++)
78 printf ("%c", isprint (pc[i]) ? pc[i] : '.');
87 /* -------------------
89 * ------------------- */
92 ssize_t spi_read (uchar *, int, uchar *, int);
93 ssize_t spi_write (uchar *, int, uchar *, int);
94 ssize_t spi_xfer (size_t);
96 /* -------------------
98 * ------------------- */
100 #define MAX_BUFFER 0x104
102 /* ----------------------------------------------------------------------
103 * Initially we place the RX and TX buffers at a fixed location in DPRAM!
104 * ---------------------------------------------------------------------- */
105 static uchar *rxbuf =
106 (uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase
107 [CONFIG_SYS_SPI_INIT_OFFSET];
108 static uchar *txbuf =
109 (uchar *)&((immap_t *)CONFIG_SYS_IMMR)->im_dprambase
110 [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
112 /* **************************************************************************
114 * Function: spi_init_f
116 * Description: Init SPI-Controller (ROM part)
120 * *********************************************************************** */
121 void spi_init_f (void)
126 volatile immap_t *immr;
127 volatile cpm8260_t *cp;
128 volatile cbd_t *tbdf, *rbdf;
130 immr = (immap_t *) CONFIG_SYS_IMMR;
131 cp = (cpm8260_t *) &immr->im_cpm;
133 immr->im_dprambase16[PROFF_SPI_BASE / sizeof(u16)] = PROFF_SPI;
134 spi = (spi_t *)&immr->im_dprambase[PROFF_SPI];
137 /* ------------------------------------------------
138 * Initialize Port D SPI pins
139 * (we are only in Master Mode !)
140 * ------------------------------------------------ */
142 /* --------------------------------------------
143 * GPIO or per. Function
144 * PPARD[16] = 1 [0x00008000] (SPIMISO)
145 * PPARD[17] = 1 [0x00004000] (SPIMOSI)
146 * PPARD[18] = 1 [0x00002000] (SPICLK)
147 * PPARD[12] = 0 [0x00080000] -> GPIO: (CS for ATC EEPROM)
148 * -------------------------------------------- */
149 immr->im_ioport.iop_ppard |= 0x0000E000; /* set bits */
150 immr->im_ioport.iop_ppard &= ~0x00080000; /* reset bit */
152 /* ----------------------------------------------
153 * In/Out or per. Function 0/1
154 * PDIRD[16] = 0 [0x00008000] -> PERI1: SPIMISO
155 * PDIRD[17] = 0 [0x00004000] -> PERI1: SPIMOSI
156 * PDIRD[18] = 0 [0x00002000] -> PERI1: SPICLK
157 * PDIRD[12] = 1 [0x00080000] -> GPIO OUT: CS for ATC EEPROM
158 * ---------------------------------------------- */
159 immr->im_ioport.iop_pdird &= ~0x0000E000;
160 immr->im_ioport.iop_pdird |= 0x00080000;
162 /* ----------------------------------------------
163 * special option reg.
164 * PSORD[16] = 1 [0x00008000] -> SPIMISO
165 * PSORD[17] = 1 [0x00004000] -> SPIMOSI
166 * PSORD[18] = 1 [0x00002000] -> SPICLK
167 * ---------------------------------------------- */
168 immr->im_ioport.iop_psord |= 0x0000E000;
170 /* Initialize the parameter ram.
171 * We need to make sure many things are initialized to zero
184 /* Allocate space for one transmit and one receive buffer
185 * descriptor in the DP ram
187 #ifdef CONFIG_SYS_ALLOC_DPRAM
188 dpaddr = m8260_cpm_dpalloc (sizeof(cbd_t)*2, 8);
190 dpaddr = CPM_SPI_BASE;
194 /* Set up the SPI parameters in the parameter ram */
195 spi->spi_rbase = dpaddr;
196 spi->spi_tbase = dpaddr + sizeof (cbd_t);
198 /***********IMPORTANT******************/
201 * Setting transmit and receive buffer descriptor pointers
202 * initially to rbase and tbase. Only the microcode patches
203 * documentation talks about initializing this pointer. This
204 * is missing from the sample I2C driver. If you dont
205 * initialize these pointers, the kernel hangs.
207 spi->spi_rbptr = spi->spi_rbase;
208 spi->spi_tbptr = spi->spi_tbase;
211 /* Init SPI Tx + Rx Parameters */
212 while (cp->cp_cpcr & CPM_CR_FLG)
214 cp->cp_cpcr = mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK,
215 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
216 while (cp->cp_cpcr & CPM_CR_FLG)
220 /* Set to big endian. */
221 spi->spi_tfcr = CPMFCR_EB;
222 spi->spi_rfcr = CPMFCR_EB;
225 /* Set maximum receive size. */
226 spi->spi_mrblr = MAX_BUFFER;
229 /* tx and rx buffer descriptors */
230 tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase];
231 rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase];
233 tbdf->cbd_sc &= ~BD_SC_READY;
234 rbdf->cbd_sc &= ~BD_SC_EMPTY;
236 /* Set the bd's rx and tx buffer address pointers */
237 rbdf->cbd_bufaddr = (ulong) rxbuf;
238 tbdf->cbd_bufaddr = (ulong) txbuf;
241 immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */
242 immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */
248 /* **************************************************************************
250 * Function: spi_init_r
252 * Description: Init SPI-Controller (RAM part) -
253 * The malloc engine is ready and we can move our buffers to
258 * *********************************************************************** */
259 void spi_init_r (void)
262 volatile immap_t *immr;
263 volatile cbd_t *tbdf, *rbdf;
265 immr = (immap_t *) CONFIG_SYS_IMMR;
267 spi = (spi_t *)&immr->im_dprambase[PROFF_SPI];
269 /* tx and rx buffer descriptors */
270 tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase];
271 rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase];
273 /* Allocate memory for RX and TX buffers */
274 rxbuf = (uchar *) malloc (MAX_BUFFER);
275 txbuf = (uchar *) malloc (MAX_BUFFER);
277 rbdf->cbd_bufaddr = (ulong) rxbuf;
278 tbdf->cbd_bufaddr = (ulong) txbuf;
283 /****************************************************************************
284 * Function: spi_write
285 **************************************************************************** */
286 ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
290 memset(rxbuf, 0, MAX_BUFFER);
291 memset(txbuf, 0, MAX_BUFFER);
292 *txbuf = SPI_EEPROM_WREN; /* write enable */
294 memcpy(txbuf, addr, alen);
295 *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */
296 memcpy(alen + txbuf, buffer, len);
297 spi_xfer(alen + len);
298 /* ignore received data */
299 for (i = 0; i < 1000; i++) {
300 *txbuf = SPI_EEPROM_RDSR; /* read status */
303 if (!(rxbuf[1] & 1)) {
309 printf ("*** spi_write: Time out while writing!\n");
315 /****************************************************************************
317 **************************************************************************** */
318 ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
320 memset(rxbuf, 0, MAX_BUFFER);
321 memset(txbuf, 0, MAX_BUFFER);
322 memcpy(txbuf, addr, alen);
323 *txbuf = SPI_EEPROM_READ; /* READ memory array */
326 * There is a bug in 860T (?) that cuts the last byte of input
327 * if we're reading into DPRAM. The solution we choose here is
328 * to always read len+1 bytes (we have one extra byte at the
329 * end of the buffer).
331 spi_xfer(alen + len + 1);
332 memcpy(buffer, alen + rxbuf, len);
337 /****************************************************************************
339 **************************************************************************** */
340 ssize_t spi_xfer (size_t count)
342 volatile immap_t *immr;
347 DPRINT (("*** spi_xfer entered ***\n"));
349 immr = (immap_t *) CONFIG_SYS_IMMR;
351 spi = (spi_t *)&immr->im_dprambase[PROFF_SPI];
353 tbdf = (cbd_t *) & immr->im_dprambase[spi->spi_tbase];
354 rbdf = (cbd_t *) & immr->im_dprambase[spi->spi_rbase];
356 /* Board-specific: Set CS for device (ATC EEPROM) */
357 immr->im_ioport.iop_pdatd &= ~0x00080000;
359 /* Setting tx bd status and data length */
360 tbdf->cbd_sc = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP;
361 tbdf->cbd_datlen = count;
363 DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n",
366 /* Setting rx bd status and data length */
367 rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
368 rbdf->cbd_datlen = 0; /* rx length has no significance */
370 immr->im_spi.spi_spmode = SPMODE_REV |
373 SPMODE_LEN(8) | /* 8 Bits per char */
374 SPMODE_PM(0x8) ; /* medium speed */
375 immr->im_spi.spi_spie = SPI_EMASK; /* Clear all SPI events */
376 immr->im_spi.spi_spim = 0x00; /* Mask all SPI events */
378 /* start spi transfer */
379 DPRINT (("*** spi_xfer: Performing transfer ...\n"));
380 immr->im_spi.spi_spcom |= SPI_STR; /* Start transmit */
382 /* --------------------------------
383 * Wait for SPI transmit to get out
384 * or time out (1 second = 1000 ms)
385 * -------------------------------- */
386 for (tm=0; tm<1000; ++tm) {
387 if (immr->im_spi.spi_spie & SPI_TXB) { /* Tx Buffer Empty */
388 DPRINT (("*** spi_xfer: Tx buffer empty\n"));
391 if ((tbdf->cbd_sc & BD_SC_READY) == 0) {
392 DPRINT (("*** spi_xfer: Tx BD done\n"));
398 printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
400 DPRINT (("*** spi_xfer: ... transfer ended\n"));
403 printf ("\nspi_xfer: txbuf after xfer\n");
404 memdump ((void *) txbuf, 16); /* dump of txbuf before transmit */
405 printf ("spi_xfer: rxbuf after xfer\n");
406 memdump ((void *) rxbuf, 16); /* dump of rxbuf after transmit */
410 /* Clear CS for device */
411 immr->im_ioport.iop_pdatd |= 0x00080000;
415 #endif /* CONFIG_SPI */