2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
24 * changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the
25 * Linux/PPC sources (m8260_tty.c had no copyright info in it).
29 * Minimal serial functions needed to use one of the SMC ports
30 * as serial console interface.
35 #include <asm/cpm_8260.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 #if defined(CONFIG_CONS_ON_SMC)
41 #if CONFIG_CONS_INDEX == 1 /* Console on SMC1 */
44 #define PROFF_SMC_BASE PROFF_SMC1_BASE
45 #define PROFF_SMC PROFF_SMC1
46 #define CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE
47 #define CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK
48 #define CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
49 #define CMXSMR_VALUE CMXSMR_SMC1CS_BRG7
51 #elif CONFIG_CONS_INDEX == 2 /* Console on SMC2 */
54 #define PROFF_SMC_BASE PROFF_SMC2_BASE
55 #define PROFF_SMC PROFF_SMC2
56 #define CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE
57 #define CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK
58 #define CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
59 #define CMXSMR_VALUE CMXSMR_SMC2CS_BRG8
63 #error "console not correctly defined"
67 #if !defined(CONFIG_SYS_SMC_RXBUFLEN)
68 #define CONFIG_SYS_SMC_RXBUFLEN 1
69 #define CONFIG_SYS_MAXIDLE 0
71 #if !defined(CONFIG_SYS_MAXIDLE)
72 #error "you must define CONFIG_SYS_MAXIDLE"
76 typedef volatile struct serialbuffer {
77 cbd_t rxbd; /* Rx BD */
78 cbd_t txbd; /* Tx BD */
79 uint rxindex; /* index for next character to read */
80 volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
81 volatile uchar txbuf; /* tx buffers */
84 /* map rs_table index to baud rate generator index */
85 static unsigned char brg_map[] = {
86 6, /* BRG7 for SMC1 */
87 7, /* BRG8 for SMC2 */
88 0, /* BRG1 for SCC1 */
89 1, /* BRG1 for SCC2 */
90 2, /* BRG1 for SCC3 */
91 3, /* BRG1 for SCC4 */
94 int serial_init (void)
96 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
98 volatile smc_uart_t *up;
99 volatile cpm8260_t *cp = &(im->im_cpm);
101 volatile serialbuffer_t *rtx;
103 /* initialize pointers to SMC */
105 sp = (smc_t *) &(im->im_smc[SMC_INDEX]);
106 *(ushort *)(&im->im_dprambase[PROFF_SMC_BASE]) = PROFF_SMC;
107 up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC];
109 /* Disable transmitter/receiver. */
110 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
112 /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
114 /* Allocate space for two buffer descriptors in the DP ram.
115 * damm: allocating space after the two buffers for rx/tx data
118 /* allocate size of struct serialbuffer with bd rx/tx,
119 * buffer rx/tx and rx index
121 dpaddr = m8260_cpm_dpalloc((sizeof(serialbuffer_t)), 16);
123 rtx = (serialbuffer_t *)&im->im_dprambase[dpaddr];
125 /* Set the physical address of the host memory buffers in
126 * the buffer descriptors.
128 rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
129 rtx->rxbd.cbd_sc = 0;
131 rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
132 rtx->txbd.cbd_sc = 0;
134 /* Set up the uart parameters in the parameter ram. */
135 up->smc_rbase = dpaddr;
136 up->smc_tbase = dpaddr+sizeof(cbd_t);
137 up->smc_rfcr = CPMFCR_EB;
138 up->smc_tfcr = CPMFCR_EB;
143 /* Set UART mode, 8 bit, no parity, one stop.
144 * Enable receive and transmit.
146 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
148 /* Mask all interrupts and remove anything pending. */
152 /* put the SMC channel into NMSI (non multiplexd serial interface)
153 * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
155 im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE;
157 /* Set up the baud rate generator. */
160 /* Make the first buffer the only buffer. */
161 rtx->txbd.cbd_sc |= BD_SC_WRAP;
162 rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
164 /* single/multi character receive. */
165 up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
166 up->smc_maxidl = CONFIG_SYS_MAXIDLE;
169 /* Initialize Tx/Rx parameters. */
171 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
174 cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC_PAGE, CPM_CR_SMC_SBLOCK,
175 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
177 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
180 /* Enable transmitter/receiver. */
181 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
189 #if defined(CONFIG_CONS_USE_EXTC)
190 m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate,
191 CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
193 m8260_cpm_setbrg(brg_map[SMC_INDEX], gd->baudrate);
198 serial_putc(const char c)
200 volatile smc_uart_t *up;
201 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
202 volatile serialbuffer_t *rtx;
207 up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
209 rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
211 /* Wait for last character to go. */
212 while (rtx->txbd.cbd_sc & BD_SC_READY & BD_SC_READY)
215 rtx->txbd.cbd_datlen = 1;
216 rtx->txbd.cbd_sc |= BD_SC_READY;
220 serial_puts (const char *s)
230 volatile smc_uart_t *up;
231 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
232 volatile serialbuffer_t *rtx;
235 up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
237 rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
239 /* Wait for character to show up. */
240 while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
243 /* the characters are read one by one,
244 * use the rxindex to know the next char to deliver
246 c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr + rtx->rxindex);
249 /* check if all char are readout, then make prepare for next receive */
250 if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
252 rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
260 volatile smc_uart_t *up;
261 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
262 volatile serialbuffer_t *rtx;
264 up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
265 rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
267 return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
270 #endif /* CONFIG_CONS_ON_SMC */
272 #if defined(CONFIG_KGDB_ON_SMC)
274 #if defined(CONFIG_CONS_ON_SMC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
275 #error Whoops! serial console and kgdb are on the same smc serial port
278 #if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SMC1 */
280 #define KGDB_SMC_INDEX 0
281 #define KGDB_PROFF_SMC_BASE PROFF_SMC1_BASE
282 #define KGDB_PROFF_SMC PROFF_SMC1
283 #define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE
284 #define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK
285 #define KGDB_CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
286 #define KGDB_CMXSMR_VALUE CMXSMR_SMC1CS_BRG7
288 #elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SMC2 */
290 #define KGDB_SMC_INDEX 1
291 #define KGDB_PROFF_SMC_BASE PROFF_SMC2_BASE
292 #define KGDB_PROFF_SMC PROFF_SMC2
293 #define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE
294 #define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK
295 #define KGDB_CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
296 #define KGDB_CMXSMR_VALUE CMXSMR_SMC2CS_BRG8
300 #error "console not correctly defined"
305 kgdb_serial_init (void)
307 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
309 volatile smc_uart_t *up;
310 volatile cbd_t *tbdf, *rbdf;
311 volatile cpm8260_t *cp = &(im->im_cpm);
312 uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
315 if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
316 ulong rate = simple_strtoul(s, &e, 10);
317 if (e > s && *e == '\0')
321 /* initialize pointers to SMC */
323 sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]);
324 *(ushort *)(&im->im_dprambase[KGDB_PROFF_SMC_BASE]) = KGDB_PROFF_SMC;
325 up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC];
327 /* Disable transmitter/receiver. */
328 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
330 /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
332 /* Allocate space for two buffer descriptors in the DP ram.
333 * damm: allocating space after the two buffers for rx/tx data
336 dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
338 /* Set the physical address of the host memory buffers in
339 * the buffer descriptors.
341 rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
342 rbdf->cbd_bufaddr = (uint) (rbdf+2);
345 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
348 /* Set up the uart parameters in the parameter ram. */
349 up->smc_rbase = dpaddr;
350 up->smc_tbase = dpaddr+sizeof(cbd_t);
351 up->smc_rfcr = CPMFCR_EB;
352 up->smc_tfcr = CPMFCR_EB;
357 /* Set UART mode, 8 bit, no parity, one stop.
358 * Enable receive and transmit.
360 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
362 /* Mask all interrupts and remove anything pending. */
366 /* put the SMC channel into NMSI (non multiplexd serial interface)
367 * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
369 im->im_cpmux.cmx_smr =
370 (im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE;
372 /* Set up the baud rate generator. */
373 #if defined(CONFIG_KGDB_USE_EXTC)
374 m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed,
375 CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
377 m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed);
380 /* Make the first buffer the only buffer. */
381 tbdf->cbd_sc |= BD_SC_WRAP;
382 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
384 /* Single character receive. */
388 /* Initialize Tx/Rx parameters. */
390 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
393 cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SMC_PAGE, KGDB_CPM_CR_SMC_SBLOCK,
394 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
396 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
399 /* Enable transmitter/receiver. */
400 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
402 printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
406 putDebugChar(const char c)
408 volatile cbd_t *tbdf;
410 volatile smc_uart_t *up;
411 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
416 up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
418 tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase];
420 /* Wait for last character to go. */
421 buf = (char *)tbdf->cbd_bufaddr;
422 while (tbdf->cbd_sc & BD_SC_READY)
426 tbdf->cbd_datlen = 1;
427 tbdf->cbd_sc |= BD_SC_READY;
431 putDebugStr (const char *s)
441 volatile cbd_t *rbdf;
442 volatile unsigned char *buf;
443 volatile smc_uart_t *up;
444 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
447 up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
449 rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
451 /* Wait for character to show up. */
452 buf = (unsigned char *)rbdf->cbd_bufaddr;
453 while (rbdf->cbd_sc & BD_SC_EMPTY)
456 rbdf->cbd_sc |= BD_SC_EMPTY;
462 kgdb_interruptible(int yes)
467 #endif /* CONFIG_KGDB_ON_SMC */