3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
27 * Minimal serial functions needed to use one of the SCC ports
28 * as serial console interface.
33 #include <asm/cpm_8260.h>
35 #include <linux/compiler.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 #if defined(CONFIG_CONS_ON_SCC)
41 #if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */
44 #define PROFF_SCC PROFF_SCC1
45 #define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\
46 CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
47 #define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
48 #define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE
49 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK
51 #elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */
54 #define PROFF_SCC PROFF_SCC2
55 #define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\
56 CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
57 #define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
58 #define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE
59 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK
61 #elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */
64 #define PROFF_SCC PROFF_SCC3
65 #define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\
66 CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
67 #define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
68 #define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE
69 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK
71 #elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */
74 #define PROFF_SCC PROFF_SCC4
75 #define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\
76 CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
77 #define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
78 #define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE
79 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK
83 #error "console not correctly defined"
87 static int mpc8260_scc_serial_init(void)
89 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
91 volatile scc_uart_t *up;
92 volatile cbd_t *tbdf, *rbdf;
93 volatile cpm8260_t *cp = &(im->im_cpm);
96 /* initialize pointers to SCC */
98 sp = (scc_t *) &(im->im_scc[SCC_INDEX]);
99 up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
101 /* Disable transmitter/receiver.
103 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
105 /* put the SCC channel into NMSI (non multiplexd serial interface)
106 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
108 im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr&~CMXSCR_MASK)|CMXSCR_VALUE;
110 /* Set up the baud rate generator.
114 /* Allocate space for two buffer descriptors in the DP ram.
115 * damm: allocating space after the two buffers for rx/tx data
118 dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
120 /* Set the physical address of the host memory buffers in
121 * the buffer descriptors.
123 rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
124 rbdf->cbd_bufaddr = (uint) (rbdf+2);
125 rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
127 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
128 tbdf->cbd_sc = BD_SC_WRAP;
130 /* Set up the uart parameters in the parameter ram.
132 up->scc_genscc.scc_rbase = dpaddr;
133 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
134 up->scc_genscc.scc_rfcr = CPMFCR_EB;
135 up->scc_genscc.scc_tfcr = CPMFCR_EB;
136 up->scc_genscc.scc_mrblr = 1;
146 up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
147 up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
148 up->scc_rccm = 0xc0ff;
150 /* Mask all interrupts and remove anything pending.
153 sp->scc_scce = 0xffff;
155 /* Set 8 bit FIFO, 16 bit oversampling and UART mode.
157 sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */
159 SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
161 /* Set CTS flow control, 1 stop bit, 8 bit character length,
162 * normal async UART mode, no parity
164 sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL;
166 /* execute the "Init Rx and Tx params" CP command.
169 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
172 cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
173 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
175 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
178 /* Enable transmitter/receiver.
180 sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
185 static void mpc8260_scc_serial_setbrg(void)
187 #if defined(CONFIG_CONS_USE_EXTC)
188 m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate,
189 CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
191 m8260_cpm_setbrg(SCC_INDEX, gd->baudrate);
195 static void mpc8260_scc_serial_putc(const char c)
197 volatile scc_uart_t *up;
198 volatile cbd_t *tbdf;
199 volatile immap_t *im;
204 im = (immap_t *)CONFIG_SYS_IMMR;
205 up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
206 tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
208 /* Wait for last character to go.
210 while (tbdf->cbd_sc & BD_SC_READY)
213 /* Load the character into the transmit buffer.
215 *(volatile char *)tbdf->cbd_bufaddr = c;
216 tbdf->cbd_datlen = 1;
217 tbdf->cbd_sc |= BD_SC_READY;
220 static int mpc8260_scc_serial_getc(void)
222 volatile cbd_t *rbdf;
223 volatile scc_uart_t *up;
224 volatile immap_t *im;
227 im = (immap_t *)CONFIG_SYS_IMMR;
228 up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
229 rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
231 /* Wait for character to show up.
233 while (rbdf->cbd_sc & BD_SC_EMPTY)
236 /* Grab the char and clear the buffer again.
238 c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
239 rbdf->cbd_sc |= BD_SC_EMPTY;
244 static int mpc8260_scc_serial_tstc(void)
246 volatile cbd_t *rbdf;
247 volatile scc_uart_t *up;
248 volatile immap_t *im;
250 im = (immap_t *)CONFIG_SYS_IMMR;
251 up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
252 rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
254 return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
257 static struct serial_device mpc8260_scc_serial_drv = {
258 .name = "mpc8260_scc_uart",
259 .start = mpc8260_scc_serial_init,
261 .setbrg = mpc8260_scc_serial_setbrg,
262 .putc = mpc8260_scc_serial_putc,
263 .puts = default_serial_puts,
264 .getc = mpc8260_scc_serial_getc,
265 .tstc = mpc8260_scc_serial_tstc,
268 void mpc8260_scc_serial_initialize(void)
270 serial_register(&mpc8260_scc_serial_drv);
273 __weak struct serial_device *default_serial_console(void)
275 return &mpc8260_scc_serial_drv;
277 #endif /* CONFIG_CONS_ON_SCC */
279 #if defined(CONFIG_KGDB_ON_SCC)
281 #if defined(CONFIG_CONS_ON_SCC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
282 #error Whoops! serial console and kgdb are on the same scc serial port
285 #if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SCC1 */
287 #define KGDB_SCC_INDEX 0
288 #define KGDB_PROFF_SCC PROFF_SCC1
289 #define KGDB_CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\
290 CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
291 #define KGDB_CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
292 #define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE
293 #define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK
295 #elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SCC2 */
297 #define KGDB_SCC_INDEX 1
298 #define KGDB_PROFF_SCC PROFF_SCC2
299 #define KGDB_CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\
300 CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
301 #define KGDB_CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
302 #define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE
303 #define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK
305 #elif CONFIG_KGDB_INDEX == 3 /* KGDB Port on SCC3 */
307 #define KGDB_SCC_INDEX 2
308 #define KGDB_PROFF_SCC PROFF_SCC3
309 #define KGDB_CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\
310 CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
311 #define KGDB_CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
312 #define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE
313 #define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK
315 #elif CONFIG_KGDB_INDEX == 4 /* KGDB Port on SCC4 */
317 #define KGDB_SCC_INDEX 3
318 #define KGDB_PROFF_SCC PROFF_SCC4
319 #define KGDB_CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\
320 CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
321 #define KGDB_CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
322 #define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE
323 #define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK
327 #error "kgdb serial port not correctly defined"
332 kgdb_serial_init (void)
334 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
336 volatile scc_uart_t *up;
337 volatile cbd_t *tbdf, *rbdf;
338 volatile cpm8260_t *cp = &(im->im_cpm);
339 uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
342 if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
343 ulong rate = simple_strtoul(s, &e, 10);
344 if (e > s && *e == '\0')
348 /* initialize pointers to SCC */
350 sp = (scc_t *) &(im->im_scc[KGDB_SCC_INDEX]);
351 up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
353 /* Disable transmitter/receiver.
355 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
357 /* put the SCC channel into NMSI (non multiplexd serial interface)
358 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
360 im->im_cpmux.cmx_scr = \
361 (im->im_cpmux.cmx_scr & ~KGDB_CMXSCR_MASK) | KGDB_CMXSCR_VALUE;
363 /* Set up the baud rate generator.
365 #if defined(CONFIG_KGDB_USE_EXTC)
366 m8260_cpm_extcbrg(KGDB_SCC_INDEX, speed,
367 CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
369 m8260_cpm_setbrg(KGDB_SCC_INDEX, speed);
372 /* Allocate space for two buffer descriptors in the DP ram.
373 * damm: allocating space after the two buffers for rx/tx data
376 dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
378 /* Set the physical address of the host memory buffers in
379 * the buffer descriptors.
381 rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
382 rbdf->cbd_bufaddr = (uint) (rbdf+2);
383 rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
385 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
386 tbdf->cbd_sc = BD_SC_WRAP;
388 /* Set up the uart parameters in the parameter ram.
390 up->scc_genscc.scc_rbase = dpaddr;
391 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
392 up->scc_genscc.scc_rfcr = CPMFCR_EB;
393 up->scc_genscc.scc_tfcr = CPMFCR_EB;
394 up->scc_genscc.scc_mrblr = 1;
404 up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
405 up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
406 up->scc_rccm = 0xc0ff;
408 /* Mask all interrupts and remove anything pending.
411 sp->scc_scce = 0xffff;
413 /* Set 8 bit FIFO, 16 bit oversampling and UART mode.
415 sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */
417 SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
419 /* Set CTS flow control, 1 stop bit, 8 bit character length,
420 * normal async UART mode, no parity
422 sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL;
424 /* execute the "Init Rx and Tx params" CP command.
427 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
430 cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SCC_PAGE, KGDB_CPM_CR_SCC_SBLOCK,
431 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
433 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
436 /* Enable transmitter/receiver.
438 sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
440 printf("SCC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
444 putDebugChar(const char c)
446 volatile scc_uart_t *up;
447 volatile cbd_t *tbdf;
448 volatile immap_t *im;
453 im = (immap_t *)CONFIG_SYS_IMMR;
454 up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
455 tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
457 /* Wait for last character to go.
459 while (tbdf->cbd_sc & BD_SC_READY)
462 /* Load the character into the transmit buffer.
464 *(volatile char *)tbdf->cbd_bufaddr = c;
465 tbdf->cbd_datlen = 1;
466 tbdf->cbd_sc |= BD_SC_READY;
470 putDebugStr (const char *s)
480 volatile cbd_t *rbdf;
481 volatile scc_uart_t *up;
482 volatile immap_t *im;
485 im = (immap_t *)CONFIG_SYS_IMMR;
486 up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
487 rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
489 /* Wait for character to show up.
491 while (rbdf->cbd_sc & BD_SC_EMPTY)
494 /* Grab the char and clear the buffer again.
496 c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
497 rbdf->cbd_sc |= BD_SC_EMPTY;
503 kgdb_interruptible(int yes)
508 #endif /* CONFIG_KGDB_ON_SCC */