3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (c) 2005 MontaVista Software, Inc.
6 * Vitaly Bordug <vbordug@ru.mvista.com>
7 * Added support for PCI bridge on MPC8272ADS
9 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/m8260_pci.h>
20 #ifdef CONFIG_OF_LIBFDT
22 #include <fdt_support.h>
25 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
26 DECLARE_GLOBAL_DATA_PTR;
30 * Local->PCI map (from CPU) controlled by
31 * MPC826x master window
33 * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
34 * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
36 * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
37 * PCI Mem with prefetch
39 * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
40 * PCI Mem w/o prefetch
42 * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
45 * PCI->Local map (from PCI)
46 * MPC826x slave window controlled by
48 * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
49 * MPC826x local memory
53 * Slave window that allows PCI masters to access MPC826x local memory.
54 * This window is set up using the first set of Inbound ATU registers
57 #ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL
58 #define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
60 #define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL
63 #ifndef CONFIG_SYS_PCI_SLV_MEM_BUS
64 #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
66 #define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS
69 #ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB
70 #define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
73 #define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB
77 * These are the windows that allow the CPU to access PCI address space.
78 * All three PCI master windows, which allow the CPU to access PCI
79 * prefetch, non prefetch, and IO space (see below), must all fit within
84 #ifndef CONFIG_SYS_PCI_MSTR0_LOCAL
85 #define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
87 #define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL
90 #ifndef CONFIG_SYS_PCIMSK0_MASK
91 #define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
93 #define PCIMSK0_MASK CONFIG_SYS_PCIMSK0_MASK
97 #ifndef CONFIG_SYS_PCI_MSTR1_LOCAL
98 #define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
100 #define PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR1_LOCAL
103 #ifndef CONFIG_SYS_PCIMSK1_MASK
104 #define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
106 #define PCIMSK1_MASK CONFIG_SYS_PCIMSK1_MASK
110 * Master window that allows the CPU to access PCI Memory (prefetch).
111 * This window will be setup with the first set of Outbound ATU registers
115 #ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL
116 #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
118 #define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
121 #ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS
122 #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
124 #define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS
127 #ifndef CONFIG_SYS_CPU_PCI_MEM_START
128 #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
130 #define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START
133 #ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE
134 #define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
136 #define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE
139 #ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB
140 #define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
142 #define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB
146 * Master window that allows the CPU to access PCI Memory (non-prefetch).
147 * This window will be setup with the second set of Outbound ATU registers
151 #ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
152 #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
154 #define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
157 #ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS
158 #define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
160 #define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS
163 #ifndef CONFIG_SYS_CPU_PCI_MEMIO_START
164 #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
166 #define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START
169 #ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
170 #define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
172 #define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
175 #ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB
176 #define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
178 #define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB
182 * Master window that allows the CPU to access PCI IO space.
183 * This window will be setup with the third set of Outbound ATU registers
187 #ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL
188 #define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
190 #define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL
193 #ifndef CONFIG_SYS_PCI_MSTR_IO_BUS
194 #define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
196 #define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS
199 #ifndef CONFIG_SYS_CPU_PCI_IO_START
200 #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
202 #define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START
205 #ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE
206 #define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
208 #define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE
211 #ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB
212 #define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
214 #define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB
217 /* PCI bus configuration registers.
220 #define PCI_CLASS_BRIDGE_CTLR 0x06
223 static inline void pci_outl (u32 addr, u32 data)
225 *(volatile u32 *) addr = cpu_to_le32 (data);
228 void pci_mpc8250_init (struct pci_controller *hose)
232 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
233 pci_dev_t host_devno = PCI_BDF (0, 0, 0);
235 pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG,
236 CONFIG_SYS_IMMR + PCI_CFG_DATA_REG);
239 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
241 #ifdef CONFIG_MPC8266ADS
242 immap->im_siu_conf.sc_siumcr =
243 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
245 #elif defined(CONFIG_ADSTYPE) && CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
246 /* nothing to do for this board here */
247 #elif defined CONFIG_MPC8272
248 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
267 #elif defined(CONFIG_TQM8272)
268 /* nothing to do for this Board here */
271 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
272 * and local bus for PCI (SIUMCR [LBPC]).
274 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
283 /* Make PCI lowest priority */
284 /* Each 4 bits is a device bus request and the MS 4bits
285 is highest priority */
295 External Master 1 0b0111
296 External Master 2 0b1000
297 External Master 3 0b1001
298 The rest are reserved */
299 immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
301 /* Park bus on core while modifying PCI Bus accesses */
302 immap->im_siu_conf.sc_ppc_acr = 0x6;
305 * Set up master windows that allow the CPU to access PCI space. These
306 * windows are set up using the two SIU PCIBR registers.
308 immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
309 immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
311 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
312 immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
313 immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
316 /* Release PCI RST (by default the PCI RST signal is held low) */
317 immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
319 /* give it some time */
321 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
322 /* Give the PCI cards more time to initialize before query
323 This might be good for other boards also
327 for (i = 0; i < 1000; ++i)
333 * Set up master window that allows the CPU to access PCI Memory (prefetch)
334 * space. This window is set up using the first set of Outbound ATU registers.
336 immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */
337 immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
338 immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */
341 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
342 * space. This window is set up using the second set of Outbound ATU registers.
344 immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
345 immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
346 immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */
349 * Set up master window that allows the CPU to access PCI IO space. This window
350 * is set up using the third set of Outbound ATU registers.
352 immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
353 immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */
354 immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */
357 * Set up slave window that allows PCI masters to access MPC826x local memory.
358 * This window is set up using the first set of Inbound ATU registers
360 immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */
361 immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
362 immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
364 /* See above for description - puts PCI request as highest priority */
365 #ifdef CONFIG_MPC8272
366 immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
368 immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
371 /* Park the bus on the PCI */
372 immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
374 /* Host mode - specify the bridge as a host-PCI bridge */
376 pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
377 PCI_CLASS_BRIDGE_CTLR);
379 /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
380 pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
381 pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
382 tempShort | PCI_COMMAND_MASTER |
385 /* do some bridge init, should be done on all 8260 based bridges */
386 pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
388 pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
391 hose->first_busno = 0;
392 hose->last_busno = 0xff;
394 /* System memory space */
395 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
396 pci_set_region (hose->regions + 0,
399 gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
401 pci_set_region (hose->regions + 0,
402 CONFIG_SYS_SDRAM_BASE,
403 CONFIG_SYS_SDRAM_BASE,
404 0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
407 /* PCI memory space */
408 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
409 pci_set_region (hose->regions + 1,
411 PCI_MSTR_MEMIO_LOCAL,
412 PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
414 pci_set_region (hose->regions + 1,
417 PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
421 pci_set_region (hose->regions + 2,
423 PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
425 hose->region_count = 3;
427 pci_register_hose (hose);
428 /* Mask off master abort machine checks */
429 immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
432 hose->last_busno = pci_hose_scan (hose);
435 /* clear the error in the error status register */
436 immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
438 /* unmask master abort machine checks */
439 immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
442 #if defined(CONFIG_OF_LIBFDT)
443 void ft_pci_setup(void *blob, bd_t *bd)
445 do_fixup_by_prop_u32(blob, "device_type", "pci", 4,
446 "clock-frequency", gd->pci_clk, 1);
450 #endif /* CONFIG_PCI */