3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if defined(CONFIG_HARD_I2C)
31 #include <asm/cpm_8260.h>
34 /* define to enable debug messages */
37 DECLARE_GLOBAL_DATA_PTR;
39 #if defined(CONFIG_I2C_MULTI_BUS)
40 static unsigned int i2c_bus_num __attribute__ ((section(".data"))) = 0;
41 #endif /* CONFIG_I2C_MULTI_BUS */
43 /* uSec to wait between polls of the i2c */
45 /* uSec to wait for the CPM to start processing the buffer */
46 #define START_DELAY_US 1000
49 * tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the
50 * timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP
57 #ifndef CONFIG_SYS_I2C_SPEED
58 #define CONFIG_SYS_I2C_SPEED 50000
62 typedef void (*i2c_ecb_t) (int, int, void *); /* error callback function */
64 /* This structure keeps track of the bd and buffer space usage. */
65 typedef struct i2c_state {
66 int rx_idx; /* index to next free Rx BD */
67 int tx_idx; /* index to next free Tx BD */
68 void *rxbd; /* pointer to next free Rx BD */
69 void *txbd; /* pointer to next free Tx BD */
70 int tx_space; /* number of Tx bytes left */
71 unsigned char *tx_buf; /* pointer to free Tx area */
72 i2c_ecb_t err_cb; /* error callback function */
73 void *cb_data; /* private data to be passed */
76 /* flags for i2c_send() and i2c_receive() */
77 #define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
78 #define I2CF_START_COND 0x02 /* tx: generate start condition */
79 #define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
82 #define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */
83 #define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */
84 #define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */
85 #define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/rcv */
86 #define I2CERR_IO_ERROR 5 /* had an error during comms */
88 /* error callback flags */
89 #define I2CECB_RX_ERR 0x10 /* this is a receive error */
90 #define I2CECB_RX_OV 0x02 /* receive overrun error */
91 #define I2CECB_RX_MASK 0x0f /* mask for error bits */
92 #define I2CECB_TX_ERR 0x20 /* this is a transmit error */
93 #define I2CECB_TX_CL 0x01 /* transmit collision error */
94 #define I2CECB_TX_UN 0x02 /* transmit underflow error */
95 #define I2CECB_TX_NAK 0x04 /* transmit no ack error */
96 #define I2CECB_TX_MASK 0x0f /* mask for error bits */
97 #define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
99 #define ERROR_I2C_NONE 0
100 #define ERROR_I2C_LENGTH 1
102 #define I2C_WRITE_BIT 0x00
103 #define I2C_READ_BIT 0x01
105 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
110 #define MAX_TX_SPACE 256
112 typedef struct I2C_BD {
113 unsigned short status;
114 unsigned short length;
118 #define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
120 #define BD_I2C_TX_CL 0x0001 /* collision error */
121 #define BD_I2C_TX_UN 0x0002 /* underflow error */
122 #define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
123 #define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
125 #define BD_I2C_RX_ERR BD_SC_OV
128 #define PRINTD(x) printf x
134 * Returns the best value of I2BRG to meet desired clock speed of I2C with
135 * input parameters (clock speed, filter, and predivider value).
136 * It returns computer speed value and the difference between it and desired
140 i2c_roundrate(int hz, int speed, int filter, int modval,
141 int *brgval, int *totspeed)
143 int moddiv = 1 << (5 - (modval & 3)), brgdiv, div;
145 PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
146 hz, speed, filter, modval));
148 div = moddiv * speed;
149 brgdiv = (hz + div - 1) / div;
151 PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
153 *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter);
155 if ((*brgval < 0) || (*brgval > 255)) {
156 PRINTD(("\t\trejected brgval=%d\n", *brgval));
160 brgdiv = 2 * (*brgval + 3 + (2 * filter));
161 div = moddiv * brgdiv;
162 *totspeed = hz / div;
164 PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
170 * Sets the I2C clock predivider and divider to meet required clock speed.
172 static int i2c_setrate(int hz, int speed)
174 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
175 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
178 bestspeed_diff = speed,
179 bestspeed_brgval = 0,
180 bestspeed_modval = 0,
181 bestspeed_filter = 0,
183 filter = 0; /* Use this fixed value */
185 for (modval = 0; modval < 4; modval++) {
186 if (i2c_roundrate(hz, speed, filter, modval, &brgval, &totspeed)
188 int diff = speed - totspeed;
190 if ((diff >= 0) && (diff < bestspeed_diff)) {
191 bestspeed_diff = diff;
192 bestspeed_modval = modval;
193 bestspeed_brgval = brgval;
194 bestspeed_filter = filter;
199 PRINTD(("[I2C] Best is:\n"));
200 PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
201 hz, speed, bestspeed_filter, bestspeed_modval, bestspeed_brgval,
204 i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) |
205 (bestspeed_filter << 3);
206 i2c->i2c_i2brg = bestspeed_brgval & 0xff;
208 PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod,
214 void i2c_init(int speed, int slaveadd)
216 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
217 volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
218 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
221 volatile I2C_BD *rxbd, *txbd;
224 #ifdef CONFIG_SYS_I2C_INIT_BOARD
226 * call board specific i2c bus reset routine before accessing the
227 * environment, which might be in a chip on that bus. For details
228 * about this problem see doc/I2C_Edge_Conditions.
233 dpaddr = *((unsigned short *) (&immap->im_dprambase[PROFF_I2C_BASE]));
235 /* need to allocate dual port ram */
236 dpaddr = m8260_cpm_dpalloc(64 +
237 (NUM_RX_BDS * sizeof(I2C_BD)) +
238 (NUM_TX_BDS * sizeof(I2C_BD)) +
240 *((unsigned short *)(&immap->im_dprambase[PROFF_I2C_BASE])) =
245 * initialise data in dual port ram:
247 * dpaddr -> parameter ram (64 bytes)
248 * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
249 * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
250 * tx buffer (MAX_TX_SPACE bytes)
253 iip = (iic_t *)&immap->im_dprambase[dpaddr];
254 memset((void *)iip, 0, sizeof(iic_t));
257 tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
259 /* Disable interrupts */
260 i2c->i2c_i2mod = 0x00;
261 i2c->i2c_i2cmr = 0x00;
262 i2c->i2c_i2cer = 0xff;
263 i2c->i2c_i2add = slaveadd;
266 * Set the I2C BRG Clock division factor from desired i2c rate
267 * and current CPU rate (we assume sccr dfbgr field is 0;
268 * divide BRGCLK by 1)
270 PRINTD(("[I2C] Setting rate...\n"));
271 i2c_setrate(gd->brg_clk, CONFIG_SYS_I2C_SPEED);
273 /* Set I2C controller in master mode */
274 i2c->i2c_i2com = 0x01;
276 /* Initialize Tx/Rx parameters */
277 iip->iic_rbase = rbase;
278 iip->iic_tbase = tbase;
279 rxbd = (I2C_BD *)((unsigned char *) &immap->
280 im_dprambase[iip->iic_rbase]);
281 txbd = (I2C_BD *)((unsigned char *) &immap->
282 im_dprambase[iip->iic_tbase]);
284 PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
285 PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
286 PRINTD(("[I2C] rxbd = %08x\n", (int) rxbd));
287 PRINTD(("[I2C] txbd = %08x\n", (int) txbd));
289 /* Set big endian byte order */
290 iip->iic_tfcr = 0x10;
291 iip->iic_rfcr = 0x10;
293 /* Set maximum receive size. */
294 iip->iic_mrblr = I2C_RXTX_LEN;
296 cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
298 0x00, CPM_CR_INIT_TRX) | CPM_CR_FLG;
300 __asm__ __volatile__("eieio");
301 } while (cp->cp_cpcr & CPM_CR_FLG);
303 /* Clear events and interrupts */
304 i2c->i2c_i2cer = 0xff;
305 i2c->i2c_i2cmr = 0x00;
309 void i2c_newio(i2c_state_t *state)
311 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
315 PRINTD(("[I2C] i2c_newio\n"));
317 dpaddr = *((unsigned short *)(&immap->im_dprambase[PROFF_I2C_BASE]));
318 iip = (iic_t *)&immap->im_dprambase[dpaddr];
321 state->rxbd = (void *)&immap->im_dprambase[iip->iic_rbase];
322 state->txbd = (void *)&immap->im_dprambase[iip->iic_tbase];
323 state->tx_space = MAX_TX_SPACE;
324 state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
325 state->err_cb = NULL;
326 state->cb_data = NULL;
328 PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
329 PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
330 PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
332 /* clear the buffer memory */
333 memset((char *) state->tx_buf, 0, MAX_TX_SPACE);
337 int i2c_send(i2c_state_t *state,
338 unsigned char address,
339 unsigned char secondary_address,
340 unsigned int flags, unsigned short size, unsigned char *dataout)
342 volatile I2C_BD *txbd;
345 PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
346 address, secondary_address, flags, size));
348 /* trying to send message larger than BD */
349 if (size > I2C_RXTX_LEN)
350 return I2CERR_MSG_TOO_LONG;
352 /* no more free bds */
353 if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
354 return I2CERR_NO_BUFFERS;
356 txbd = (I2C_BD *)state->txbd;
357 txbd->addr = state->tx_buf;
359 PRINTD(("[I2C] txbd = %08x\n", (int) txbd));
361 if (flags & I2CF_START_COND) {
362 PRINTD(("[I2C] Formatting addresses...\n"));
363 if (flags & I2CF_ENABLE_SECONDARY) {
364 /* Length of message plus dest addresses */
365 txbd->length = size + 2;
366 txbd->addr[0] = address << 1;
367 txbd->addr[1] = secondary_address;
370 /* Length of message plus dest address */
371 txbd->length = size + 1;
372 /* Write destination address to BD */
373 txbd->addr[0] = address << 1;
377 txbd->length = size; /* Length of message */
382 txbd->status = BD_SC_READY;
383 if (flags & I2CF_START_COND)
384 txbd->status |= BD_I2C_TX_START;
385 if (flags & I2CF_STOP_COND)
386 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
388 /* Copy data to send into buffer */
389 PRINTD(("[I2C] copy data...\n"));
390 for (j = 0; j < size; i++, j++)
391 txbd->addr[i] = dataout[j];
393 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
394 txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]));
397 state->tx_buf += txbd->length;
398 state->tx_space -= txbd->length;
400 state->txbd = (void *) (txbd + 1);
406 int i2c_receive(i2c_state_t *state,
407 unsigned char address,
408 unsigned char secondary_address,
410 unsigned short size_to_expect, unsigned char *datain)
412 volatile I2C_BD *rxbd, *txbd;
414 PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address,
415 secondary_address, flags));
417 /* Expected to receive too much */
418 if (size_to_expect > I2C_RXTX_LEN)
419 return I2CERR_MSG_TOO_LONG;
421 /* no more free bds */
422 if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
423 || state->tx_space < 2)
424 return I2CERR_NO_BUFFERS;
426 rxbd = (I2C_BD *) state->rxbd;
427 txbd = (I2C_BD *) state->txbd;
429 PRINTD(("[I2C] rxbd = %08x\n", (int) rxbd));
430 PRINTD(("[I2C] txbd = %08x\n", (int) txbd));
432 txbd->addr = state->tx_buf;
434 /* set up TXBD for destination address */
435 if (flags & I2CF_ENABLE_SECONDARY) {
437 txbd->addr[0] = address << 1; /* Write data */
438 txbd->addr[1] = secondary_address; /* Internal address */
439 txbd->status = BD_SC_READY;
441 txbd->length = 1 + size_to_expect;
442 txbd->addr[0] = (address << 1) | 0x01;
443 txbd->status = BD_SC_READY;
444 memset(&txbd->addr[1], 0, txbd->length);
447 /* set up rxbd for reception */
448 rxbd->status = BD_SC_EMPTY;
449 rxbd->length = size_to_expect;
452 txbd->status |= BD_I2C_TX_START;
453 if (flags & I2CF_STOP_COND) {
454 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
455 rxbd->status |= BD_SC_WRAP;
458 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
459 txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]));
460 PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
461 rxbd->length, rxbd->status, rxbd->addr[0], rxbd->addr[1]));
464 state->tx_buf += txbd->length;
465 state->tx_space -= txbd->length;
467 state->txbd = (void *) (txbd + 1);
469 state->rxbd = (void *) (rxbd + 1);
476 int i2c_doio(i2c_state_t *state)
478 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
480 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
481 volatile I2C_BD *txbd, *rxbd;
482 int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
485 PRINTD(("[I2C] i2c_doio\n"));
487 if (state->tx_idx <= 0 && state->rx_idx <= 0) {
488 PRINTD(("[I2C] No I/O is queued\n"));
489 return I2CERR_QUEUE_EMPTY;
492 dpaddr = *((unsigned short *)(&immap->im_dprambase[PROFF_I2C_BASE]));
493 iip = (iic_t *)&immap->im_dprambase[dpaddr];
494 iip->iic_rbptr = iip->iic_rbase;
495 iip->iic_tbptr = iip->iic_tbase;
498 PRINTD(("[I2C] Enabling I2C...\n"));
499 i2c->i2c_i2mod |= 0x01;
501 /* Begin transmission */
502 i2c->i2c_i2com |= 0x80;
504 /* Loop until transmit & receive completed */
510 txbd = ((I2C_BD *) state->txbd) - n;
511 for (i = 0; i < n; i++) {
512 txtimeo += TOUT_LOOP * txbd->length;
516 txbd--; /* wait until last in list is done */
518 PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n",
521 udelay(START_DELAY_US); /* give it time to start */
522 while ((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) {
526 __asm__ __volatile__("eieio");
532 if (txcnt < txtimeo && n > 0) {
534 rxbd = ((I2C_BD *) state->rxbd) - n;
535 for (i = 0; i < n; i++) {
536 rxtimeo += TOUT_LOOP * rxbd->length;
540 rxbd--; /* wait until last in list is done */
542 PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong) rxbd));
544 udelay(START_DELAY_US); /* give it time to start */
545 while ((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) {
549 __asm__ __volatile__("eieio");
554 i2c->i2c_i2mod &= ~0x01;
559 for (i = 0; i < n; i++) {
560 txbd = ((I2C_BD *) state->txbd) - (n - i);
561 b = txbd->status & BD_I2C_TX_ERR;
563 if (state->err_cb != NULL)
564 (*state->err_cb) (I2CECB_TX_ERR | b,
567 rc = I2CERR_IO_ERROR;
575 for (i = 0; i < n; i++) {
576 rxbd = ((I2C_BD *) state->rxbd) - (n - i);
577 b = rxbd->status & BD_I2C_RX_ERR;
579 if (state->err_cb != NULL)
580 (*state->err_cb) (I2CECB_RX_ERR | b,
583 rc = I2CERR_IO_ERROR;
588 if ((txtimeo > 0 && txcnt >= txtimeo) ||
589 (rxtimeo > 0 && rxcnt >= rxtimeo)) {
590 if (state->err_cb != NULL)
591 (*state->err_cb) (I2CECB_TIMEOUT, -1, state->cb_data);
599 static void i2c_probe_callback(int flags, int xnum, void *data)
602 * the only acceptable errors are a transmit NAK or a receive
603 * overrun - tx NAK means the device does not exist, rx OV
604 * means the device must have responded to the slave address
605 * even though the transfer failed
607 if (flags == (I2CECB_TX_ERR | I2CECB_TX_NAK))
609 if (flags == (I2CECB_RX_ERR | I2CECB_RX_OV))
613 int i2c_probe(uchar chip)
621 state.err_cb = i2c_probe_callback;
622 state.cb_data = (void *) &err_flag;
625 rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1,
629 return rc; /* probe failed */
631 rc = i2c_doio(&state);
634 return 0; /* device exists - read succeeded */
636 if (rc == I2CERR_TIMEOUT)
637 return -1; /* device does not exist - timeout */
639 if (rc != I2CERR_IO_ERROR || err_flag == 0)
640 return rc; /* probe failed */
643 return -1; /* device does not exist - had transmit NAK */
645 return 0; /* device exists - had receive overrun */
649 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
655 xaddr[0] = (addr >> 24) & 0xFF;
656 xaddr[1] = (addr >> 16) & 0xFF;
657 xaddr[2] = (addr >> 8) & 0xFF;
658 xaddr[3] = addr & 0xFF;
660 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
662 * EEPROM chips that implement "address overflow" are ones
663 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
664 * and the extra bits end up in the "chip address" bit slots.
665 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
668 * Note that we consider the length of the address field to still
669 * be one byte because the extra address bits are hidden in the
672 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
677 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
680 printf("i2c_read: i2c_send failed (%d)\n", rc);
684 rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
686 printf("i2c_read: i2c_receive failed (%d)\n", rc);
690 rc = i2c_doio(&state);
692 printf("i2c_read: i2c_doio failed (%d)\n", rc);
698 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
704 xaddr[0] = (addr >> 24) & 0xFF;
705 xaddr[1] = (addr >> 16) & 0xFF;
706 xaddr[2] = (addr >> 8) & 0xFF;
707 xaddr[3] = addr & 0xFF;
709 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
711 * EEPROM chips that implement "address overflow" are ones
712 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
713 * and the extra bits end up in the "chip address" bit slots.
714 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
717 * Note that we consider the length of the address field to still
718 * be one byte because the extra address bits are hidden in the
721 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
726 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
729 printf("i2c_write: first i2c_send failed (%d)\n", rc);
733 rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
735 printf("i2c_write: second i2c_send failed (%d)\n", rc);
739 rc = i2c_doio(&state);
741 printf("i2c_write: i2c_doio failed (%d)\n", rc);
747 #if defined(CONFIG_I2C_MULTI_BUS)
749 * Functions for multiple I2C bus handling
751 unsigned int i2c_get_bus_num(void)
756 int i2c_set_bus_num(unsigned int bus)
758 #if defined(CONFIG_I2C_MUX)
759 if (bus < CONFIG_SYS_MAX_I2C_BUS) {
764 ret = i2x_mux_select_mux(bus);
771 if (bus >= CONFIG_SYS_MAX_I2C_BUS)
778 #endif /* CONFIG_I2C_MULTI_BUS */
779 #endif /* CONFIG_HARD_I2C */