3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if defined(CONFIG_HARD_I2C)
31 #include <asm/cpm_8260.h>
34 /* define to enable debug messages */
37 DECLARE_GLOBAL_DATA_PTR;
39 #if defined(CONFIG_I2C_MULTI_BUS)
40 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
41 #endif /* CONFIG_I2C_MULTI_BUS */
43 /* uSec to wait between polls of the i2c */
45 /* uSec to wait for the CPM to start processing the buffer */
46 #define START_DELAY_US 1000
49 * tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the
50 * timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP
54 /*-----------------------------------------------------------------------
57 #ifndef CONFIG_SYS_I2C_SPEED
58 #define CONFIG_SYS_I2C_SPEED 50000
61 /*-----------------------------------------------------------------------
64 typedef void (*i2c_ecb_t)(int, int, void *); /* error callback function */
66 /* This structure keeps track of the bd and buffer space usage. */
67 typedef struct i2c_state {
68 int rx_idx; /* index to next free Rx BD */
69 int tx_idx; /* index to next free Tx BD */
70 void *rxbd; /* pointer to next free Rx BD */
71 void *txbd; /* pointer to next free Tx BD */
72 int tx_space; /* number of Tx bytes left */
73 unsigned char *tx_buf; /* pointer to free Tx area */
74 i2c_ecb_t err_cb; /* error callback function */
75 void *cb_data; /* private data to be passed */
78 /* flags for i2c_send() and i2c_receive() */
79 #define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
80 #define I2CF_START_COND 0x02 /* tx: generate start condition */
81 #define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
84 #define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */
85 #define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */
86 #define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */
87 #define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/receive */
88 #define I2CERR_IO_ERROR 5 /* had an error during comms */
90 /* error callback flags */
91 #define I2CECB_RX_ERR 0x10 /* this is a receive error */
92 #define I2CECB_RX_OV 0x02 /* receive overrun error */
93 #define I2CECB_RX_MASK 0x0f /* mask for error bits */
94 #define I2CECB_TX_ERR 0x20 /* this is a transmit error */
95 #define I2CECB_TX_CL 0x01 /* transmit collision error */
96 #define I2CECB_TX_UN 0x02 /* transmit underflow error */
97 #define I2CECB_TX_NAK 0x04 /* transmit no ack error */
98 #define I2CECB_TX_MASK 0x0f /* mask for error bits */
99 #define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
101 #define ERROR_I2C_NONE 0
102 #define ERROR_I2C_LENGTH 1
104 #define I2C_WRITE_BIT 0x00
105 #define I2C_READ_BIT 0x01
107 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
112 #define MAX_TX_SPACE 256
114 typedef struct I2C_BD
116 unsigned short status;
117 unsigned short length;
120 #define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
122 #define BD_I2C_TX_CL 0x0001 /* collision error */
123 #define BD_I2C_TX_UN 0x0002 /* underflow error */
124 #define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
125 #define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
127 #define BD_I2C_RX_ERR BD_SC_OV
130 #define PRINTD(x) printf x
136 * Returns the best value of I2BRG to meet desired clock speed of I2C with
137 * input parameters (clock speed, filter, and predivider value).
138 * It returns computer speed value and the difference between it and desired
142 i2c_roundrate(int hz, int speed, int filter, int modval,
143 int *brgval, int *totspeed)
145 int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
147 PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
148 hz, speed, filter, modval));
150 div = moddiv * speed;
151 brgdiv = (hz + div - 1) / div;
153 PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
155 *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter);
157 if ((*brgval < 0) || (*brgval > 255)) {
158 PRINTD(("\t\trejected brgval=%d\n", *brgval));
162 brgdiv = 2 * (*brgval + 3 + (2 * filter));
163 div = moddiv * brgdiv ;
164 *totspeed = hz / div;
166 PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
172 * Sets the I2C clock predivider and divider to meet required clock speed.
174 static int i2c_setrate(int hz, int speed)
176 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
177 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
180 bestspeed_diff = speed,
185 filter = 0; /* Use this fixed value */
187 for (modval = 0; modval < 4; modval++)
189 if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0)
191 int diff = speed - totspeed ;
193 if ((diff >= 0) && (diff < bestspeed_diff))
195 bestspeed_diff = diff ;
196 bestspeed_modval = modval;
197 bestspeed_brgval = brgval;
198 bestspeed_filter = filter;
203 PRINTD(("[I2C] Best is:\n"));
204 PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
206 bestspeed_filter, bestspeed_modval, bestspeed_brgval,
209 i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
210 i2c->i2c_i2brg = bestspeed_brgval & 0xff;
212 PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg));
217 void i2c_init(int speed, int slaveadd)
219 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
220 volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
221 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
224 volatile I2C_BD *rxbd, *txbd;
227 #ifdef CONFIG_SYS_I2C_INIT_BOARD
228 /* call board specific i2c bus reset routine before accessing the */
229 /* environment, which might be in a chip on that bus. For details */
230 /* about this problem see doc/I2C_Edge_Conditions. */
234 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
236 /* need to allocate dual port ram */
237 dpaddr = m8260_cpm_dpalloc(64 +
238 (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
240 *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])) = dpaddr;
244 * initialise data in dual port ram:
246 * dpaddr -> parameter ram (64 bytes)
247 * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
248 * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
249 * tx buffer (MAX_TX_SPACE bytes)
252 iip = (iic_t *)&immap->im_dprambase[dpaddr];
253 memset((void*)iip, 0, sizeof(iic_t));
256 tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
258 /* Disable interrupts */
259 i2c->i2c_i2mod = 0x00;
260 i2c->i2c_i2cmr = 0x00;
261 i2c->i2c_i2cer = 0xff;
262 i2c->i2c_i2add = slaveadd;
265 * Set the I2C BRG Clock division factor from desired i2c rate
266 * and current CPU rate (we assume sccr dfbgr field is 0;
267 * divide BRGCLK by 1)
269 PRINTD(("[I2C] Setting rate...\n"));
270 i2c_setrate (gd->brg_clk, CONFIG_SYS_I2C_SPEED) ;
272 /* Set I2C controller in master mode */
273 i2c->i2c_i2com = 0x01;
275 /* Initialize Tx/Rx parameters */
276 iip->iic_rbase = rbase;
277 iip->iic_tbase = tbase;
278 rxbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_rbase]);
279 txbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_tbase]);
281 PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
282 PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
283 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
284 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
286 /* Set big endian byte order */
287 iip->iic_tfcr = 0x10;
288 iip->iic_rfcr = 0x10;
290 /* Set maximum receive size. */
291 iip->iic_mrblr = I2C_RXTX_LEN;
293 cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
296 CPM_CR_INIT_TRX) | CPM_CR_FLG;
298 __asm__ __volatile__ ("eieio");
299 } while (cp->cp_cpcr & CPM_CR_FLG);
301 /* Clear events and interrupts */
302 i2c->i2c_i2cer = 0xff;
303 i2c->i2c_i2cmr = 0x00;
307 void i2c_newio(i2c_state_t *state)
309 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
313 PRINTD(("[I2C] i2c_newio\n"));
315 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
316 iip = (iic_t *)&immap->im_dprambase[dpaddr];
319 state->rxbd = (void*)&immap->im_dprambase[iip->iic_rbase];
320 state->txbd = (void*)&immap->im_dprambase[iip->iic_tbase];
321 state->tx_space = MAX_TX_SPACE;
322 state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
323 state->err_cb = NULL;
324 state->cb_data = NULL;
326 PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
327 PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
328 PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
330 /* clear the buffer memory */
331 memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
335 int i2c_send(i2c_state_t *state,
336 unsigned char address,
337 unsigned char secondary_address,
340 unsigned char *dataout)
342 volatile I2C_BD *txbd;
345 PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
346 address, secondary_address, flags, size));
348 /* trying to send message larger than BD */
349 if (size > I2C_RXTX_LEN)
350 return I2CERR_MSG_TOO_LONG;
352 /* no more free bds */
353 if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
354 return I2CERR_NO_BUFFERS;
356 txbd = (I2C_BD *)state->txbd;
357 txbd->addr = state->tx_buf;
359 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
361 if (flags & I2CF_START_COND)
363 PRINTD(("[I2C] Formatting addresses...\n"));
364 if (flags & I2CF_ENABLE_SECONDARY)
366 txbd->length = size + 2; /* Length of message plus dest addresses */
367 txbd->addr[0] = address << 1;
368 txbd->addr[1] = secondary_address;
373 txbd->length = size + 1; /* Length of message plus dest address */
374 txbd->addr[0] = address << 1; /* Write destination address to BD */
380 txbd->length = size; /* Length of message */
385 txbd->status = BD_SC_READY;
386 if (flags & I2CF_START_COND)
387 txbd->status |= BD_I2C_TX_START;
388 if (flags & I2CF_STOP_COND)
389 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
391 /* Copy data to send into buffer */
392 PRINTD(("[I2C] copy data...\n"));
393 for(j = 0; j < size; i++, j++)
394 txbd->addr[i] = dataout[j];
396 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
403 state->tx_buf += txbd->length;
404 state->tx_space -= txbd->length;
406 state->txbd = (void*)(txbd + 1);
412 int i2c_receive(i2c_state_t *state,
413 unsigned char address,
414 unsigned char secondary_address,
416 unsigned short size_to_expect,
417 unsigned char *datain)
419 volatile I2C_BD *rxbd, *txbd;
421 PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
423 /* Expected to receive too much */
424 if (size_to_expect > I2C_RXTX_LEN)
425 return I2CERR_MSG_TOO_LONG;
427 /* no more free bds */
428 if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
429 || state->tx_space < 2)
430 return I2CERR_NO_BUFFERS;
432 rxbd = (I2C_BD *)state->rxbd;
433 txbd = (I2C_BD *)state->txbd;
435 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
436 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
438 txbd->addr = state->tx_buf;
440 /* set up TXBD for destination address */
441 if (flags & I2CF_ENABLE_SECONDARY)
444 txbd->addr[0] = address << 1; /* Write data */
445 txbd->addr[1] = secondary_address; /* Internal address */
446 txbd->status = BD_SC_READY;
450 txbd->length = 1 + size_to_expect;
451 txbd->addr[0] = (address << 1) | 0x01;
452 txbd->status = BD_SC_READY;
453 memset(&txbd->addr[1], 0, txbd->length);
456 /* set up rxbd for reception */
457 rxbd->status = BD_SC_EMPTY;
458 rxbd->length = size_to_expect;
461 txbd->status |= BD_I2C_TX_START;
462 if (flags & I2CF_STOP_COND)
464 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
465 rxbd->status |= BD_SC_WRAP;
468 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
473 PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
480 state->tx_buf += txbd->length;
481 state->tx_space -= txbd->length;
483 state->txbd = (void*)(txbd + 1);
485 state->rxbd = (void*)(rxbd + 1);
492 int i2c_doio(i2c_state_t *state)
494 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
496 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
497 volatile I2C_BD *txbd, *rxbd;
498 int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
501 PRINTD(("[I2C] i2c_doio\n"));
503 if (state->tx_idx <= 0 && state->rx_idx <= 0) {
504 PRINTD(("[I2C] No I/O is queued\n"));
505 return I2CERR_QUEUE_EMPTY;
508 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
509 iip = (iic_t *)&immap->im_dprambase[dpaddr];
510 iip->iic_rbptr = iip->iic_rbase;
511 iip->iic_tbptr = iip->iic_tbase;
514 PRINTD(("[I2C] Enabling I2C...\n"));
515 i2c->i2c_i2mod |= 0x01;
517 /* Begin transmission */
518 i2c->i2c_i2com |= 0x80;
520 /* Loop until transmit & receive completed */
522 if ((n = state->tx_idx) > 0) {
524 txbd = ((I2C_BD*)state->txbd) - n;
525 for (i = 0; i < n; i++) {
526 txtimeo += TOUT_LOOP * txbd->length;
530 txbd--; /* wait until last in list is done */
532 PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
534 udelay(START_DELAY_US); /* give it time to start */
535 while((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) {
539 __asm__ __volatile__ ("eieio");
543 if (txcnt < txtimeo && (n = state->rx_idx) > 0) {
545 rxbd = ((I2C_BD*)state->rxbd) - n;
546 for (i = 0; i < n; i++) {
547 rxtimeo += TOUT_LOOP * rxbd->length;
551 rxbd--; /* wait until last in list is done */
553 PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
555 udelay(START_DELAY_US); /* give it time to start */
556 while((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) {
560 __asm__ __volatile__ ("eieio");
565 i2c->i2c_i2mod &= ~0x01;
567 if ((n = state->tx_idx) > 0) {
568 for (i = 0; i < n; i++) {
569 txbd = ((I2C_BD*)state->txbd) - (n - i);
570 if ((b = txbd->status & BD_I2C_TX_ERR) != 0) {
571 if (state->err_cb != NULL)
572 (*state->err_cb)(I2CECB_TX_ERR|b, i,
575 rc = I2CERR_IO_ERROR;
580 if ((n = state->rx_idx) > 0) {
581 for (i = 0; i < n; i++) {
582 rxbd = ((I2C_BD*)state->rxbd) - (n - i);
583 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) {
584 if (state->err_cb != NULL)
585 (*state->err_cb)(I2CECB_RX_ERR|b, i,
588 rc = I2CERR_IO_ERROR;
593 if ((txtimeo > 0 && txcnt >= txtimeo) || \
594 (rxtimeo > 0 && rxcnt >= rxtimeo)) {
595 if (state->err_cb != NULL)
596 (*state->err_cb)(I2CECB_TIMEOUT, -1, state->cb_data);
605 i2c_probe_callback(int flags, int xnum, void *data)
608 * the only acceptable errors are a transmit NAK or a receive
609 * overrun - tx NAK means the device does not exist, rx OV
610 * means the device must have responded to the slave address
611 * even though the transfer failed
613 if (flags == (I2CECB_TX_ERR|I2CECB_TX_NAK))
615 if (flags == (I2CECB_RX_ERR|I2CECB_RX_OV))
620 i2c_probe(uchar chip)
628 state.err_cb = i2c_probe_callback;
629 state.cb_data = (void *) &err_flag;
632 rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);
635 return (rc); /* probe failed */
637 rc = i2c_doio(&state);
640 return (0); /* device exists - read succeeded */
642 if (rc == I2CERR_TIMEOUT)
643 return (-1); /* device does not exist - timeout */
645 if (rc != I2CERR_IO_ERROR || err_flag == 0)
646 return (rc); /* probe failed */
649 return (-1); /* device does not exist - had transmit NAK */
651 return (0); /* device exists - had receive overrun */
656 i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
662 xaddr[0] = (addr >> 24) & 0xFF;
663 xaddr[1] = (addr >> 16) & 0xFF;
664 xaddr[2] = (addr >> 8) & 0xFF;
665 xaddr[3] = addr & 0xFF;
667 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
669 * EEPROM chips that implement "address overflow" are ones
670 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
671 * and the extra bits end up in the "chip address" bit slots.
672 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
675 * Note that we consider the length of the address field to still
676 * be one byte because the extra address bits are hidden in the
679 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
684 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
686 printf("i2c_read: i2c_send failed (%d)\n", rc);
690 rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
692 printf("i2c_read: i2c_receive failed (%d)\n", rc);
696 rc = i2c_doio(&state);
698 printf("i2c_read: i2c_doio failed (%d)\n", rc);
705 i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
711 xaddr[0] = (addr >> 24) & 0xFF;
712 xaddr[1] = (addr >> 16) & 0xFF;
713 xaddr[2] = (addr >> 8) & 0xFF;
714 xaddr[3] = addr & 0xFF;
716 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
718 * EEPROM chips that implement "address overflow" are ones
719 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
720 * and the extra bits end up in the "chip address" bit slots.
721 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
724 * Note that we consider the length of the address field to still
725 * be one byte because the extra address bits are hidden in the
728 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
733 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
735 printf("i2c_write: first i2c_send failed (%d)\n", rc);
739 rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
741 printf("i2c_write: second i2c_send failed (%d)\n", rc);
745 rc = i2c_doio(&state);
747 printf("i2c_write: i2c_doio failed (%d)\n", rc);
753 #if defined(CONFIG_I2C_MULTI_BUS)
755 * Functions for multiple I2C bus handling
757 unsigned int i2c_get_bus_num(void)
762 int i2c_set_bus_num(unsigned int bus)
764 #if defined(CONFIG_I2C_MUX)
765 if (bus < CONFIG_SYS_MAX_I2C_BUS) {
770 ret = i2x_mux_select_mux(bus);
777 if (bus >= CONFIG_SYS_MAX_I2C_BUS)
784 #endif /* CONFIG_I2C_MULTI_BUS */
785 #endif /* CONFIG_HARD_I2C */