2 * MPC8260 FCC Fast Ethernet
4 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * SPDX-License-Identifier: GPL-2.0+
13 * MPC8260 FCC Fast Ethernet
14 * Basic ET HW initialization and packet RX/TX routines
16 * This code will not perform the IO port configuration. This should be
17 * done in the iop_conf_t structure specific for the board.
20 * add a PHY driver to do the negotiation
21 * reflect negotiation results in FPSMR
22 * look for ways to configure the board specific stuff elsewhere, eg.
23 * config_xxx.h or the board directory
28 #include <asm/cpm_8260.h>
34 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
38 DECLARE_GLOBAL_DATA_PTR;
40 #if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET)
42 static struct ether_fcc_info_s
46 ulong cpm_cr_enet_sblock;
47 ulong cpm_cr_enet_page;
53 #ifdef CONFIG_ETHER_ON_FCC1
59 CONFIG_SYS_CMXFCR_MASK1,
60 CONFIG_SYS_CMXFCR_VALUE1
64 #ifdef CONFIG_ETHER_ON_FCC2
70 CONFIG_SYS_CMXFCR_MASK2,
71 CONFIG_SYS_CMXFCR_VALUE2
75 #ifdef CONFIG_ETHER_ON_FCC3
81 CONFIG_SYS_CMXFCR_MASK3,
82 CONFIG_SYS_CMXFCR_VALUE3
87 /*---------------------------------------------------------------------*/
89 /* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
90 #define PKT_MAXDMA_SIZE 1520
92 /* The FCC stores dest/src/type, data, and checksum for receive packets. */
93 #define PKT_MAXBUF_SIZE 1518
94 #define PKT_MINBUF_SIZE 64
96 /* Maximum input buffer size. Must be a multiple of 32. */
97 #define PKT_MAXBLR_SIZE 1536
99 #define TOUT_LOOP 1000000
103 static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8)));
105 #error "txbuf must be 64-bit aligned"
108 static uint rxIdx; /* index of the current RX buffer */
109 static uint txIdx; /* index of the current TX buffer */
112 * FCC Ethernet Tx and Rx buffer descriptors.
113 * Provide for Double Buffering
114 * Note: PKTBUFSRX is defined in net.h
117 typedef volatile struct rtxbd {
118 cbd_t rxbd[PKTBUFSRX];
119 cbd_t txbd[TX_BUF_CNT];
122 /* Good news: the FCC supports external BDs! */
124 static RTXBD rtx __attribute__ ((aligned(8)));
126 #error "rtx must be 64-bit aligned"
129 static int fec_send(struct eth_device *dev, void *packet, int length)
135 printf("fec: bad packet size: %d\n", length);
139 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
140 if (i >= TOUT_LOOP) {
141 puts ("fec: tx buffer not ready\n");
146 rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
147 rtx.txbd[txIdx].cbd_datlen = length;
148 rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
151 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
152 if (i >= TOUT_LOOP) {
153 puts ("fec: tx error\n");
159 printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc);
162 /* return only status bits */
163 result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
169 static int fec_recv(struct eth_device* dev)
175 if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
177 break; /* nothing received - leave for() loop */
179 length = rtx.rxbd[rxIdx].cbd_datlen;
181 if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
182 printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
185 /* Pass the packet up to the protocol layers. */
186 NetReceive(NetRxPackets[rxIdx], length - 4);
190 /* Give the buffer back to the FCC. */
191 rtx.rxbd[rxIdx].cbd_datlen = 0;
193 /* wrap around buffer index when necessary */
194 if ((rxIdx + 1) >= PKTBUFSRX) {
195 rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
199 rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
207 static int fec_init(struct eth_device* dev, bd_t *bis)
209 struct ether_fcc_info_s * info = dev->priv;
211 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
212 volatile cpm8260_t *cp = &(immr->im_cpm);
213 fcc_enet_t *pram_ptr;
214 unsigned long mem_addr;
220 /* 28.9 - (1-2): ioports have been set up already */
222 /* 28.9 - (3): connect FCC's tx and rx clocks */
223 immr->im_cpmux.cmx_uar = 0;
224 immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) |
227 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
228 immr->im_fcc[info->ether_index].fcc_gfmr =
229 FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
231 /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */
232 immr->im_fcc[info->ether_index].fcc_fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
234 /* 28.9 - (6): FDSR: Ethernet Syn */
235 immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555;
237 /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
241 /* Setup Receiver Buffer Descriptors */
242 for (i = 0; i < PKTBUFSRX; i++)
244 rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
245 rtx.rxbd[i].cbd_datlen = 0;
246 rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
248 rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
250 /* Setup Ethernet Transmitter Buffer Descriptors */
251 for (i = 0; i < TX_BUF_CNT; i++)
253 rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
254 rtx.txbd[i].cbd_datlen = 0;
255 rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
257 rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
259 /* 28.9 - (7): initialise parameter ram */
260 pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]);
262 /* clear whole structure to make sure all reserved fields are zero */
263 memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
266 * common Parameter RAM area
268 * Allocate space in the reserved FCC area of DPRAM for the
269 * internal buffers. No one uses this space (yet), so we
270 * can do this. Later, we will add resource management for
273 mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
274 pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
275 pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
277 * Set maximum bytes per receive buffer.
278 * It must be a multiple of 32.
280 pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
281 pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
282 CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
283 pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
284 pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
285 CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
286 pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
288 /* protocol-specific area */
289 pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
290 pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
291 pram_ptr->fen_retlim = 15; /* Retry limit threshold */
292 pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
294 * Set Ethernet station address.
296 * This is supplied in the board information structure, so we
297 * copy that into the controller.
298 * So, far we have only been given one Ethernet address. We make
299 * it unique by setting a few bits in the upper byte of the
300 * non-static part of the address.
302 #define ea eth_get_dev()->enetaddr
303 pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
304 pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
305 pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
307 pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
308 /* pad pointer. use tiptr since we don't need a specific padding char */
309 pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
310 pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
311 pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
312 pram_ptr->fen_rfthr = 1;
313 pram_ptr->fen_rfcnt = 1;
315 printf("pram_ptr->fen_genfcc.fcc_rbase %08lx\n",
316 pram_ptr->fen_genfcc.fcc_rbase);
317 printf("pram_ptr->fen_genfcc.fcc_tbase %08lx\n",
318 pram_ptr->fen_genfcc.fcc_tbase);
321 /* 28.9 - (8): clear out events in FCCE */
322 immr->im_fcc[info->ether_index].fcc_fcce = ~0x0;
324 /* 28.9 - (9): FCCM: mask all events */
325 immr->im_fcc[info->ether_index].fcc_fccm = 0;
327 /* 28.9 - (10-12): we don't use ethernet interrupts */
331 * Let's re-initialize the channel now. We have to do it later
332 * than the manual describes because we have just now finished
333 * the BD initialization.
335 cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
336 info->cpm_cr_enet_sblock,
338 CPM_CR_INIT_TRX) | CPM_CR_FLG;
340 __asm__ __volatile__ ("eieio");
341 } while (cp->cp_cpcr & CPM_CR_FLG);
343 /* 28.9 - (14): enable tx/rx in gfmr */
344 immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
349 static void fec_halt(struct eth_device* dev)
351 struct ether_fcc_info_s * info = dev->priv;
352 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
354 /* write GFMR: disable tx/rx */
355 immr->im_fcc[info->ether_index].fcc_gfmr &=
356 ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
359 int fec_initialize(bd_t *bis)
361 struct eth_device* dev;
364 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
366 dev = (struct eth_device*) malloc(sizeof *dev);
367 memset(dev, 0, sizeof *dev);
369 sprintf(dev->name, "FCC%d",
370 ether_fcc_info[i].ether_index + 1);
371 dev->priv = ðer_fcc_info[i];
372 dev->init = fec_init;
373 dev->halt = fec_halt;
374 dev->send = fec_send;
375 dev->recv = fec_recv;
379 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
380 && defined(CONFIG_BITBANGMII)
381 miiphy_register(dev->name,
382 bb_miiphy_read, bb_miiphy_write);
389 #ifdef CONFIG_ETHER_LOOPBACK_TEST
391 #define ELBT_BUFSZ 1024 /* must be multiple of 32 */
395 #define ELBT_NRXBD 4 /* must be at least 2 */
398 #define ELBT_MAXRXERR 32
399 #define ELBT_MAXTXERR 32
401 #define ELBT_CLSWAIT 1000 /* msec to wait for further input frames */
412 uint _l, _f, m, bc, mc, lg, no, sh, cr, ov, cl;
413 uint badsrc, badtyp, badlen, badbit;
417 static elbt_prdesc rxeacc_descs[] = {
418 { offsetof(elbt_rxeacc, _l), "Not Last in Frame" },
419 { offsetof(elbt_rxeacc, _f), "Not First in Frame" },
420 { offsetof(elbt_rxeacc, m), "Address Miss" },
421 { offsetof(elbt_rxeacc, bc), "Broadcast Address" },
422 { offsetof(elbt_rxeacc, mc), "Multicast Address" },
423 { offsetof(elbt_rxeacc, lg), "Frame Length Violation"},
424 { offsetof(elbt_rxeacc, no), "Non-Octet Alignment" },
425 { offsetof(elbt_rxeacc, sh), "Short Frame" },
426 { offsetof(elbt_rxeacc, cr), "CRC Error" },
427 { offsetof(elbt_rxeacc, ov), "Overrun" },
428 { offsetof(elbt_rxeacc, cl), "Collision" },
429 { offsetof(elbt_rxeacc, badsrc), "Bad Src Address" },
430 { offsetof(elbt_rxeacc, badtyp), "Bad Frame Type" },
431 { offsetof(elbt_rxeacc, badlen), "Bad Frame Length" },
432 { offsetof(elbt_rxeacc, badbit), "Data Compare Errors" },
434 static int rxeacc_ndesc = sizeof (rxeacc_descs) / sizeof (rxeacc_descs[0]);
438 uint def, hb, lc, rl, rc, un, csl;
442 static elbt_prdesc txeacc_descs[] = {
443 { offsetof(elbt_txeacc, def), "Defer Indication" },
444 { offsetof(elbt_txeacc, hb), "Heartbeat" },
445 { offsetof(elbt_txeacc, lc), "Late Collision" },
446 { offsetof(elbt_txeacc, rl), "Retransmission Limit" },
447 { offsetof(elbt_txeacc, rc), "Retry Count" },
448 { offsetof(elbt_txeacc, un), "Underrun" },
449 { offsetof(elbt_txeacc, csl), "Carrier Sense Lost" },
451 static int txeacc_ndesc = sizeof (txeacc_descs) / sizeof (txeacc_descs[0]);
455 uchar rxbufs[ELBT_NRXBD][ELBT_BUFSZ];
456 uchar txbufs[ELBT_NTXBD][ELBT_BUFSZ];
457 cbd_t rxbd[ELBT_NRXBD];
458 cbd_t txbd[ELBT_NTXBD];
459 enum { Idle, Running, Closing, Closed } state;
460 int proff, page, sblock;
461 uint clstime, nsent, ntxerr, nrcvd, nrxerr;
462 ushort rxerrs[ELBT_MAXRXERR], txerrs[ELBT_MAXTXERR];
465 } __attribute__ ((aligned(8)))
468 static uchar patbytes[ELBT_NTXBD] = {
469 0xff, 0xaa, 0x55, 0x00
471 static uint patwords[ELBT_NTXBD] = {
472 0xffffffff, 0xaaaaaaaa, 0x55555555, 0x00000000
476 static elbt_chan elbt_chans[3] __attribute__ ((aligned(8)));
478 #error "elbt_chans must be 64-bit aligned"
481 #define CPM_CR_GRACEFUL_STOP_TX ((ushort)0x0005)
483 static elbt_prdesc epram_descs[] = {
484 { offsetof(fcc_enet_t, fen_crcec), "CRC Errors" },
485 { offsetof(fcc_enet_t, fen_alec), "Alignment Errors" },
486 { offsetof(fcc_enet_t, fen_disfc), "Discarded Frames" },
487 { offsetof(fcc_enet_t, fen_octc), "Octets" },
488 { offsetof(fcc_enet_t, fen_colc), "Collisions" },
489 { offsetof(fcc_enet_t, fen_broc), "Broadcast Frames" },
490 { offsetof(fcc_enet_t, fen_mulc), "Multicast Frames" },
491 { offsetof(fcc_enet_t, fen_uspc), "Undersize Frames" },
492 { offsetof(fcc_enet_t, fen_frgc), "Fragments" },
493 { offsetof(fcc_enet_t, fen_ospc), "Oversize Frames" },
494 { offsetof(fcc_enet_t, fen_jbrc), "Jabbers" },
495 { offsetof(fcc_enet_t, fen_p64c), "64 Octet Frames" },
496 { offsetof(fcc_enet_t, fen_p65c), "65-127 Octet Frames" },
497 { offsetof(fcc_enet_t, fen_p128c), "128-255 Octet Frames" },
498 { offsetof(fcc_enet_t, fen_p256c), "256-511 Octet Frames" },
499 { offsetof(fcc_enet_t, fen_p512c), "512-1023 Octet Frames" },
500 { offsetof(fcc_enet_t, fen_p1024c), "1024-1518 Octet Frames"},
502 static int epram_ndesc = sizeof (epram_descs) / sizeof (epram_descs[0]);
505 * given an elbt_prdesc array and an array of base addresses, print
506 * each prdesc down the screen with the values fetched from each
507 * base address across the screen
510 print_desc (elbt_prdesc descs[], int ndesc, uchar *bases[], int nbase)
512 elbt_prdesc *dp = descs, *edp = dp + ndesc;
517 for (i = 0; i < nbase; i++)
518 printf (" Channel %d", i);
524 printf ("%-32s", dp->lab);
526 for (i = 0; i < nbase; i++) {
527 uint val = *(uint *)(bases[i] + dp->off);
529 printf (" %10u", val);
539 * return number of bits that are set in a value; value contains
540 * nbits (right-justified) bits.
542 static uint __inline__
543 nbs (uint value, uint nbits)
547 uint pos = sizeof (uint) * 8;
549 __asm__ __volatile__ ("\
551 1: rlwnm. %2,%1,%4,31,31\n\
557 : "r"(value), "r"(nbits), "r"(cnt), "r"(pos)
573 badbits (uchar *bp, int n, ulong pat)
578 while (n > 0 && ((ulong)bp & (sizeof (ulong) - 1)) != 0) {
581 diff = *bp++ ^ (uchar)pat;
584 cnt += nbs ((ulong)diff, 8);
590 nl = n / sizeof (ulong);
591 n -= nl * sizeof (ulong);
599 cnt += nbs (diff, 32);
609 diff = *bp++ ^ (uchar)pat;
612 cnt += nbs ((ulong)diff, 8);
620 static inline unsigned short
621 swap16 (unsigned short x)
623 return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
626 /* broadcast is not an error - we send them like that */
627 #define BD_ENET_RX_ERRS (BD_ENET_RX_STATS & ~BD_ENET_RX_BC)
630 eth_loopback_test (void)
632 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
633 volatile cpm8260_t *cp = &(immr->im_cpm);
635 ulong runtime, nmsec;
638 puts ("FCC Ethernet External loopback test\n");
640 eth_getenv_enetaddr("ethaddr", NetOurEther);
643 * global initialisations for all FCC channels
646 /* 28.9 - (1-2): ioports have been set up already */
648 #if defined(CONFIG_SACSng)
650 * Attention: this is board-specific
653 # define FCC_START_LOOP 1
654 # define FCC_END_LOOP 1
657 * Attention: this is board-specific
658 * - FCC2 Rx-CLK is CLK13
659 * - FCC2 Tx-CLK is CLK14
662 /* 28.9 - (3): connect FCC's tx and rx clocks */
663 immr->im_cpmux.cmx_uar = 0;
664 immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14;
666 #error "eth_loopback_test not supported on your board"
669 puts ("Initialise FCC channels:");
671 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
672 elbt_chan *ecp = &elbt_chans[c];
673 volatile fcc_t *fcp = &immr->im_fcc[c];
674 volatile fcc_enet_t *fpp;
679 * initialise channel data
684 memset ((void *)ecp, 0, sizeof (*ecp));
691 ecp->proff = PROFF_FCC1;
692 ecp->page = CPM_CR_FCC1_PAGE;
693 ecp->sblock = CPM_CR_FCC1_SBLOCK;
697 ecp->proff = PROFF_FCC2;
698 ecp->page = CPM_CR_FCC2_PAGE;
699 ecp->sblock = CPM_CR_FCC2_SBLOCK;
703 ecp->proff = PROFF_FCC3;
704 ecp->page = CPM_CR_FCC3_PAGE;
705 ecp->sblock = CPM_CR_FCC3_SBLOCK;
710 * set up tx buffers and bds
713 for (i = 0; i < ELBT_NTXBD; i++) {
714 cbd_t *bdp = &ecp->txbd[i];
715 uchar *bp = &ecp->txbufs[i][0];
717 bdp->cbd_bufaddr = (uint)bp;
719 bdp->cbd_datlen = ELBT_BUFSZ - ELBT_CRCSZ;
720 bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \
721 BD_ENET_TX_LAST | BD_ENET_TX_TC;
723 memset ((void *)bp, patbytes[i], ELBT_BUFSZ);
724 NetSetEther (bp, NetBcastAddr, 0x8000);
726 ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP;
729 * set up rx buffers and bds
732 for (i = 0; i < ELBT_NRXBD; i++) {
733 cbd_t *bdp = &ecp->rxbd[i];
734 uchar *bp = &ecp->rxbufs[i][0];
736 bdp->cbd_bufaddr = (uint)bp;
738 bdp->cbd_sc = BD_ENET_RX_EMPTY;
740 memset ((void *)bp, 0, ELBT_BUFSZ);
742 ecp->rxbd[ELBT_NRXBD - 1].cbd_sc |= BD_ENET_RX_WRAP;
745 * set up the FCC channel hardware
748 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
749 fcp->fcc_gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
751 /* 28.9 - (5): FPSMR: fd, enet CRC, Promis, RMON, Rx SHort */
752 fcp->fcc_fpsmr = FCC_PSMR_FDE | FCC_PSMR_LPB | \
753 FCC_PSMR_ENCRC | FCC_PSMR_PRO | \
754 FCC_PSMR_MON | FCC_PSMR_RSH;
756 /* 28.9 - (6): FDSR: Ethernet Syn */
757 fcp->fcc_fdsr = 0xD555;
759 /* 29.9 - (7): initialise parameter ram */
760 fpp = (fcc_enet_t *)&(immr->im_dprambase[ecp->proff]);
762 /* clear whole struct to make sure all resv fields are zero */
763 memset ((void *)fpp, 0, sizeof (fcc_enet_t));
766 * common Parameter RAM area
768 * Allocate space in the reserved FCC area of DPRAM for the
769 * internal buffers. No one uses this space (yet), so we
770 * can do this. Later, we will add resource management for
773 addr = CPM_FCC_SPECIAL_BASE + (c * 64);
774 fpp->fen_genfcc.fcc_riptr = addr;
775 fpp->fen_genfcc.fcc_tiptr = addr + 32;
778 * Set maximum bytes per receive buffer.
779 * It must be a multiple of 32.
780 * buffers are in 60x bus memory.
782 fpp->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
783 fpp->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
784 fpp->fen_genfcc.fcc_rbase = (unsigned int)(&ecp->rxbd[0]);
785 fpp->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
786 fpp->fen_genfcc.fcc_tbase = (unsigned int)(&ecp->txbd[0]);
788 /* protocol-specific area */
789 fpp->fen_cmask = 0xdebb20e3; /* CRC mask */
790 fpp->fen_cpres = 0xffffffff; /* CRC preset */
791 fpp->fen_retlim = 15; /* Retry limit threshold */
792 fpp->fen_mflr = PKT_MAXBUF_SIZE;/* max frame length register */
795 * Set Ethernet station address.
797 * This is supplied in the board information structure, so we
798 * copy that into the controller.
799 * So, far we have only been given one Ethernet address. We use
800 * the same address for all channels
802 #define ea NetOurEther
803 fpp->fen_paddrh = (ea[5] << 8) + ea[4];
804 fpp->fen_paddrm = (ea[3] << 8) + ea[2];
805 fpp->fen_paddrl = (ea[1] << 8) + ea[0];
808 fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */
810 * pad pointer. use tiptr since we don't need
811 * a specific padding char
813 fpp->fen_padptr = fpp->fen_genfcc.fcc_tiptr;
814 fpp->fen_maxd1 = PKT_MAXDMA_SIZE; /* max DMA1 length */
815 fpp->fen_maxd2 = PKT_MAXDMA_SIZE; /* max DMA2 length */
819 /* 28.9 - (8): clear out events in FCCE */
820 fcp->fcc_fcce = ~0x0;
822 /* 28.9 - (9): FCCM: mask all events */
825 /* 28.9 - (10-12): we don't use ethernet interrupts */
829 * Let's re-initialize the channel now. We have to do it later
830 * than the manual describes because we have just now finished
831 * the BD initialization.
833 cp->cp_cpcr = mk_cr_cmd (ecp->page, ecp->sblock, \
834 0x0c, CPM_CR_INIT_TRX) | CPM_CR_FLG;
836 __asm__ __volatile__ ("eieio");
837 } while (cp->cp_cpcr & CPM_CR_FLG);
840 puts (" done\nStarting test... (Ctrl-C to Finish)\n");
843 * Note: don't want serial output from here until the end of the
844 * test - the delays would probably stuff things up.
848 runtime = get_timer (0);
853 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
854 volatile fcc_t *fcp = &immr->im_fcc[c];
855 elbt_chan *ecp = &elbt_chans[c];
858 switch (ecp->state) {
862 * set the channel Running ...
865 /* 28.9 - (14): enable tx/rx in gfmr */
866 fcp->fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
868 ecp->state = Running;
873 * (while Running only) check for
874 * termination of the test
881 * initiate a "graceful stop transmit"
884 cp->cp_cpcr = mk_cr_cmd (ecp->page, \
886 CPM_CR_GRACEFUL_STOP_TX) | \
889 __asm__ __volatile__ ("eieio");
890 } while (cp->cp_cpcr & CPM_CR_FLG);
892 ecp->clstime = get_timer (0);
893 ecp->state = Closing;
895 /* fall through ... */
899 * (while Running or Closing) poll the channel:
900 * - check for any non-READY tx buffers and
902 * - check for any non-EMPTY rx buffers and
903 * check that they were received correctly,
904 * adjust counters etc, then make empty
907 for (i = 0; i < ELBT_NTXBD; i++) {
908 cbd_t *bdp = &ecp->txbd[i];
909 ushort sc = bdp->cbd_sc;
911 if ((sc & BD_ENET_TX_READY) != 0)
915 * this frame has finished
920 if (sc & BD_ENET_TX_STATS) {
928 if (n < ELBT_MAXTXERR)
931 if (sc & BD_ENET_TX_DEF)
933 if (sc & BD_ENET_TX_HB)
935 if (sc & BD_ENET_TX_LC)
937 if (sc & BD_ENET_TX_RL)
939 if (sc & BD_ENET_TX_RCMASK)
941 if (sc & BD_ENET_TX_UN)
943 if (sc & BD_ENET_TX_CSL)
950 if (ecp->state == Closing)
951 ecp->clstime = get_timer (0);
953 /* make it ready again */
954 bdp->cbd_sc |= BD_ENET_TX_READY;
957 for (i = 0; i < ELBT_NRXBD; i++) {
958 cbd_t *bdp = &ecp->rxbd[i];
959 ushort sc = bdp->cbd_sc, mask;
961 if ((sc & BD_ENET_RX_EMPTY) != 0)
964 /* we have a new frame in this buffer */
967 mask = BD_ENET_RX_LAST|BD_ENET_RX_FIRST;
968 if ((sc & mask) != mask) {
969 /* somethings wrong here ... */
970 if (!(sc & BD_ENET_RX_LAST))
972 if (!(sc & BD_ENET_RX_FIRST))
976 if (sc & BD_ENET_RX_ERRS) {
980 * we had some sort of error
984 if (n < ELBT_MAXRXERR)
987 if (sc & BD_ENET_RX_MISS)
989 if (sc & BD_ENET_RX_BC)
991 if (sc & BD_ENET_RX_MC)
993 if (sc & BD_ENET_RX_LG)
995 if (sc & BD_ENET_RX_NO)
997 if (sc & BD_ENET_RX_SH)
999 if (sc & BD_ENET_RX_CR)
1001 if (sc & BD_ENET_RX_OV)
1003 if (sc & BD_ENET_RX_CL)
1010 ushort datlen = bdp->cbd_datlen;
1011 struct ethernet_hdr *ehp;
1013 int ours, tb, n, nbytes;
1015 ehp = (struct ethernet_hdr *) \
1018 ours = memcmp (ehp->et_src, \
1021 prot = swap16 (ehp->et_protlen);
1025 nbytes = ELBT_BUFSZ -
1029 /* check the frame is correct */
1030 if (datlen != ELBT_BUFSZ)
1031 ecp->rxeacc.badlen++;
1033 ecp->rxeacc.badsrc++;
1034 else if (!tb || n >= ELBT_NTXBD)
1035 ecp->rxeacc.badtyp++;
1046 ecp->rxeacc.badbit += \
1051 if (ecp->state == Closing)
1052 ecp->clstime = get_timer (0);
1054 /* make it empty again */
1055 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
1058 if (ecp->state != Closing)
1062 * (while Closing) check to see if
1063 * waited long enough
1066 if (get_timer (ecp->clstime) >= ELBT_CLSWAIT) {
1067 /* write GFMR: disable tx/rx */
1069 ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
1070 ecp->state = Closed;
1081 } while (nclosed < (FCC_END_LOOP - FCC_START_LOOP + 1));
1083 runtime = get_timer (runtime);
1084 if (runtime <= ELBT_CLSWAIT) {
1085 printf ("Whoops! somehow elapsed time (%ld) is wrong (<= %d)\n",
1086 runtime, ELBT_CLSWAIT);
1089 nmsec = runtime - ELBT_CLSWAIT;
1091 printf ("Test Finished in %ldms (plus %dms close wait period)!\n\n",
1092 nmsec, ELBT_CLSWAIT);
1098 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++) {
1099 elbt_chan *ecp = &elbt_chans[c];
1100 uint rxpps, txpps, nerr;
1102 rxpps = (ecp->nrcvd * 1000) / nmsec;
1103 txpps = (ecp->nsent * 1000) / nmsec;
1105 printf ("Channel %d: %d rcvd (%d pps, %d rxerrs), "
1106 "%d sent (%d pps, %d txerrs)\n\n", c,
1107 ecp->nrcvd, rxpps, ecp->nrxerr,
1108 ecp->nsent, txpps, ecp->ntxerr);
1110 if ((nerr = ecp->nrxerr) > 0) {
1113 printf ("\tFirst %d rx errs:", nerr);
1114 for (i = 0; i < nerr; i++)
1115 printf (" %04x", ecp->rxerrs[i]);
1119 if ((nerr = ecp->ntxerr) > 0) {
1122 printf ("\tFirst %d tx errs:", nerr);
1123 for (i = 0; i < nerr; i++)
1124 printf (" %04x", ecp->txerrs[i]);
1129 puts ("Receive Error Counts:\n");
1130 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
1131 bases[c] = (uchar *)&elbt_chans[c].rxeacc;
1132 print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3);
1134 puts ("\nTransmit Error Counts:\n");
1135 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
1136 bases[c] = (uchar *)&elbt_chans[c].txeacc;
1137 print_desc (txeacc_descs, txeacc_ndesc, bases, 3);
1139 puts ("\nRMON(-like) Counters:\n");
1140 for (c = FCC_START_LOOP; c <= FCC_END_LOOP; c++)
1141 bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff];
1142 print_desc (epram_descs, epram_ndesc, bases, 3);
1145 #endif /* CONFIG_ETHER_LOOPBACK_TEST */