2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * U-Boot - Startup Code for MPC8220 CPUs
28 #include <asm-offsets.h>
31 #include <timestamp.h>
34 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
36 #include <ppc_asm.tmpl>
39 #include <asm/cache.h>
41 #include <asm/u-boot.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING ""
47 /* We don't want the MMU yet.
50 /* Floating Point enable, Machine Check and Recoverable Interr. */
52 #define MSR_KERNEL (MSR_FP|MSR_RI)
54 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
58 * Set up GOT: Global Offset Table
60 * Use r12 to access the GOT
63 GOT_ENTRY(_GOT2_TABLE_)
64 GOT_ENTRY(_FIXUP_TABLE_)
67 GOT_ENTRY(_start_of_vectors)
68 GOT_ENTRY(_end_of_vectors)
69 GOT_ENTRY(transfer_to_handler)
72 GOT_ENTRY(__bss_end__)
73 GOT_ENTRY(__bss_start)
83 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
84 .ascii CONFIG_IDENT_STRING, "\0"
93 mfmsr r5 /* save msr contents */
95 /* replace default MBAR base address from 0x80000000
98 #if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
99 lis r3, CONFIG_SYS_MBAR@h
100 ori r3, r3, CONFIG_SYS_MBAR@l
102 /* MBAR is mirrored into the MBAR SPR */
105 lis r4, CONFIG_SYS_DEFAULT_MBAR@h
107 #endif /* CONFIG_SYS_DEFAULT_MBAR */
109 /* Initialise the MPC8220 processor core */
110 /*--------------------------------------------------------------*/
114 /* initialize some things that are hard to access from C */
115 /*--------------------------------------------------------------*/
117 /* set up stack in on-chip SRAM */
118 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
119 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
120 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
122 li r0, 0 /* Make room for stack frame header and */
123 stwu r0, -4(r1) /* clear final stack frame so that */
124 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
126 /* let the C-code set up the rest */
128 /* Be careful to keep code relocatable ! */
129 /*--------------------------------------------------------------*/
131 GET_GOT /* initialize GOT access */
132 #if defined(__pic__) && __pic__ == 1
133 /* Needed for upcoming -msingle-pic-base */
134 bl _GLOBAL_OFFSET_TABLE_@local-4
138 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
140 bl board_init_f /* run 1st part of board init code (in Flash)*/
142 /* NOTREACHED - board_init_f() does not return */
148 .globl _start_of_vectors
152 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
154 /* Data Storage exception. */
155 STD_EXCEPTION(0x300, DataStorage, UnknownException)
157 /* Instruction Storage exception. */
158 STD_EXCEPTION(0x400, InstStorage, UnknownException)
160 /* External Interrupt exception. */
161 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
163 /* Alignment exception. */
166 EXCEPTION_PROLOG(SRR0, SRR1)
171 addi r3,r1,STACK_FRAME_OVERHEAD
172 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
174 /* Program check exception */
177 EXCEPTION_PROLOG(SRR0, SRR1)
178 addi r3,r1,STACK_FRAME_OVERHEAD
179 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
182 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
184 /* I guess we could implement decrementer, and may have
185 * to someday for timekeeping.
187 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
189 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
190 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
191 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
192 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
194 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
195 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
197 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
198 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
199 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
203 * This exception occurs when the program counter matches the
204 * Instruction Address Breakpoint Register (IABR).
206 * I want the cpu to halt if this occurs so I can hunt around
207 * with the debugger and look at things.
209 * When DEBUG is defined, both machine check enable (in the MSR)
210 * and checkstop reset enable (in the reset mode register) are
211 * turned off and so a checkstop condition will result in the cpu
214 * I force the cpu into a checkstop condition by putting an illegal
215 * instruction here (at least this is the theory).
217 * well - that didnt work, so just do an infinite loop!
221 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
223 STD_EXCEPTION(0x1400, SMI, UnknownException)
225 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
226 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
227 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
228 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
229 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
230 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
231 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
232 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
233 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
234 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
235 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
236 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
237 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
238 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
239 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
240 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
241 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
242 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
243 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
244 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
245 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
246 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
247 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
248 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
249 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
250 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
251 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
254 .globl _end_of_vectors
260 * This code finishes saving the registers to the exception frame
261 * and jumps to the appropriate handler for the exception.
262 * Register r21 is pointer into trap frame, r1 has new stack pointer.
264 .globl transfer_to_handler
275 andi. r24,r23,0x3f00 /* get vector offset */
279 lwz r24,0(r23) /* virtual address of handler */
280 lwz r23,4(r23) /* where to go when done */
285 rfi /* jump to handler, enable MMU */
288 mfmsr r28 /* Disable interrupts */
292 SYNC /* Some chip revs need this... */
307 lwz r2,_NIP(r1) /* Restore environment */
318 * This code initialises the MPC8220 processor core
319 * (conforms to PowerPC 603e spec)
320 * Note: expects original MSR contents to be in r5.
323 .globl init_8220_core
326 /* Initialize machine status; enable machine check interrupt */
327 /*--------------------------------------------------------------*/
329 li r3, MSR_KERNEL /* Set ME and RI flags */
330 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
332 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
334 SYNC /* Some chip revs need this... */
337 mtspr SRR1, r3 /* Make SRR1 match MSR */
339 /* Initialize the Hardware Implementation-dependent Registers */
340 /* HID0 also contains cache control */
341 /*--------------------------------------------------------------*/
343 lis r3, CONFIG_SYS_HID0_INIT@h
344 ori r3, r3, CONFIG_SYS_HID0_INIT@l
348 lis r3, CONFIG_SYS_HID0_FINAL@h
349 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
353 /* Enable Extra BATs */
354 mfspr r3, 1011 /* HID2 */
361 /* clear all BAT's */
362 /*--------------------------------------------------------------*/
399 /* invalidate all tlb's */
401 /* From the 603e User Manual: "The 603e provides the ability to */
402 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
403 /* instruction invalidates the TLB entry indexed by the EA, and */
404 /* operates on both the instruction and data TLBs simultaneously*/
405 /* invalidating four TLB entries (both sets in each TLB). The */
406 /* index corresponds to bits 15-19 of the EA. To invalidate all */
407 /* entries within both TLBs, 32 tlbie instructions should be */
408 /* issued, incrementing this field by one each time." */
410 /* "Note that the tlbia instruction is not implemented on the */
413 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
414 /* incrementing by 0x1000 each time. The code below is sort of */
415 /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
417 /*--------------------------------------------------------------*/
428 /*--------------------------------------------------------------*/
434 * Note: requires that all cache bits in
435 * HID0 are in the low half word.
440 ori r4, r4, CONFIG_SYS_HID0_INIT /* set ICE & ICFI bit */
441 rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */
444 * The setting of the instruction cache enable (ICE) bit must be
445 * preceded by an isync instruction to prevent the cache from being
446 * enabled or disabled while an instruction access is in progress.
449 mtspr HID0, r4 /* Enable Instr Cache & Inval cache */
450 mtspr HID0, r3 /* using 2 consec instructions */
454 .globl icache_disable
457 rlwinm r3, r3, 0, 17, 15 /* clear the ICE bit */
465 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
471 ori r4, r4, HID0_DCE|HID0_DCFI /* set DCE & DCFI bit */
472 rlwinm r3, r4, 0, 22, 20 /* clear the DCFI bit */
474 /* Enable address translation in MSR bit */
480 * The setting of the instruction cache enable (ICE) bit must be
481 * preceded by an isync instruction to prevent the cache from being
482 * enabled or disabled while an instruction access is in progress.
485 mtspr HID0, r4 /* Enable Data Cache & Inval cache*/
486 mtspr HID0, r3 /* using 2 consec instructions */
490 .globl dcache_disable
493 rlwinm r3, r3, 0, 18, 16 /* clear the DCE bit */
501 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
509 /*------------------------------------------------------------------------------*/
512 * void relocate_code (addr_sp, gd, addr_moni)
514 * This "function" does not return, instead it continues in RAM
515 * after relocating the monitor code.
519 * r5 = length in bytes
524 mr r1, r3 /* Set new stack pointer */
525 mr r9, r4 /* Save copy of Global Data pointer */
526 mr r10, r5 /* Save copy of Destination Address */
529 #if defined(__pic__) && __pic__ == 1
530 /* Needed for upcoming -msingle-pic-base */
531 bl _GLOBAL_OFFSET_TABLE_@local-4
534 mr r3, r5 /* Destination Address */
535 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
536 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
537 lwz r5, GOT(__init_end)
539 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
544 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
550 /* First our own GOT */
552 /* then the one used by the C code */
562 beq cr1,4f /* In place copy is not necessary */
563 beq 7f /* Protect against 0 count */
582 * Now flush the cache: note that we must start from a cache aligned
583 * address. Otherwise we might miss one cache line.
587 beq 7f /* Always flush prefetch queue in any case */
590 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
591 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
599 sync /* Wait for all dcbst to complete on bus */
600 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
601 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
609 7: sync /* Wait for all icbi to complete on bus */
613 * We are done. Do not return, instead branch to second part of board
614 * initialization, now running from RAM.
617 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
624 * Relocation Function, r12 point to got2+0x8000
626 * Adjust got2 pointers, no need to check for 0, this code
627 * already puts a few entries in the table.
629 li r0,__got2_entries@sectoff@l
630 la r3,GOT(_GOT2_TABLE_)
631 lwz r11,GOT(_GOT2_TABLE_)
643 * Now adjust the fixups and the pointers to the fixups
644 * in case we need to move ourselves again.
646 li r0,__fixup_entries@sectoff@l
647 lwz r3,GOT(_FIXUP_TABLE_)
663 * Now clear BSS segment
665 lwz r3,GOT(__bss_start)
666 lwz r4,GOT(__bss_end__)
679 mr r3, r9 /* Global Data pointer */
680 mr r4, r10 /* Destination Address */
684 * Copy exception vector code to low memory
687 * r7: source address, r8: end address, r9: target address
691 mflr r4 /* save link register */
694 lwz r8, GOT(_end_of_vectors)
696 li r9, 0x100 /* reset vector always at 0x100 */
699 bgelr /* return if r7>=r8 - just in case */
709 * relocate `hdlr' and `int_return' entries
711 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
712 li r8, Alignment - _start + EXC_OFF_SYS_RESET
715 addi r7, r7, 0x100 /* next exception vector */
719 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
722 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
725 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
726 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
729 addi r7, r7, 0x100 /* next exception vector */
733 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
734 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
737 addi r7, r7, 0x100 /* next exception vector */
741 mfmsr r3 /* now that the vectors have */
742 lis r7, MSR_IP@h /* relocated into low memory */
743 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
744 andc r3, r3, r7 /* (if it was on) */
745 SYNC /* Some chip revs need this... */
749 mtlr r4 /* restore link register */