2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * U-Boot - Startup Code for MPC8220 CPUs
30 #include <timestamp.h>
33 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
35 #include <ppc_asm.tmpl>
38 #include <asm/cache.h>
41 #ifndef CONFIG_IDENT_STRING
42 #define CONFIG_IDENT_STRING ""
45 /* We don't want the MMU yet.
48 /* Floating Point enable, Machine Check and Recoverable Interr. */
50 #define MSR_KERNEL (MSR_FP|MSR_RI)
52 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
56 * Set up GOT: Global Offset Table
58 * Use r12 to access the GOT
61 GOT_ENTRY(_GOT2_TABLE_)
62 GOT_ENTRY(_FIXUP_TABLE_)
65 GOT_ENTRY(_start_of_vectors)
66 GOT_ENTRY(_end_of_vectors)
67 GOT_ENTRY(transfer_to_handler)
71 GOT_ENTRY(__bss_start)
81 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
82 .ascii CONFIG_IDENT_STRING, "\0"
91 mfmsr r5 /* save msr contents */
93 /* replace default MBAR base address from 0x80000000
96 #if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
97 lis r3, CONFIG_SYS_MBAR@h
98 ori r3, r3, CONFIG_SYS_MBAR@l
100 /* MBAR is mirrored into the MBAR SPR */
103 lis r4, CONFIG_SYS_DEFAULT_MBAR@h
105 #endif /* CONFIG_SYS_DEFAULT_MBAR */
107 /* Initialise the MPC8220 processor core */
108 /*--------------------------------------------------------------*/
112 /* initialize some things that are hard to access from C */
113 /*--------------------------------------------------------------*/
115 /* set up stack in on-chip SRAM */
116 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
117 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
118 ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
120 li r0, 0 /* Make room for stack frame header and */
121 stwu r0, -4(r1) /* clear final stack frame so that */
122 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
124 /* let the C-code set up the rest */
126 /* Be careful to keep code relocatable ! */
127 /*--------------------------------------------------------------*/
129 GET_GOT /* initialize GOT access */
132 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
134 bl board_init_f /* run 1st part of board init code (in Flash)*/
136 /* NOTREACHED - board_init_f() does not return */
142 .globl _start_of_vectors
146 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
148 /* Data Storage exception. */
149 STD_EXCEPTION(0x300, DataStorage, UnknownException)
151 /* Instruction Storage exception. */
152 STD_EXCEPTION(0x400, InstStorage, UnknownException)
154 /* External Interrupt exception. */
155 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
157 /* Alignment exception. */
160 EXCEPTION_PROLOG(SRR0, SRR1)
165 addi r3,r1,STACK_FRAME_OVERHEAD
166 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
168 /* Program check exception */
171 EXCEPTION_PROLOG(SRR0, SRR1)
172 addi r3,r1,STACK_FRAME_OVERHEAD
173 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
176 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
178 /* I guess we could implement decrementer, and may have
179 * to someday for timekeeping.
181 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
183 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
184 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
185 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
186 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
188 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
189 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
191 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
192 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
193 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
197 * This exception occurs when the program counter matches the
198 * Instruction Address Breakpoint Register (IABR).
200 * I want the cpu to halt if this occurs so I can hunt around
201 * with the debugger and look at things.
203 * When DEBUG is defined, both machine check enable (in the MSR)
204 * and checkstop reset enable (in the reset mode register) are
205 * turned off and so a checkstop condition will result in the cpu
208 * I force the cpu into a checkstop condition by putting an illegal
209 * instruction here (at least this is the theory).
211 * well - that didnt work, so just do an infinite loop!
215 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
217 STD_EXCEPTION(0x1400, SMI, UnknownException)
219 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
220 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
221 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
222 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
223 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
224 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
225 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
226 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
227 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
228 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
229 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
230 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
231 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
232 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
233 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
234 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
235 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
236 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
237 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
238 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
239 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
240 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
241 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
242 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
243 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
244 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
245 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
248 .globl _end_of_vectors
254 * This code finishes saving the registers to the exception frame
255 * and jumps to the appropriate handler for the exception.
256 * Register r21 is pointer into trap frame, r1 has new stack pointer.
258 .globl transfer_to_handler
269 andi. r24,r23,0x3f00 /* get vector offset */
273 lwz r24,0(r23) /* virtual address of handler */
274 lwz r23,4(r23) /* where to go when done */
279 rfi /* jump to handler, enable MMU */
282 mfmsr r28 /* Disable interrupts */
286 SYNC /* Some chip revs need this... */
301 lwz r2,_NIP(r1) /* Restore environment */
312 * This code initialises the MPC8220 processor core
313 * (conforms to PowerPC 603e spec)
314 * Note: expects original MSR contents to be in r5.
317 .globl init_8220_core
320 /* Initialize machine status; enable machine check interrupt */
321 /*--------------------------------------------------------------*/
323 li r3, MSR_KERNEL /* Set ME and RI flags */
324 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
326 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
328 SYNC /* Some chip revs need this... */
331 mtspr SRR1, r3 /* Make SRR1 match MSR */
333 /* Initialize the Hardware Implementation-dependent Registers */
334 /* HID0 also contains cache control */
335 /*--------------------------------------------------------------*/
337 lis r3, CONFIG_SYS_HID0_INIT@h
338 ori r3, r3, CONFIG_SYS_HID0_INIT@l
342 lis r3, CONFIG_SYS_HID0_FINAL@h
343 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
347 /* Enable Extra BATs */
348 mfspr r3, 1011 /* HID2 */
355 /* clear all BAT's */
356 /*--------------------------------------------------------------*/
393 /* invalidate all tlb's */
395 /* From the 603e User Manual: "The 603e provides the ability to */
396 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
397 /* instruction invalidates the TLB entry indexed by the EA, and */
398 /* operates on both the instruction and data TLBs simultaneously*/
399 /* invalidating four TLB entries (both sets in each TLB). The */
400 /* index corresponds to bits 15-19 of the EA. To invalidate all */
401 /* entries within both TLBs, 32 tlbie instructions should be */
402 /* issued, incrementing this field by one each time." */
404 /* "Note that the tlbia instruction is not implemented on the */
407 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
408 /* incrementing by 0x1000 each time. The code below is sort of */
409 /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
411 /*--------------------------------------------------------------*/
422 /*--------------------------------------------------------------*/
428 * Note: requires that all cache bits in
429 * HID0 are in the low half word.
434 ori r4, r4, CONFIG_SYS_HID0_INIT /* set ICE & ICFI bit */
435 rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */
438 * The setting of the instruction cache enable (ICE) bit must be
439 * preceded by an isync instruction to prevent the cache from being
440 * enabled or disabled while an instruction access is in progress.
443 mtspr HID0, r4 /* Enable Instr Cache & Inval cache */
444 mtspr HID0, r3 /* using 2 consec instructions */
448 .globl icache_disable
451 rlwinm r3, r3, 0, 17, 15 /* clear the ICE bit */
459 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
465 ori r4, r4, HID0_DCE|HID0_DCFI /* set DCE & DCFI bit */
466 rlwinm r3, r4, 0, 22, 20 /* clear the DCFI bit */
468 /* Enable address translation in MSR bit */
474 * The setting of the instruction cache enable (ICE) bit must be
475 * preceded by an isync instruction to prevent the cache from being
476 * enabled or disabled while an instruction access is in progress.
479 mtspr HID0, r4 /* Enable Data Cache & Inval cache*/
480 mtspr HID0, r3 /* using 2 consec instructions */
484 .globl dcache_disable
487 rlwinm r3, r3, 0, 18, 16 /* clear the DCE bit */
495 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
503 /*------------------------------------------------------------------------------*/
506 * void relocate_code (addr_sp, gd, addr_moni)
508 * This "function" does not return, instead it continues in RAM
509 * after relocating the monitor code.
513 * r5 = length in bytes
518 mr r1, r3 /* Set new stack pointer */
519 mr r9, r4 /* Save copy of Global Data pointer */
520 mr r10, r5 /* Save copy of Destination Address */
523 mr r3, r5 /* Destination Address */
524 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
525 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
526 lwz r5, GOT(__init_end)
528 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
533 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
539 /* First our own GOT */
541 /* then the one used by the C code */
551 beq cr1,4f /* In place copy is not necessary */
552 beq 7f /* Protect against 0 count */
571 * Now flush the cache: note that we must start from a cache aligned
572 * address. Otherwise we might miss one cache line.
576 beq 7f /* Always flush prefetch queue in any case */
579 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
580 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
588 sync /* Wait for all dcbst to complete on bus */
589 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
590 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
598 7: sync /* Wait for all icbi to complete on bus */
602 * We are done. Do not return, instead branch to second part of board
603 * initialization, now running from RAM.
606 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
613 * Relocation Function, r12 point to got2+0x8000
615 * Adjust got2 pointers, no need to check for 0, this code
616 * already puts a few entries in the table.
618 li r0,__got2_entries@sectoff@l
619 la r3,GOT(_GOT2_TABLE_)
620 lwz r11,GOT(_GOT2_TABLE_)
632 * Now adjust the fixups and the pointers to the fixups
633 * in case we need to move ourselves again.
635 li r0,__fixup_entries@sectoff@l
636 lwz r3,GOT(_FIXUP_TABLE_)
650 * Now clear BSS segment
652 lwz r3,GOT(__bss_start)
666 mr r3, r9 /* Global Data pointer */
667 mr r4, r10 /* Destination Address */
671 * Copy exception vector code to low memory
674 * r7: source address, r8: end address, r9: target address
678 mflr r4 /* save link register */
681 lwz r8, GOT(_end_of_vectors)
683 li r9, 0x100 /* reset vector always at 0x100 */
686 bgelr /* return if r7>=r8 - just in case */
696 * relocate `hdlr' and `int_return' entries
698 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
699 li r8, Alignment - _start + EXC_OFF_SYS_RESET
702 addi r7, r7, 0x100 /* next exception vector */
706 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
709 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
712 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
713 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
716 addi r7, r7, 0x100 /* next exception vector */
720 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
721 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
724 addi r7, r7, 0x100 /* next exception vector */
728 mfmsr r3 /* now that the vectors have */
729 lis r7, MSR_IP@h /* relocated into low memory */
730 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
731 andc r3, r3, r7 /* (if it was on) */
732 SYNC /* Some chip revs need this... */
736 mtlr r4 /* restore link register */