3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 DECLARE_GLOBAL_DATA_PTR;
28 #ifdef CONFIG_HARD_I2C
33 #if (CONFIG_SYS_I2C_MODULE == 2)
34 #define I2C_BASE MPC5XXX_I2C2
35 #elif (CONFIG_SYS_I2C_MODULE == 1)
36 #define I2C_BASE MPC5XXX_I2C1
38 #error CONFIG_SYS_I2C_MODULE is not properly configured
41 #define I2C_TIMEOUT 6667
44 struct mpc5xxx_i2c_tap {
49 static int mpc_reg_in (volatile u32 *reg);
50 static void mpc_reg_out (volatile u32 *reg, int val, int mask);
51 static int wait_for_bb (void);
52 static int wait_for_pin (int *status);
53 static int do_address (uchar chip, char rdwr_flag);
54 static int send_bytes (uchar chip, char *buf, int len);
55 static int receive_bytes (uchar chip, char *buf, int len);
56 static int mpc_get_fdr (int);
58 static int mpc_reg_in(volatile u32 *reg)
61 __asm__ __volatile__ ("eieio");
65 static void mpc_reg_out(volatile u32 *reg, int val, int mask)
72 tmp = mpc_reg_in(reg);
73 *reg = ((tmp & ~mask) | (val & mask)) << 24;
75 __asm__ __volatile__ ("eieio");
80 static int wait_for_bb(void)
82 struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
83 int timeout = I2C_TIMEOUT;
86 status = mpc_reg_in(®s->msr);
88 while (timeout-- && (status & I2C_BB)) {
91 mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
92 temp = mpc_reg_in(®s->mdr);
93 mpc_reg_out(®s->mcr, 0, I2C_STA);
94 mpc_reg_out(®s->mcr, 0, 0);
95 mpc_reg_out(®s->mcr, I2C_EN, 0);
98 status = mpc_reg_in(®s->msr);
101 return (status & I2C_BB);
104 static int wait_for_pin(int *status)
106 struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
107 int timeout = I2C_TIMEOUT;
109 *status = mpc_reg_in(®s->msr);
111 while (timeout-- && !(*status & I2C_IF)) {
113 *status = mpc_reg_in(®s->msr);
116 if (!(*status & I2C_IF)) {
120 mpc_reg_out(®s->msr, 0, I2C_IF);
125 static int do_address(uchar chip, char rdwr_flag)
127 struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
136 mpc_reg_out(®s->mcr, I2C_TX, I2C_TX);
137 mpc_reg_out(®s->mdr, chip, 0);
139 if (wait_for_pin(&status)) {
143 if (status & I2C_RXAK) {
150 static int send_bytes(uchar chip, char *buf, int len)
152 struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
156 for (wrcount = 0; wrcount < len; ++wrcount) {
158 mpc_reg_out(®s->mdr, buf[wrcount], 0);
160 if (wait_for_pin(&status)) {
164 if (status & I2C_RXAK) {
170 return !(wrcount == len);
173 static int receive_bytes(uchar chip, char *buf, int len)
175 struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
181 mpc_reg_out(®s->mcr, 0, I2C_TX);
183 for (i = 0; i < len; ++i) {
184 buf[rdcount] = mpc_reg_in(®s->mdr);
193 if (wait_for_pin(&status)) {
198 mpc_reg_out(®s->mcr, I2C_TXAK, I2C_TXAK);
199 buf[rdcount++] = mpc_reg_in(®s->mdr);
201 if (wait_for_pin(&status)) {
205 mpc_reg_out(®s->mcr, 0, I2C_TXAK);
210 #if defined(CONFIG_SYS_I2C_INIT_MPC5XXX)
212 #define FDR510(x) (u8) (((x & 0x20) >> 3) | (x & 0x3))
213 #define FDR432(x) (u8) ((x & 0x1C) >> 2)
215 * Reset any i2c devices that may have been interrupted during a system reset.
216 * Normally this would be accomplished by clocking the line until SCL and SDA
217 * are released and then sending a start condtiion (From an Atmel datasheet).
218 * There is no direct access to the i2c pins so instead create start commands
219 * through the i2c interface. Send a start command then delay for the SDA Hold
220 * time, repeat this by disabling/enabling the bus a total of 9 times.
222 static void send_reset(void)
224 struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
228 int SDA_Tap[] = { 3, 3, 4, 4, 1, 1, 2, 2};
229 struct mpc5xxx_i2c_tap scltap[] = {
240 fdr = (u8)mpc_reg_in(®s->mfdr);
242 delay = scltap[FDR432(fdr)].scl2tap + ((SDA_Tap[FDR510(fdr)] - 1) * \
243 scltap[FDR432(fdr)].tap2tap) + 3;
245 for (i = 0; i < 9; i++) {
246 mpc_reg_out(®s->mcr, I2C_EN|I2C_STA|I2C_TX, I2C_INIT_MASK);
248 mpc_reg_out(®s->mcr, 0, I2C_INIT_MASK);
252 mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK);
254 #endif /* CONFIG_SYS_I2c_INIT_MPC5XXX */
256 /**************** I2C API ****************/
258 void i2c_init(int speed, int saddr)
260 struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
262 mpc_reg_out(®s->mcr, 0, 0);
263 mpc_reg_out(®s->madr, saddr << 1, 0);
267 mpc_reg_out(®s->mfdr, mpc_get_fdr(speed), 0);
271 mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK);
272 mpc_reg_out(®s->msr, 0, I2C_IF);
274 #if defined(CONFIG_SYS_I2C_INIT_MPC5XXX)
280 static int mpc_get_fdr(int speed)
285 ulong best_speed = 0;
288 ulong bestmatch = 0xffffffffUL;
289 int best_i = 0, best_j = 0, i, j;
290 int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8};
291 struct mpc5xxx_i2c_tap scltap[] = {
303 for (i = 7; i >= 0; i--) {
304 for (j = 7; j >= 0; j--) {
305 scl = 2 * (scltap[j].scl2tap +
306 (SCL_Tap[i] - 1) * scltap[j].tap2tap + 2);
307 if (ipb <= speed*scl) {
308 if ((speed*scl - ipb) < bestmatch) {
309 bestmatch = speed*scl - ipb;
312 best_speed = ipb/scl;
317 divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2);
318 if (gd->flags & GD_FLG_RELOC) {
321 if (gd->have_console)
322 printf("%ld kHz, ", best_speed / 1000);
330 int i2c_probe(uchar chip)
332 struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
335 for (i = 0; i < I2C_RETRIES; i++) {
336 mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
338 if (! do_address(chip, 0)) {
339 mpc_reg_out(®s->mcr, 0, I2C_STA);
344 mpc_reg_out(®s->mcr, 0, I2C_STA);
348 return (i == I2C_RETRIES);
351 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
354 struct mpc5xxx_i2c * regs = (struct mpc5xxx_i2c *)I2C_BASE;
357 xaddr[0] = (addr >> 24) & 0xFF;
358 xaddr[1] = (addr >> 16) & 0xFF;
359 xaddr[2] = (addr >> 8) & 0xFF;
360 xaddr[3] = addr & 0xFF;
363 if (gd->have_console)
364 printf("i2c_read: bus is busy\n");
368 mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
369 if (do_address(chip, 0)) {
370 if (gd->have_console)
371 printf("i2c_read: failed to address chip\n");
375 if (send_bytes(chip, &xaddr[4-alen], alen)) {
376 if (gd->have_console)
377 printf("i2c_read: send_bytes failed\n");
381 mpc_reg_out(®s->mcr, I2C_RSTA, I2C_RSTA);
382 if (do_address(chip, 1)) {
383 if (gd->have_console)
384 printf("i2c_read: failed to address chip\n");
388 if (receive_bytes(chip, (char *)buf, len)) {
389 if (gd->have_console)
390 printf("i2c_read: receive_bytes failed\n");
396 mpc_reg_out(®s->mcr, 0, I2C_STA);
400 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
403 struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
406 xaddr[0] = (addr >> 24) & 0xFF;
407 xaddr[1] = (addr >> 16) & 0xFF;
408 xaddr[2] = (addr >> 8) & 0xFF;
409 xaddr[3] = addr & 0xFF;
412 if (gd->have_console)
413 printf("i2c_write: bus is busy\n");
417 mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
418 if (do_address(chip, 0)) {
419 if (gd->have_console)
420 printf("i2c_write: failed to address chip\n");
424 if (send_bytes(chip, &xaddr[4-alen], alen)) {
425 if (gd->have_console)
426 printf("i2c_write: send_bytes failed\n");
430 if (send_bytes(chip, (char *)buf, len)) {
431 if (gd->have_console)
432 printf("i2c_write: send_bytes failed\n");
438 mpc_reg_out(®s->mcr, 0, I2C_STA);
442 #endif /* CONFIG_HARD_I2C */