2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001, 2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch.
7 * SPDX-License-Identifier: GPL-2.0+
13 * Discription: startup code
17 #include <asm-offsets.h>
22 #define CONFIG_5xx 1 /* needed for Linux kernel header files */
24 #include <ppc_asm.tmpl>
27 #include <asm/processor.h>
28 #include <asm/u-boot.h>
30 /* We don't have a MMU.
33 #define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
36 * Set up GOT: Global Offset Table
38 * Use r12 to access the GOT
41 GOT_ENTRY(_GOT2_TABLE_)
42 GOT_ENTRY(_FIXUP_TABLE_)
45 GOT_ENTRY(_start_of_vectors)
46 GOT_ENTRY(_end_of_vectors)
47 GOT_ENTRY(transfer_to_handler)
51 GOT_ENTRY(__bss_start)
55 * r3 - 1st arg to board_init(): IMMP pointer
56 * r4 - 2nd arg to board_init(): boot flag
59 .long 0x27051956 /* U-Boot Magic Number */
62 .ascii U_BOOT_VERSION_STRING, "\0"
68 li r4, CONFIG_SYS_ISB /* Set ISB bit */
72 /* Initialize machine status; enable machine check interrupt */
73 /*----------------------------------------------------------------------*/
74 li r3, MSR_KERNEL /* Set ME, RI flags */
76 mtspr SRR1, r3 /* Make SRR1 match MSR */
78 /* Initialize debug port registers */
79 /*----------------------------------------------------------------------*/
80 xor r0, r0, r0 /* Clear R0 */
81 mtspr LCTRL1, r0 /* Initialize debug port regs */
86 #if defined(CONFIG_PATI)
87 /* the external flash access on PATI fails if programming the PLL to 40MHz.
88 * Copy the PLL programming code to the internal RAM and execute it
89 *----------------------------------------------------------------------*/
90 lis r3, CONFIG_SYS_MONITOR_BASE@h
91 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
92 addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET
94 lis r4, CONFIG_SYS_INIT_RAM_ADDR@h
95 ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
98 ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2)
105 bdnz 0b /* copy loop */
110 * Calculate absolute address in FLASH and jump there
111 *----------------------------------------------------------------------*/
113 lis r3, CONFIG_SYS_MONITOR_BASE@h
114 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
115 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
121 /* Initialize some SPRs that are hard to access from C */
122 /*----------------------------------------------------------------------*/
124 lis r3, CONFIG_SYS_IMMR@h /* Pass IMMR as arg1 to C routine */
125 lis r2, CONFIG_SYS_INIT_SP_ADDR@h
126 ori r1, r2, CONFIG_SYS_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
127 /* Note: R0 is still 0 here */
128 stwu r0, -4(r1) /* Clear final stack frame so that */
129 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
132 * Disable serialized ifetch and show cycles
133 * (i.e. set processor to normal mode) for maximum
140 /* Set up debug mode entry */
142 lis r2, CONFIG_SYS_DER@h
143 ori r2, r2, CONFIG_SYS_DER@l
146 /* Let the C-code set up the rest */
148 /* Be careful to keep code relocatable ! */
149 /*----------------------------------------------------------------------*/
151 GET_GOT /* initialize GOT access */
154 bl cpu_init_f /* run low-level CPU init code (from Flash) */
156 bl board_init_f /* run 1st part of board init code (from Flash) */
158 /* NOTREACHED - board_init_f() does not return */
161 .globl _start_of_vectors
165 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
167 /* Data Storage exception. "Never" generated on the 860. */
168 STD_EXCEPTION(0x300, DataStorage, UnknownException)
170 /* Instruction Storage exception. "Never" generated on the 860. */
171 STD_EXCEPTION(0x400, InstStorage, UnknownException)
173 /* External Interrupt exception. */
174 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
176 /* Alignment exception. */
179 EXCEPTION_PROLOG(SRR0, SRR1)
184 addi r3,r1,STACK_FRAME_OVERHEAD
185 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
187 /* Program check exception */
190 EXCEPTION_PROLOG(SRR0, SRR1)
191 addi r3,r1,STACK_FRAME_OVERHEAD
192 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
195 /* FPU on MPC5xx available. We will use it later.
197 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
199 /* I guess we could implement decrementer, and may have
200 * to someday for timekeeping.
202 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
203 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
204 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
205 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
206 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
208 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
209 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
211 /* On the MPC8xx, this is a software emulation interrupt. It occurs
212 * for all unimplemented and illegal instructions.
214 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
215 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
216 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
217 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
218 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
220 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
221 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
222 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
223 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
224 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
225 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
226 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
228 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
229 STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
230 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
231 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
234 .globl _end_of_vectors
241 * This code finishes saving the registers to the exception frame
242 * and jumps to the appropriate handler for the exception.
243 * Register r21 is pointer into trap frame, r1 has new stack pointer.
245 .globl transfer_to_handler
256 andi. r24,r23,0x3f00 /* get vector offset */
260 mtspr SPRG2,r22 /* r1 is now kernel sp */
261 lwz r24,0(r23) /* virtual address of handler */
262 lwz r23,4(r23) /* where to go when done */
267 rfi /* jump to handler, enable MMU */
270 mfmsr r28 /* Disable interrupts */
274 SYNC /* Some chip revs need this... */
289 lwz r2,_NIP(r1) /* Restore environment */
301 * unsigned int get_immr (unsigned int mask)
303 * return (mask ? (IMMR & mask) : IMMR);
307 mr r4,r3 /* save mask */
308 mfspr r3, IMMR /* IMMR */
309 cmpwi 0,r4,0 /* mask != 0 ? */
311 and r3,r3,r4 /* IMMR & mask */
321 /*------------------------------------------------------------------------------*/
324 * void relocate_code (addr_sp, gd, addr_moni)
326 * This "function" does not return, instead it continues in RAM
327 * after relocating the monitor code.
331 * r5 = length in bytes
336 mr r1, r3 /* Set new stack pointer in SRAM */
337 mr r9, r4 /* Save copy of global data pointer in SRAM */
338 mr r10, r5 /* Save copy of monitor destination Address in SRAM */
341 mr r3, r5 /* Destination Address */
342 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
343 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
344 lwz r5, GOT(__init_end)
350 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
356 /* First our own GOT */
358 /* the the one used by the C code */
368 beq cr1,4f /* In place copy is not necessary */
369 beq 4f /* Protect against 0 count */
391 * We are done. Do not return, instead branch to second part of board
392 * initialization, now running from RAM.
395 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
402 * Relocation Function, r12 point to got2+0x8000
404 * Adjust got2 pointers, no need to check for 0, this code
405 * already puts a few entries in the table.
407 li r0,__got2_entries@sectoff@l
408 la r3,GOT(_GOT2_TABLE_)
409 lwz r11,GOT(_GOT2_TABLE_)
421 * Now adjust the fixups and the pointers to the fixups
422 * in case we need to move ourselves again.
424 li r0,__fixup_entries@sectoff@l
425 lwz r3,GOT(_FIXUP_TABLE_)
441 * Now clear BSS segment
443 lwz r3,GOT(__bss_start)
444 lwz r4,GOT(__bss_end)
456 mr r3, r9 /* Global Data pointer */
457 mr r4, r10 /* Destination Address */
461 * Copy exception vector code to low memory
464 * r7: source address, r8: end address, r9: target address
468 mflr r4 /* save link register */
471 lwz r8, GOT(_end_of_vectors)
473 li r9, 0x100 /* reset vector always at 0x100 */
476 bgelr /* return if r7>=r8 - just in case */
486 * relocate `hdlr' and `int_return' entries
488 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
489 li r8, Alignment - _start + EXC_OFF_SYS_RESET
492 addi r7, r7, 0x100 /* next exception vector */
496 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
499 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
502 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
503 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
506 addi r7, r7, 0x100 /* next exception vector */
510 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
511 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
514 addi r7, r7, 0x100 /* next exception vector */
518 mtlr r4 /* restore link register */
521 #if defined(CONFIG_PATI)
522 /* Program the PLL */
524 lis r4, (CONFIG_SYS_IMMR + 0x002fc384)@h
525 ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc384)@l
526 lis r3, (0x55ccaa33)@h
527 ori r3, r3, (0x55ccaa33)@l
529 lis r4, (CONFIG_SYS_IMMR + 0x002fc284)@h
530 ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc284)@l
531 lis r3, CONFIG_SYS_PLPRCR@h
532 ori r3, r3, CONFIG_SYS_PLPRCR@l
538 bdnz ..spinlp /* spin loop */