2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Based on the MPC83xx code.
29 * U-Boot - Startup Code for MPC512x based Embedded Boards
33 #include <timestamp.h>
36 #define CONFIG_521X 1 /* needed for Linux kernel header files*/
38 #include <asm/immap_512x.h>
39 #include "asm-offsets.h"
41 #include <ppc_asm.tmpl>
44 #include <asm/cache.h>
46 #include <asm/u-boot.h>
48 #ifndef CONFIG_IDENT_STRING
49 #define CONFIG_IDENT_STRING "MPC512X"
53 * Floating Point enable, Machine Check and Recoverable Interr.
57 #define MSR_KERNEL (MSR_FP|MSR_RI)
59 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
62 /* Macros for manipulating CSx_START/STOP */
63 #define START_REG(start) ((start) >> 16)
64 #define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
67 * Set up GOT: Global Offset Table
69 * Use r12 to access the GOT
72 GOT_ENTRY(_GOT2_TABLE_)
73 GOT_ENTRY(_FIXUP_TABLE_)
76 GOT_ENTRY(_start_of_vectors)
77 GOT_ENTRY(_end_of_vectors)
78 GOT_ENTRY(transfer_to_handler)
82 GOT_ENTRY(__bss_start)
86 * Magic number and version string
88 .long 0x27051956 /* U-Boot Magic Number */
92 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
93 .ascii " ", CONFIG_IDENT_STRING, "\0"
102 /* Start from here after reset/power on */
106 .globl _start_of_vectors
110 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
112 /* Data Storage exception. */
113 STD_EXCEPTION(0x300, DataStorage, UnknownException)
115 /* Instruction Storage exception. */
116 STD_EXCEPTION(0x400, InstStorage, UnknownException)
118 /* External Interrupt exception. */
119 STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
121 /* Alignment exception. */
124 EXCEPTION_PROLOG(SRR0, SRR1)
129 addi r3,r1,STACK_FRAME_OVERHEAD
130 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
132 /* Program check exception */
135 EXCEPTION_PROLOG(SRR0, SRR1)
136 addi r3,r1,STACK_FRAME_OVERHEAD
137 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
140 /* Floating Point Unit unavailable exception */
141 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
144 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
146 /* Critical interrupt */
147 STD_EXCEPTION(0xa00, Critical, UnknownException)
150 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
152 /* Trace interrupt */
153 STD_EXCEPTION(0xd00, Trace, UnknownException)
155 /* Performance Monitor interrupt */
156 STD_EXCEPTION(0xf00, PerfMon, UnknownException)
158 /* Intruction Translation Miss */
159 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
161 /* Data Load Translation Miss */
162 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
164 /* Data Store Translation Miss */
165 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
167 /* Instruction Address Breakpoint */
168 STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
170 /* System Management interrupt */
171 STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
173 .globl _end_of_vectors
178 /* Save msr contents */
181 /* Set IMMR area to our preferred location */
182 lis r4, CONFIG_DEFAULT_IMMR@h
183 lis r3, CONFIG_SYS_IMMR@h
184 ori r3, r3, CONFIG_SYS_IMMR@l
186 mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
188 /* Initialise the machine */
192 * Set up Local Access Windows:
194 * 1) Boot/CS0 (boot FLASH)
195 * 2) On-chip SRAM (initial stack purposes)
198 /* Boot CS/CS0 window range */
199 lis r3, CONFIG_SYS_IMMR@h
200 ori r3, r3, CONFIG_SYS_IMMR@l
202 lis r4, START_REG(CONFIG_SYS_FLASH_BASE)
203 ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
207 * The SRAM window has a fixed size (256K), so only the start address
210 lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
214 * According to MPC5121e RM, configuring local access windows should
215 * be followed by a dummy read of the config register that was
216 * modified last and an isync
222 * Set configuration of the Boot/CS0, the SRAM window does not have a
223 * config register so no params can be set for it
225 lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
226 ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
228 lis r4, CONFIG_SYS_CS0_CFG@h
229 ori r4, r4, CONFIG_SYS_CS0_CFG@l
230 stw r4, CS0_CONFIG(r3)
232 /* Master enable all CS's */
234 ori r4, r4, CS_CTRL_ME@l
237 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
238 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
239 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
244 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
245 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
247 li r0, 0 /* Make room for stack frame header and */
248 stwu r0, -4(r1) /* clear final stack frame so that */
249 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
251 /* let the C-code set up the rest */
253 /* Be careful to keep code relocatable & stack humble */
254 /*------------------------------------------------------*/
256 GET_GOT /* initialize GOT access */
259 lis r3, CONFIG_SYS_IMMR@h
260 /* run low-level CPU init code (in Flash) */
263 /* run 1st part of board init code (in Flash) */
266 /* NOTREACHED - board_init_f() does not return */
269 * This code finishes saving the registers to the exception frame
270 * and jumps to the appropriate handler for the exception.
271 * Register r21 is pointer into trap frame, r1 has new stack pointer.
273 .globl transfer_to_handler
284 andi. r24,r23,0x3f00 /* get vector offset */
288 lwz r24,0(r23) /* virtual address of handler */
289 lwz r23,4(r23) /* where to go when done */
294 rfi /* jump to handler, enable MMU */
297 mfmsr r28 /* Disable interrupts */
301 SYNC /* Some chip revs need this... */
316 lwz r2,_NIP(r1) /* Restore environment */
327 * This code initialises the machine, it expects original MSR contents to be in r5.
330 /* Initialize machine status; enable machine check interrupt */
331 /*-----------------------------------------------------------*/
333 li r3, MSR_KERNEL /* Set ME and RI flags */
334 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
336 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
340 mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
342 lis r3, CONFIG_SYS_IMMR@h
344 #if defined(CONFIG_WATCHDOG)
345 /* Initialise the watchdog and reset it */
346 /*--------------------------------------*/
347 lis r4, CONFIG_SYS_WATCHDOG_VALUE
348 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
358 /* Disable the watchdog */
359 /*----------------------*/
362 * Check to see if it's enabled for disabling: once disabled by s/w
363 * it's not possible to re-enable it
370 #endif /* CONFIG_WATCHDOG */
372 /* Initialize the Hardware Implementation-dependent Registers */
373 /* HID0 also contains cache control */
374 /*------------------------------------------------------*/
375 lis r3, CONFIG_SYS_HID0_INIT@h
376 ori r3, r3, CONFIG_SYS_HID0_INIT@l
380 lis r3, CONFIG_SYS_HID0_FINAL@h
381 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
385 lis r3, CONFIG_SYS_HID2@h
386 ori r3, r3, CONFIG_SYS_HID2@l
395 * Note: requires that all cache bits in
396 * HID0 are in the low half word.
403 ori r4, r4, HID0_ILOCK
405 ori r4, r3, HID0_ICFI
407 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
409 mtspr HID0, r3 /* clears invalidate */
412 .globl icache_disable
416 ori r4, r4, HID0_ICE|HID0_ILOCK
418 ori r4, r3, HID0_ICFI
420 mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
422 mtspr HID0, r3 /* clears invalidate */
428 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
434 li r5, HID0_DCFI|HID0_DLOCK
436 mtspr HID0, r3 /* no invalidate, unlock */
438 ori r5, r3, HID0_DCFI
439 mtspr HID0, r5 /* enable + invalidate */
440 mtspr HID0, r3 /* enable */
444 .globl dcache_disable
448 ori r4, r4, HID0_DCE|HID0_DLOCK
452 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
454 mtspr HID0, r3 /* clears invalidate */
460 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
468 /*-------------------------------------------------------------------*/
471 * void relocate_code (addr_sp, gd, addr_moni)
473 * This "function" does not return, instead it continues in RAM
474 * after relocating the monitor code.
478 * r5 = length in bytes
483 mr r1, r3 /* Set new stack pointer */
484 mr r9, r4 /* Save copy of Global Data pointer */
485 mr r10, r5 /* Save copy of Destination Address */
488 mr r3, r5 /* Destination Address */
489 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
490 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
491 lwz r5, GOT(__init_end)
493 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
498 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
499 * + Destination Address
505 /* First our own GOT */
507 /* then the one used by the C code */
516 beq cr1,4f /* In place copy is not necessary */
517 beq 7f /* Protect against 0 count */
546 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
554 * Now flush the cache: note that we must start from a cache aligned
555 * address. Otherwise we might miss one cache line.
559 beq 7f /* Always flush prefetch queue in any case */
567 sync /* Wait for all dcbst to complete on bus */
573 7: sync /* Wait for all icbi to complete on bus */
577 * We are done. Do not return, instead branch to second part of board
578 * initialization, now running from RAM.
580 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
586 * Relocation Function, r12 point to got2+0x8000
588 * Adjust got2 pointers, no need to check for 0, this code
589 * already puts a few entries in the table.
591 li r0,__got2_entries@sectoff@l
592 la r3,GOT(_GOT2_TABLE_)
593 lwz r11,GOT(_GOT2_TABLE_)
605 * Now adjust the fixups and the pointers to the fixups
606 * in case we need to move ourselves again.
608 li r0,__fixup_entries@sectoff@l
609 lwz r3,GOT(_FIXUP_TABLE_)
625 * Now clear BSS segment
627 lwz r3,GOT(__bss_start)
640 mr r3, r9 /* Global Data pointer */
641 mr r4, r10 /* Destination Address */
645 * Copy exception vector code to low memory
648 * r7: source address, r8: end address, r9: target address
652 mflr r4 /* save link register */
655 lwz r8, GOT(_end_of_vectors)
657 li r9, 0x100 /* reset vector at 0x100 */
660 bgelr /* return if r7>=r8 - just in case */
670 * relocate `hdlr' and `int_return' entries
672 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
673 li r8, Alignment - _start + EXC_OFF_SYS_RESET
676 addi r7, r7, 0x100 /* next exception vector */
680 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
683 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
686 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
687 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
690 addi r7, r7, 0x100 /* next exception vector */
694 li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
695 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
698 addi r7, r7, 0x100 /* next exception vector */
702 mfmsr r3 /* now that the vectors have */
703 lis r7, MSR_IP@h /* relocated into low memory */
704 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
705 andc r3, r3, r7 /* (if it was on) */
706 SYNC /* Some chip revs need this... */
710 mtlr r4 /* restore link register */