2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Based on the MPC83xx code.
29 * U-Boot - Startup Code for MPC512x based Embedded Boards
32 #include <asm-offsets.h>
34 #include <timestamp.h>
37 #define CONFIG_521X 1 /* needed for Linux kernel header files*/
39 #include <asm/immap_512x.h>
40 #include "asm-offsets.h"
42 #include <ppc_asm.tmpl>
45 #include <asm/cache.h>
47 #include <asm/u-boot.h>
49 #ifndef CONFIG_IDENT_STRING
50 #define CONFIG_IDENT_STRING "MPC512X"
54 * Floating Point enable, Machine Check and Recoverable Interr.
58 #define MSR_KERNEL (MSR_FP|MSR_RI)
60 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
63 /* Macros for manipulating CSx_START/STOP */
64 #define START_REG(start) ((start) >> 16)
65 #define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
68 * Set up GOT: Global Offset Table
70 * Use r12 to access the GOT
73 GOT_ENTRY(_GOT2_TABLE_)
74 GOT_ENTRY(_FIXUP_TABLE_)
77 GOT_ENTRY(_start_of_vectors)
78 GOT_ENTRY(_end_of_vectors)
79 GOT_ENTRY(transfer_to_handler)
82 GOT_ENTRY(__bss_end__)
83 GOT_ENTRY(__bss_start)
87 * Magic number and version string
89 .long 0x27051956 /* U-Boot Magic Number */
93 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
94 .ascii " ", CONFIG_IDENT_STRING, "\0"
100 . = EXC_OFF_SYS_RESET
103 /* Start from here after reset/power on */
107 .globl _start_of_vectors
111 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
113 /* Data Storage exception. */
114 STD_EXCEPTION(0x300, DataStorage, UnknownException)
116 /* Instruction Storage exception. */
117 STD_EXCEPTION(0x400, InstStorage, UnknownException)
119 /* External Interrupt exception. */
120 STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
122 /* Alignment exception. */
125 EXCEPTION_PROLOG(SRR0, SRR1)
130 addi r3,r1,STACK_FRAME_OVERHEAD
131 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
133 /* Program check exception */
136 EXCEPTION_PROLOG(SRR0, SRR1)
137 addi r3,r1,STACK_FRAME_OVERHEAD
138 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
141 /* Floating Point Unit unavailable exception */
142 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
145 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
147 /* Critical interrupt */
148 STD_EXCEPTION(0xa00, Critical, UnknownException)
151 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
153 /* Trace interrupt */
154 STD_EXCEPTION(0xd00, Trace, UnknownException)
156 /* Performance Monitor interrupt */
157 STD_EXCEPTION(0xf00, PerfMon, UnknownException)
159 /* Intruction Translation Miss */
160 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
162 /* Data Load Translation Miss */
163 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
165 /* Data Store Translation Miss */
166 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
168 /* Instruction Address Breakpoint */
169 STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
171 /* System Management interrupt */
172 STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
174 .globl _end_of_vectors
179 /* Save msr contents */
182 /* Set IMMR area to our preferred location */
183 lis r4, CONFIG_DEFAULT_IMMR@h
184 lis r3, CONFIG_SYS_IMMR@h
185 ori r3, r3, CONFIG_SYS_IMMR@l
187 mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
189 /* Initialise the machine */
193 * Set up Local Access Windows:
195 * 1) Boot/CS0 (boot FLASH)
196 * 2) On-chip SRAM (initial stack purposes)
199 /* Boot CS/CS0 window range */
200 lis r3, CONFIG_SYS_IMMR@h
201 ori r3, r3, CONFIG_SYS_IMMR@l
203 lis r4, START_REG(CONFIG_SYS_FLASH_BASE)
204 ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
208 * The SRAM window has a fixed size (256K), so only the start address
211 lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
215 * According to MPC5121e RM, configuring local access windows should
216 * be followed by a dummy read of the config register that was
217 * modified last and an isync
223 * Set configuration of the Boot/CS0, the SRAM window does not have a
224 * config register so no params can be set for it
226 lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
227 ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
229 lis r4, CONFIG_SYS_CS0_CFG@h
230 ori r4, r4, CONFIG_SYS_CS0_CFG@l
231 stw r4, CS0_CONFIG(r3)
233 /* Master enable all CS's */
235 ori r4, r4, CS_CTRL_ME@l
238 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
239 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
240 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
245 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
246 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
248 li r0, 0 /* Make room for stack frame header and */
249 stwu r0, -4(r1) /* clear final stack frame so that */
250 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
252 /* let the C-code set up the rest */
254 /* Be careful to keep code relocatable & stack humble */
255 /*------------------------------------------------------*/
257 GET_GOT /* initialize GOT access */
260 lis r3, CONFIG_SYS_IMMR@h
261 /* run low-level CPU init code (in Flash) */
264 /* run 1st part of board init code (in Flash) */
267 /* NOTREACHED - board_init_f() does not return */
270 * This code finishes saving the registers to the exception frame
271 * and jumps to the appropriate handler for the exception.
272 * Register r21 is pointer into trap frame, r1 has new stack pointer.
274 .globl transfer_to_handler
285 andi. r24,r23,0x3f00 /* get vector offset */
289 lwz r24,0(r23) /* virtual address of handler */
290 lwz r23,4(r23) /* where to go when done */
295 rfi /* jump to handler, enable MMU */
298 mfmsr r28 /* Disable interrupts */
302 SYNC /* Some chip revs need this... */
317 lwz r2,_NIP(r1) /* Restore environment */
328 * This code initialises the machine, it expects original MSR contents to be in r5.
331 /* Initialize machine status; enable machine check interrupt */
332 /*-----------------------------------------------------------*/
334 li r3, MSR_KERNEL /* Set ME and RI flags */
335 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
337 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
341 mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
343 lis r3, CONFIG_SYS_IMMR@h
345 #if defined(CONFIG_WATCHDOG)
346 /* Initialise the watchdog and reset it */
347 /*--------------------------------------*/
348 lis r4, CONFIG_SYS_WATCHDOG_VALUE
349 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
359 /* Disable the watchdog */
360 /*----------------------*/
363 * Check to see if it's enabled for disabling: once disabled by s/w
364 * it's not possible to re-enable it
371 #endif /* CONFIG_WATCHDOG */
373 /* Initialize the Hardware Implementation-dependent Registers */
374 /* HID0 also contains cache control */
375 /*------------------------------------------------------*/
376 lis r3, CONFIG_SYS_HID0_INIT@h
377 ori r3, r3, CONFIG_SYS_HID0_INIT@l
381 lis r3, CONFIG_SYS_HID0_FINAL@h
382 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
386 lis r3, CONFIG_SYS_HID2@h
387 ori r3, r3, CONFIG_SYS_HID2@l
396 * Note: requires that all cache bits in
397 * HID0 are in the low half word.
404 ori r4, r4, HID0_ILOCK
406 ori r4, r3, HID0_ICFI
408 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
410 mtspr HID0, r3 /* clears invalidate */
413 .globl icache_disable
417 ori r4, r4, HID0_ICE|HID0_ILOCK
419 ori r4, r3, HID0_ICFI
421 mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
423 mtspr HID0, r3 /* clears invalidate */
429 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
435 li r5, HID0_DCFI|HID0_DLOCK
437 mtspr HID0, r3 /* no invalidate, unlock */
439 ori r5, r3, HID0_DCFI
440 mtspr HID0, r5 /* enable + invalidate */
441 mtspr HID0, r3 /* enable */
445 .globl dcache_disable
449 ori r4, r4, HID0_DCE|HID0_DLOCK
453 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
455 mtspr HID0, r3 /* clears invalidate */
461 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
469 /*-------------------------------------------------------------------*/
472 * void relocate_code (addr_sp, gd, addr_moni)
474 * This "function" does not return, instead it continues in RAM
475 * after relocating the monitor code.
479 * r5 = length in bytes
484 mr r1, r3 /* Set new stack pointer */
485 mr r9, r4 /* Save copy of Global Data pointer */
486 mr r10, r5 /* Save copy of Destination Address */
489 mr r3, r5 /* Destination Address */
490 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
491 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
492 lwz r5, GOT(__init_end)
494 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
499 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
500 * + Destination Address
506 /* First our own GOT */
508 /* then the one used by the C code */
517 beq cr1,4f /* In place copy is not necessary */
518 beq 7f /* Protect against 0 count */
547 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
555 * Now flush the cache: note that we must start from a cache aligned
556 * address. Otherwise we might miss one cache line.
560 beq 7f /* Always flush prefetch queue in any case */
568 sync /* Wait for all dcbst to complete on bus */
574 7: sync /* Wait for all icbi to complete on bus */
578 * We are done. Do not return, instead branch to second part of board
579 * initialization, now running from RAM.
581 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
587 * Relocation Function, r12 point to got2+0x8000
589 * Adjust got2 pointers, no need to check for 0, this code
590 * already puts a few entries in the table.
592 li r0,__got2_entries@sectoff@l
593 la r3,GOT(_GOT2_TABLE_)
594 lwz r11,GOT(_GOT2_TABLE_)
606 * Now adjust the fixups and the pointers to the fixups
607 * in case we need to move ourselves again.
609 li r0,__fixup_entries@sectoff@l
610 lwz r3,GOT(_FIXUP_TABLE_)
626 * Now clear BSS segment
628 lwz r3,GOT(__bss_start)
629 lwz r4,GOT(__bss_end__)
641 mr r3, r9 /* Global Data pointer */
642 mr r4, r10 /* Destination Address */
646 * Copy exception vector code to low memory
649 * r7: source address, r8: end address, r9: target address
653 mflr r4 /* save link register */
656 lwz r8, GOT(_end_of_vectors)
658 li r9, 0x100 /* reset vector at 0x100 */
661 bgelr /* return if r7>=r8 - just in case */
671 * relocate `hdlr' and `int_return' entries
673 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
674 li r8, Alignment - _start + EXC_OFF_SYS_RESET
677 addi r7, r7, 0x100 /* next exception vector */
681 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
684 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
687 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
688 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
691 addi r7, r7, 0x100 /* next exception vector */
695 li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
696 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
699 addi r7, r7, 0x100 /* next exception vector */
703 mfmsr r3 /* now that the vectors have */
704 lis r7, MSR_IP@h /* relocated into low memory */
705 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
706 andc r3, r3, r7 /* (if it was on) */
707 SYNC /* Some chip revs need this... */
711 mtlr r4 /* restore link register */