2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Based on the MPC83xx code.
29 * U-Boot - Startup Code for MPC512x based Embedded Boards
32 #include <asm-offsets.h>
34 #ifndef CONFIG_IDENT_STRING
35 #define CONFIG_IDENT_STRING "MPC512X"
39 #define CONFIG_521X 1 /* needed for Linux kernel header files*/
41 #include <asm/immap_512x.h>
42 #include "asm-offsets.h"
44 #include <ppc_asm.tmpl>
47 #include <asm/cache.h>
49 #include <asm/u-boot.h>
52 * Floating Point enable, Machine Check and Recoverable Interr.
56 #define MSR_KERNEL (MSR_FP|MSR_RI)
58 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
61 /* Macros for manipulating CSx_START/STOP */
62 #define START_REG(start) ((start) >> 16)
63 #define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
66 * Set up GOT: Global Offset Table
68 * Use r12 to access the GOT
71 GOT_ENTRY(_GOT2_TABLE_)
72 GOT_ENTRY(_FIXUP_TABLE_)
75 GOT_ENTRY(_start_of_vectors)
76 GOT_ENTRY(_end_of_vectors)
77 GOT_ENTRY(transfer_to_handler)
81 GOT_ENTRY(__bss_start)
85 * Magic number and version string
87 .long 0x27051956 /* U-Boot Magic Number */
90 .ascii U_BOOT_VERSION_STRING, "\0"
99 /* Start from here after reset/power on */
103 .globl _start_of_vectors
107 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
109 /* Data Storage exception. */
110 STD_EXCEPTION(0x300, DataStorage, UnknownException)
112 /* Instruction Storage exception. */
113 STD_EXCEPTION(0x400, InstStorage, UnknownException)
115 /* External Interrupt exception. */
116 STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
118 /* Alignment exception. */
121 EXCEPTION_PROLOG(SRR0, SRR1)
126 addi r3,r1,STACK_FRAME_OVERHEAD
127 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
129 /* Program check exception */
132 EXCEPTION_PROLOG(SRR0, SRR1)
133 addi r3,r1,STACK_FRAME_OVERHEAD
134 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
137 /* Floating Point Unit unavailable exception */
138 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
141 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
143 /* Critical interrupt */
144 STD_EXCEPTION(0xa00, Critical, UnknownException)
147 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
149 /* Trace interrupt */
150 STD_EXCEPTION(0xd00, Trace, UnknownException)
152 /* Performance Monitor interrupt */
153 STD_EXCEPTION(0xf00, PerfMon, UnknownException)
155 /* Intruction Translation Miss */
156 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
158 /* Data Load Translation Miss */
159 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
161 /* Data Store Translation Miss */
162 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
164 /* Instruction Address Breakpoint */
165 STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
167 /* System Management interrupt */
168 STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
170 .globl _end_of_vectors
175 /* Save msr contents */
178 /* Set IMMR area to our preferred location */
179 lis r4, CONFIG_DEFAULT_IMMR@h
180 lis r3, CONFIG_SYS_IMMR@h
181 ori r3, r3, CONFIG_SYS_IMMR@l
183 mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
185 /* Initialise the machine */
189 * Set up Local Access Windows:
191 * 1) Boot/CS0 (boot FLASH)
192 * 2) On-chip SRAM (initial stack purposes)
195 /* Boot CS/CS0 window range */
196 lis r3, CONFIG_SYS_IMMR@h
197 ori r3, r3, CONFIG_SYS_IMMR@l
199 lis r4, START_REG(CONFIG_SYS_FLASH_BASE)
200 ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
204 * The SRAM window has a fixed size (256K), so only the start address
207 lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
211 * According to MPC5121e RM, configuring local access windows should
212 * be followed by a dummy read of the config register that was
213 * modified last and an isync
219 * Set configuration of the Boot/CS0, the SRAM window does not have a
220 * config register so no params can be set for it
222 lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
223 ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
225 lis r4, CONFIG_SYS_CS0_CFG@h
226 ori r4, r4, CONFIG_SYS_CS0_CFG@l
227 stw r4, CS0_CONFIG(r3)
229 /* Master enable all CS's */
231 ori r4, r4, CS_CTRL_ME@l
234 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
235 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
236 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
241 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
242 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
244 li r0, 0 /* Make room for stack frame header and */
245 stwu r0, -4(r1) /* clear final stack frame so that */
246 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
248 /* let the C-code set up the rest */
250 /* Be careful to keep code relocatable & stack humble */
251 /*------------------------------------------------------*/
253 GET_GOT /* initialize GOT access */
256 lis r3, CONFIG_SYS_IMMR@h
257 /* run low-level CPU init code (in Flash) */
260 /* run 1st part of board init code (in Flash) */
263 /* NOTREACHED - board_init_f() does not return */
266 * This code finishes saving the registers to the exception frame
267 * and jumps to the appropriate handler for the exception.
268 * Register r21 is pointer into trap frame, r1 has new stack pointer.
270 .globl transfer_to_handler
281 andi. r24,r23,0x3f00 /* get vector offset */
285 lwz r24,0(r23) /* virtual address of handler */
286 lwz r23,4(r23) /* where to go when done */
291 rfi /* jump to handler, enable MMU */
294 mfmsr r28 /* Disable interrupts */
298 SYNC /* Some chip revs need this... */
313 lwz r2,_NIP(r1) /* Restore environment */
324 * This code initialises the machine, it expects original MSR contents to be in r5.
327 /* Initialize machine status; enable machine check interrupt */
328 /*-----------------------------------------------------------*/
330 li r3, MSR_KERNEL /* Set ME and RI flags */
331 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
333 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
337 mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
339 lis r3, CONFIG_SYS_IMMR@h
341 #if defined(CONFIG_WATCHDOG)
342 /* Initialise the watchdog and reset it */
343 /*--------------------------------------*/
344 lis r4, CONFIG_SYS_WATCHDOG_VALUE
345 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
355 /* Disable the watchdog */
356 /*----------------------*/
359 * Check to see if it's enabled for disabling: once disabled by s/w
360 * it's not possible to re-enable it
367 #endif /* CONFIG_WATCHDOG */
369 /* Initialize the Hardware Implementation-dependent Registers */
370 /* HID0 also contains cache control */
371 /*------------------------------------------------------*/
372 lis r3, CONFIG_SYS_HID0_INIT@h
373 ori r3, r3, CONFIG_SYS_HID0_INIT@l
377 lis r3, CONFIG_SYS_HID0_FINAL@h
378 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
382 lis r3, CONFIG_SYS_HID2@h
383 ori r3, r3, CONFIG_SYS_HID2@l
392 * Note: requires that all cache bits in
393 * HID0 are in the low half word.
400 ori r4, r4, HID0_ILOCK
402 ori r4, r3, HID0_ICFI
404 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
406 mtspr HID0, r3 /* clears invalidate */
409 .globl icache_disable
413 ori r4, r4, HID0_ICE|HID0_ILOCK
415 ori r4, r3, HID0_ICFI
417 mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
419 mtspr HID0, r3 /* clears invalidate */
425 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
431 li r5, HID0_DCFI|HID0_DLOCK
433 mtspr HID0, r3 /* no invalidate, unlock */
435 ori r5, r3, HID0_DCFI
436 mtspr HID0, r5 /* enable + invalidate */
437 mtspr HID0, r3 /* enable */
441 .globl dcache_disable
445 ori r4, r4, HID0_DCE|HID0_DLOCK
449 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
451 mtspr HID0, r3 /* clears invalidate */
457 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
465 /*-------------------------------------------------------------------*/
468 * void relocate_code (addr_sp, gd, addr_moni)
470 * This "function" does not return, instead it continues in RAM
471 * after relocating the monitor code.
475 * r5 = length in bytes
480 mr r1, r3 /* Set new stack pointer */
481 mr r9, r4 /* Save copy of Global Data pointer */
482 mr r10, r5 /* Save copy of Destination Address */
485 mr r3, r5 /* Destination Address */
486 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
487 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
488 lwz r5, GOT(__init_end)
490 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
495 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
496 * + Destination Address
502 /* First our own GOT */
504 /* then the one used by the C code */
513 beq cr1,4f /* In place copy is not necessary */
514 beq 7f /* Protect against 0 count */
543 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
551 * Now flush the cache: note that we must start from a cache aligned
552 * address. Otherwise we might miss one cache line.
556 beq 7f /* Always flush prefetch queue in any case */
564 sync /* Wait for all dcbst to complete on bus */
570 7: sync /* Wait for all icbi to complete on bus */
574 * We are done. Do not return, instead branch to second part of board
575 * initialization, now running from RAM.
577 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
583 * Relocation Function, r12 point to got2+0x8000
585 * Adjust got2 pointers, no need to check for 0, this code
586 * already puts a few entries in the table.
588 li r0,__got2_entries@sectoff@l
589 la r3,GOT(_GOT2_TABLE_)
590 lwz r11,GOT(_GOT2_TABLE_)
602 * Now adjust the fixups and the pointers to the fixups
603 * in case we need to move ourselves again.
605 li r0,__fixup_entries@sectoff@l
606 lwz r3,GOT(_FIXUP_TABLE_)
622 * Now clear BSS segment
624 lwz r3,GOT(__bss_start)
625 lwz r4,GOT(__bss_end)
637 mr r3, r9 /* Global Data pointer */
638 mr r4, r10 /* Destination Address */
642 * Copy exception vector code to low memory
645 * r7: source address, r8: end address, r9: target address
649 mflr r4 /* save link register */
652 lwz r8, GOT(_end_of_vectors)
654 li r9, 0x100 /* reset vector at 0x100 */
657 bgelr /* return if r7>=r8 - just in case */
667 * relocate `hdlr' and `int_return' entries
669 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
670 li r8, Alignment - _start + EXC_OFF_SYS_RESET
673 addi r7, r7, 0x100 /* next exception vector */
677 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
680 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
683 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
684 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
687 addi r7, r7, 0x100 /* next exception vector */
691 li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
692 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
695 addi r7, r7, 0x100 /* next exception vector */
699 mfmsr r3 /* now that the vectors have */
700 lis r7, MSR_IP@h /* relocated into low memory */
701 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
702 andc r3, r3, r7 /* (if it was on) */
703 SYNC /* Some chip revs need this... */
707 mtlr r4 /* restore link register */