2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006.
7 * SPDX-License-Identifier: GPL-2.0+
9 * Based on the MPC83xx code.
13 * U-Boot - Startup Code for MPC512x based Embedded Boards
16 #include <asm-offsets.h>
18 #ifndef CONFIG_IDENT_STRING
19 #define CONFIG_IDENT_STRING "MPC512X"
23 #define CONFIG_521X 1 /* needed for Linux kernel header files*/
25 #include <asm/immap_512x.h>
26 #include "asm-offsets.h"
28 #include <ppc_asm.tmpl>
31 #include <asm/cache.h>
33 #include <asm/u-boot.h>
36 * Floating Point enable, Machine Check and Recoverable Interr.
40 #define MSR_KERNEL (MSR_FP|MSR_RI)
42 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
45 /* Macros for manipulating CSx_START/STOP */
46 #define START_REG(start) ((start) >> 16)
47 #define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
50 * Set up GOT: Global Offset Table
52 * Use r12 to access the GOT
55 GOT_ENTRY(_GOT2_TABLE_)
56 GOT_ENTRY(_FIXUP_TABLE_)
59 GOT_ENTRY(_start_of_vectors)
60 GOT_ENTRY(_end_of_vectors)
61 GOT_ENTRY(transfer_to_handler)
65 GOT_ENTRY(__bss_start)
69 * Magic number and version string
71 .long 0x27051956 /* U-Boot Magic Number */
74 .ascii U_BOOT_VERSION_STRING, "\0"
83 /* Start from here after reset/power on */
87 .globl _start_of_vectors
91 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
93 /* Data Storage exception. */
94 STD_EXCEPTION(0x300, DataStorage, UnknownException)
96 /* Instruction Storage exception. */
97 STD_EXCEPTION(0x400, InstStorage, UnknownException)
99 /* External Interrupt exception. */
100 STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
102 /* Alignment exception. */
105 EXCEPTION_PROLOG(SRR0, SRR1)
110 addi r3,r1,STACK_FRAME_OVERHEAD
111 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
113 /* Program check exception */
116 EXCEPTION_PROLOG(SRR0, SRR1)
117 addi r3,r1,STACK_FRAME_OVERHEAD
118 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
121 /* Floating Point Unit unavailable exception */
122 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
125 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
127 /* Critical interrupt */
128 STD_EXCEPTION(0xa00, Critical, UnknownException)
131 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
133 /* Trace interrupt */
134 STD_EXCEPTION(0xd00, Trace, UnknownException)
136 /* Performance Monitor interrupt */
137 STD_EXCEPTION(0xf00, PerfMon, UnknownException)
139 /* Intruction Translation Miss */
140 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
142 /* Data Load Translation Miss */
143 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
145 /* Data Store Translation Miss */
146 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
148 /* Instruction Address Breakpoint */
149 STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
151 /* System Management interrupt */
152 STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
154 .globl _end_of_vectors
159 /* Save msr contents */
162 /* Set IMMR area to our preferred location */
163 lis r4, CONFIG_DEFAULT_IMMR@h
164 lis r3, CONFIG_SYS_IMMR@h
165 ori r3, r3, CONFIG_SYS_IMMR@l
167 mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
169 /* Initialise the machine */
173 * Set up Local Access Windows:
175 * 1) Boot/CS0 (boot FLASH)
176 * 2) On-chip SRAM (initial stack purposes)
179 /* Boot CS/CS0 window range */
180 lis r3, CONFIG_SYS_IMMR@h
181 ori r3, r3, CONFIG_SYS_IMMR@l
183 lis r4, START_REG(CONFIG_SYS_FLASH_BASE)
184 ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
188 * The SRAM window has a fixed size (256K), so only the start address
191 lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
195 * According to MPC5121e RM, configuring local access windows should
196 * be followed by a dummy read of the config register that was
197 * modified last and an isync
203 * Set configuration of the Boot/CS0, the SRAM window does not have a
204 * config register so no params can be set for it
206 lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
207 ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
209 lis r4, CONFIG_SYS_CS0_CFG@h
210 ori r4, r4, CONFIG_SYS_CS0_CFG@l
211 stw r4, CS0_CONFIG(r3)
213 /* Master enable all CS's */
215 ori r4, r4, CS_CTRL_ME@l
218 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
219 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
220 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
225 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
226 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
228 li r0, 0 /* Make room for stack frame header and */
229 stwu r0, -4(r1) /* clear final stack frame so that */
230 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
232 /* let the C-code set up the rest */
234 /* Be careful to keep code relocatable & stack humble */
235 /*------------------------------------------------------*/
237 GET_GOT /* initialize GOT access */
240 lis r3, CONFIG_SYS_IMMR@h
241 /* run low-level CPU init code (in Flash) */
244 /* run 1st part of board init code (in Flash) */
247 /* NOTREACHED - board_init_f() does not return */
250 * This code finishes saving the registers to the exception frame
251 * and jumps to the appropriate handler for the exception.
252 * Register r21 is pointer into trap frame, r1 has new stack pointer.
254 .globl transfer_to_handler
265 andi. r24,r23,0x3f00 /* get vector offset */
269 lwz r24,0(r23) /* virtual address of handler */
270 lwz r23,4(r23) /* where to go when done */
275 rfi /* jump to handler, enable MMU */
278 mfmsr r28 /* Disable interrupts */
282 SYNC /* Some chip revs need this... */
297 lwz r2,_NIP(r1) /* Restore environment */
308 * This code initialises the machine, it expects original MSR contents to be in r5.
311 /* Initialize machine status; enable machine check interrupt */
312 /*-----------------------------------------------------------*/
314 li r3, MSR_KERNEL /* Set ME and RI flags */
315 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
317 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
321 mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
323 lis r3, CONFIG_SYS_IMMR@h
325 #if defined(CONFIG_WATCHDOG)
326 /* Initialise the watchdog and reset it */
327 /*--------------------------------------*/
328 lis r4, CONFIG_SYS_WATCHDOG_VALUE
329 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
339 /* Disable the watchdog */
340 /*----------------------*/
343 * Check to see if it's enabled for disabling: once disabled by s/w
344 * it's not possible to re-enable it
351 #endif /* CONFIG_WATCHDOG */
353 /* Initialize the Hardware Implementation-dependent Registers */
354 /* HID0 also contains cache control */
355 /*------------------------------------------------------*/
356 lis r3, CONFIG_SYS_HID0_INIT@h
357 ori r3, r3, CONFIG_SYS_HID0_INIT@l
361 lis r3, CONFIG_SYS_HID0_FINAL@h
362 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
366 lis r3, CONFIG_SYS_HID2@h
367 ori r3, r3, CONFIG_SYS_HID2@l
376 * Note: requires that all cache bits in
377 * HID0 are in the low half word.
384 ori r4, r4, HID0_ILOCK
386 ori r4, r3, HID0_ICFI
388 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
390 mtspr HID0, r3 /* clears invalidate */
393 .globl icache_disable
397 ori r4, r4, HID0_ICE|HID0_ILOCK
399 ori r4, r3, HID0_ICFI
401 mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
403 mtspr HID0, r3 /* clears invalidate */
409 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
415 li r5, HID0_DCFI|HID0_DLOCK
417 mtspr HID0, r3 /* no invalidate, unlock */
419 ori r5, r3, HID0_DCFI
420 mtspr HID0, r5 /* enable + invalidate */
421 mtspr HID0, r3 /* enable */
425 .globl dcache_disable
429 ori r4, r4, HID0_DCE|HID0_DLOCK
433 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
435 mtspr HID0, r3 /* clears invalidate */
441 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
449 /*-------------------------------------------------------------------*/
452 * void relocate_code (addr_sp, gd, addr_moni)
454 * This "function" does not return, instead it continues in RAM
455 * after relocating the monitor code.
459 * r5 = length in bytes
464 mr r1, r3 /* Set new stack pointer */
465 mr r9, r4 /* Save copy of Global Data pointer */
466 mr r10, r5 /* Save copy of Destination Address */
469 mr r3, r5 /* Destination Address */
470 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
471 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
472 lwz r5, GOT(__init_end)
474 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
479 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
480 * + Destination Address
486 /* First our own GOT */
488 /* then the one used by the C code */
497 beq cr1,4f /* In place copy is not necessary */
498 beq 7f /* Protect against 0 count */
527 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
535 * Now flush the cache: note that we must start from a cache aligned
536 * address. Otherwise we might miss one cache line.
540 beq 7f /* Always flush prefetch queue in any case */
548 sync /* Wait for all dcbst to complete on bus */
554 7: sync /* Wait for all icbi to complete on bus */
558 * We are done. Do not return, instead branch to second part of board
559 * initialization, now running from RAM.
561 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
567 * Relocation Function, r12 point to got2+0x8000
569 * Adjust got2 pointers, no need to check for 0, this code
570 * already puts a few entries in the table.
572 li r0,__got2_entries@sectoff@l
573 la r3,GOT(_GOT2_TABLE_)
574 lwz r11,GOT(_GOT2_TABLE_)
586 * Now adjust the fixups and the pointers to the fixups
587 * in case we need to move ourselves again.
589 li r0,__fixup_entries@sectoff@l
590 lwz r3,GOT(_FIXUP_TABLE_)
606 * Now clear BSS segment
608 lwz r3,GOT(__bss_start)
609 lwz r4,GOT(__bss_end)
621 mr r3, r9 /* Global Data pointer */
622 mr r4, r10 /* Destination Address */
626 * Copy exception vector code to low memory
629 * r7: source address, r8: end address, r9: target address
633 mflr r4 /* save link register */
636 lwz r8, GOT(_end_of_vectors)
638 li r9, 0x100 /* reset vector at 0x100 */
641 bgelr /* return if r7>=r8 - just in case */
651 * relocate `hdlr' and `int_return' entries
653 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
654 li r8, Alignment - _start + EXC_OFF_SYS_RESET
657 addi r7, r7, 0x100 /* next exception vector */
661 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
664 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
667 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
668 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
671 addi r7, r7, 0x100 /* next exception vector */
675 li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
676 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
679 addi r7, r7, 0x100 /* next exception vector */
683 mfmsr r3 /* now that the vectors have */
684 lis r7, MSR_IP@h /* relocated into low memory */
685 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
686 andc r3, r3, r7 /* (if it was on) */
687 SYNC /* Some chip revs need this... */
691 mtlr r4 /* restore link register */