2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2001 Josh Huber <huber@mclx.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 /* U-Boot - Startup Code for PowerPC based Embedded Boards
13 * The processor starts at 0xfff00100 and the code is executed
14 * from flash. The code is organized to be at an other address
15 * in memory, but as long we don't jump around before relocating.
16 * board_init lies at a quite high address and when the cpu has
17 * jumped there, everything is ok.
19 #include <asm-offsets.h>
24 #include <ppc_asm.tmpl>
27 #include <asm/cache.h>
29 #include <asm/u-boot.h>
31 #if !defined(CONFIG_DB64360) && \
32 !defined(CONFIG_DB64460) && \
33 !defined(CONFIG_CPCI750) && \
35 #include <galileo/gt64260R.h>
38 /* We don't want the MMU yet.
41 /* Machine Check and Recoverable Interr. */
42 #define MSR_KERNEL ( MSR_ME | MSR_RI )
45 * Set up GOT: Global Offset Table
47 * Use r12 to access the GOT
50 GOT_ENTRY(_GOT2_TABLE_)
51 GOT_ENTRY(_FIXUP_TABLE_)
54 GOT_ENTRY(_start_of_vectors)
55 GOT_ENTRY(_end_of_vectors)
56 GOT_ENTRY(transfer_to_handler)
60 GOT_ENTRY(__bss_start)
64 * r3 - 1st arg to board_init(): IMMP pointer
65 * r4 - 2nd arg to board_init(): boot flag
68 .long 0x27051956 /* U-Boot Magic Number */
71 .ascii U_BOOT_VERSION_STRING, "\0"
78 /* the boot code is located below the exception table */
80 .globl _start_of_vectors
84 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
86 /* Data Storage exception. "Never" generated on the 860. */
87 STD_EXCEPTION(0x300, DataStorage, UnknownException)
89 /* Instruction Storage exception. "Never" generated on the 860. */
90 STD_EXCEPTION(0x400, InstStorage, UnknownException)
92 /* External Interrupt exception. */
93 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
95 /* Alignment exception. */
98 EXCEPTION_PROLOG(SRR0, SRR1)
103 addi r3,r1,STACK_FRAME_OVERHEAD
104 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
106 /* Program check exception */
109 EXCEPTION_PROLOG(SRR0, SRR1)
110 addi r3,r1,STACK_FRAME_OVERHEAD
111 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
114 /* No FPU on MPC8xx. This exception is not supposed to happen.
116 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
118 /* I guess we could implement decrementer, and may have
119 * to someday for timekeeping.
121 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
122 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
123 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
124 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
125 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
127 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
128 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
131 * On the MPC8xx, this is a software emulation interrupt. It
132 * occurs for all unimplemented and illegal instructions.
134 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
136 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
137 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
138 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
139 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
141 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
142 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
143 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
144 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
145 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
146 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
147 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
149 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
150 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
151 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
152 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
154 .globl _end_of_vectors
160 /* disable everything */
169 /* init the L2 cache */
170 addis r3, r0, L2_INIT@h
171 ori r3, r3, L2_INIT@l
175 #if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
178 * dssall instruction, gas doesn't have it yet
179 * ...for altivec, data stream stop all this probably
180 * isn't needed unless we warm (software) reboot U-Boot
185 /* invalidate the L2 cache */
186 bl l2cache_invalidate
189 #ifdef CONFIG_SYS_BOARD_ASM_INIT
195 * Calculate absolute address in FLASH and jump there
196 *------------------------------------------------------*/
197 lis r3, CONFIG_SYS_MONITOR_BASE@h
198 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
199 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
204 /* let the C-code set up the rest */
206 /* Be careful to keep code relocatable ! */
207 /*------------------------------------------------------*/
209 /* perform low-level init */
210 /* sdram init, galileo init, etc */
211 /* r3: NHR bit from HID0 */
218 * Cache must be enabled here for stack-in-cache trick.
219 * This means we need to enable the BATS.
221 * 1) for the EVB, original gt regs need to be mapped
222 * 2) need to have an IBAT for the 0xf region,
223 * we are running there!
224 * Cache should be turned on after BATs, since by default
225 * everything is write-through.
226 * The init-mem BAT can be reused after reloc. The old
227 * gt-regs BAT can be reused after board_init_f calls
228 * board_early_init_f (EVB only).
230 #if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
231 /* enable address translation */
235 /* enable and invalidate the data cache */
239 #ifdef CONFIG_SYS_INIT_RAM_LOCK
244 /* set up the stack pointer in our newly created
246 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
247 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
249 li r0, 0 /* Make room for stack frame header and */
250 stwu r0, -4(r1) /* clear final stack frame so that */
251 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
253 GET_GOT /* initialize GOT access */
255 /* run low-level CPU init code (from Flash) */
259 /* run 1st part of board init code (from Flash) */
263 /* NOTREACHED - board_init_f() does not return */
265 .globl invalidate_bats
267 /* invalidate BATs */
272 #ifdef CONFIG_HIGH_BATS
283 #ifdef CONFIG_HIGH_BATS
293 /* setup_bats - set them up to some initial state */
299 addis r4, r0, CONFIG_SYS_IBAT0L@h
300 ori r4, r4, CONFIG_SYS_IBAT0L@l
301 addis r3, r0, CONFIG_SYS_IBAT0U@h
302 ori r3, r3, CONFIG_SYS_IBAT0U@l
308 addis r4, r0, CONFIG_SYS_DBAT0L@h
309 ori r4, r4, CONFIG_SYS_DBAT0L@l
310 addis r3, r0, CONFIG_SYS_DBAT0U@h
311 ori r3, r3, CONFIG_SYS_DBAT0U@l
317 addis r4, r0, CONFIG_SYS_IBAT1L@h
318 ori r4, r4, CONFIG_SYS_IBAT1L@l
319 addis r3, r0, CONFIG_SYS_IBAT1U@h
320 ori r3, r3, CONFIG_SYS_IBAT1U@l
326 addis r4, r0, CONFIG_SYS_DBAT1L@h
327 ori r4, r4, CONFIG_SYS_DBAT1L@l
328 addis r3, r0, CONFIG_SYS_DBAT1U@h
329 ori r3, r3, CONFIG_SYS_DBAT1U@l
335 addis r4, r0, CONFIG_SYS_IBAT2L@h
336 ori r4, r4, CONFIG_SYS_IBAT2L@l
337 addis r3, r0, CONFIG_SYS_IBAT2U@h
338 ori r3, r3, CONFIG_SYS_IBAT2U@l
344 addis r4, r0, CONFIG_SYS_DBAT2L@h
345 ori r4, r4, CONFIG_SYS_DBAT2L@l
346 addis r3, r0, CONFIG_SYS_DBAT2U@h
347 ori r3, r3, CONFIG_SYS_DBAT2U@l
353 addis r4, r0, CONFIG_SYS_IBAT3L@h
354 ori r4, r4, CONFIG_SYS_IBAT3L@l
355 addis r3, r0, CONFIG_SYS_IBAT3U@h
356 ori r3, r3, CONFIG_SYS_IBAT3U@l
362 addis r4, r0, CONFIG_SYS_DBAT3L@h
363 ori r4, r4, CONFIG_SYS_DBAT3L@l
364 addis r3, r0, CONFIG_SYS_DBAT3U@h
365 ori r3, r3, CONFIG_SYS_DBAT3U@l
370 #ifdef CONFIG_HIGH_BATS
372 addis r4, r0, CONFIG_SYS_IBAT4L@h
373 ori r4, r4, CONFIG_SYS_IBAT4L@l
374 addis r3, r0, CONFIG_SYS_IBAT4U@h
375 ori r3, r3, CONFIG_SYS_IBAT4U@l
381 addis r4, r0, CONFIG_SYS_DBAT4L@h
382 ori r4, r4, CONFIG_SYS_DBAT4L@l
383 addis r3, r0, CONFIG_SYS_DBAT4U@h
384 ori r3, r3, CONFIG_SYS_DBAT4U@l
390 addis r4, r0, CONFIG_SYS_IBAT5L@h
391 ori r4, r4, CONFIG_SYS_IBAT5L@l
392 addis r3, r0, CONFIG_SYS_IBAT5U@h
393 ori r3, r3, CONFIG_SYS_IBAT5U@l
399 addis r4, r0, CONFIG_SYS_DBAT5L@h
400 ori r4, r4, CONFIG_SYS_DBAT5L@l
401 addis r3, r0, CONFIG_SYS_DBAT5U@h
402 ori r3, r3, CONFIG_SYS_DBAT5U@l
408 addis r4, r0, CONFIG_SYS_IBAT6L@h
409 ori r4, r4, CONFIG_SYS_IBAT6L@l
410 addis r3, r0, CONFIG_SYS_IBAT6U@h
411 ori r3, r3, CONFIG_SYS_IBAT6U@l
417 addis r4, r0, CONFIG_SYS_DBAT6L@h
418 ori r4, r4, CONFIG_SYS_DBAT6L@l
419 addis r3, r0, CONFIG_SYS_DBAT6U@h
420 ori r3, r3, CONFIG_SYS_DBAT6U@l
426 addis r4, r0, CONFIG_SYS_IBAT7L@h
427 ori r4, r4, CONFIG_SYS_IBAT7L@l
428 addis r3, r0, CONFIG_SYS_IBAT7U@h
429 ori r3, r3, CONFIG_SYS_IBAT7U@l
435 addis r4, r0, CONFIG_SYS_DBAT7L@h
436 ori r4, r4, CONFIG_SYS_DBAT7L@l
437 addis r3, r0, CONFIG_SYS_DBAT7U@h
438 ori r3, r3, CONFIG_SYS_DBAT7U@l
444 /* bats are done, now invalidate the TLBs */
447 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
460 .globl enable_addr_trans
462 /* enable address translation */
464 ori r5, r5, (MSR_IR | MSR_DR)
469 .globl disable_addr_trans
471 /* disable address translation */
474 andi. r0, r3, (MSR_IR | MSR_DR)
482 * This code finishes saving the registers to the exception frame
483 * and jumps to the appropriate handler for the exception.
484 * Register r21 is pointer into trap frame, r1 has new stack pointer.
486 .globl transfer_to_handler
497 andi. r24,r23,0x3f00 /* get vector offset */
501 mtspr SPRG2,r22 /* r1 is now kernel sp */
502 lwz r24,0(r23) /* virtual address of handler */
503 lwz r23,4(r23) /* where to go when done */
508 rfi /* jump to handler, enable MMU */
511 mfmsr r28 /* Disable interrupts */
515 SYNC /* Some chip revs need this... */
530 lwz r2,_NIP(r1) /* Restore environment */
549 /*-----------------------------------------------------------------------*/
551 * void relocate_code (addr_sp, gd, addr_moni)
553 * This "function" does not return, instead it continues in RAM
554 * after relocating the monitor code.
558 * r5 = length in bytes
563 mr r1, r3 /* Set new stack pointer */
564 mr r9, r4 /* Save copy of Global Data pointer */
565 mr r10, r5 /* Save copy of Destination Address */
568 mr r3, r5 /* Destination Address */
569 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
570 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
571 lwz r5, GOT(__init_end)
573 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
578 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
584 /* First our own GOT */
586 /* then the one used by the C code */
593 bl board_relocate_rom
595 mr r3, r10 /* Destination Address */
596 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
597 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
598 lwz r5, GOT(__init_end)
600 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
605 beq cr1,4f /* In place copy is not necessary */
606 beq 7f /* Protect against 0 count */
625 * Now flush the cache: note that we must start from a cache aligned
626 * address. Otherwise we might miss one cache line.
630 beq 7f /* Always flush prefetch queue in any case */
638 sync /* Wait for all dcbst to complete on bus */
644 7: sync /* Wait for all icbi to complete on bus */
648 * We are done. Do not return, instead branch to second part of board
649 * initialization, now running from RAM.
651 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
660 * Relocation Function, r12 point to got2+0x8000
662 * Adjust got2 pointers, no need to check for 0, this code
663 * already puts a few entries in the table.
665 li r0,__got2_entries@sectoff@l
666 la r3,GOT(_GOT2_TABLE_)
667 lwz r11,GOT(_GOT2_TABLE_)
679 * Now adjust the fixups and the pointers to the fixups
680 * in case we need to move ourselves again.
682 li r0,__fixup_entries@sectoff@l
683 lwz r3,GOT(_FIXUP_TABLE_)
699 * Now clear BSS segment
701 lwz r3,GOT(__bss_start)
702 lwz r4,GOT(__bss_end)
714 mr r3, r10 /* Destination Address */
715 #if defined(CONFIG_DB64360) || \
716 defined(CONFIG_DB64460) || \
717 defined(CONFIG_CPCI750) || \
718 defined(CONFIG_PPMC7XX) || \
720 mr r4, r9 /* Use RAM copy of the global data */
724 /* not reached - end relocate_code */
725 /*-----------------------------------------------------------------------*/
728 * Copy exception vector code to low memory
731 * r7: source address, r8: end address, r9: target address
735 mflr r4 /* save link register */
738 lwz r8, GOT(_end_of_vectors)
740 li r9, 0x100 /* reset vector always at 0x100 */
743 bgelr /* return if r7>=r8 - just in case */
753 * relocate `hdlr' and `int_return' entries
755 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
756 li r8, Alignment - _start + EXC_OFF_SYS_RESET
759 addi r7, r7, 0x100 /* next exception vector */
763 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
766 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
769 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
770 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
773 addi r7, r7, 0x100 /* next exception vector */
777 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
778 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
781 addi r7, r7, 0x100 /* next exception vector */
785 /* enable execptions from RAM vectors */
791 mtlr r4 /* restore link register */
794 #ifdef CONFIG_SYS_INIT_RAM_LOCK
796 /* Allocate Initial RAM in data cache.
798 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
799 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
800 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
801 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
808 /* Lock the data cache */
816 .globl unlock_ram_in_cache
818 /* invalidate the INIT_RAM section */
819 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
820 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
821 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
822 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
827 sync /* Wait for all icbi to complete on bus */
830 /* Unlock the data cache and invalidate it */