2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2001 Josh Huber <huber@mclx.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /* U-Boot - Startup Code for PowerPC based Embedded Boards
29 * The processor starts at 0xfff00100 and the code is executed
30 * from flash. The code is organized to be at an other address
31 * in memory, but as long we don't jump around before relocating.
32 * board_init lies at a quite high address and when the cpu has
33 * jumped there, everything is ok.
35 #include <asm-offsets.h>
38 #include <timestamp.h>
41 #include <ppc_asm.tmpl>
44 #include <asm/cache.h>
46 #include <asm/u-boot.h>
48 #if !defined(CONFIG_DB64360) && \
49 !defined(CONFIG_DB64460) && \
50 !defined(CONFIG_CPCI750) && \
52 #include <galileo/gt64260R.h>
55 #ifndef CONFIG_IDENT_STRING
56 #define CONFIG_IDENT_STRING ""
59 /* We don't want the MMU yet.
62 /* Machine Check and Recoverable Interr. */
63 #define MSR_KERNEL ( MSR_ME | MSR_RI )
66 * Set up GOT: Global Offset Table
68 * Use r12 to access the GOT
71 GOT_ENTRY(_GOT2_TABLE_)
72 GOT_ENTRY(_FIXUP_TABLE_)
75 GOT_ENTRY(_start_of_vectors)
76 GOT_ENTRY(_end_of_vectors)
77 GOT_ENTRY(transfer_to_handler)
81 GOT_ENTRY(__bss_start)
85 * r3 - 1st arg to board_init(): IMMP pointer
86 * r4 - 2nd arg to board_init(): boot flag
89 .long 0x27051956 /* U-Boot Magic Number */
93 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
94 .ascii CONFIG_IDENT_STRING, "\0"
101 /* the boot code is located below the exception table */
103 .globl _start_of_vectors
107 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
109 /* Data Storage exception. "Never" generated on the 860. */
110 STD_EXCEPTION(0x300, DataStorage, UnknownException)
112 /* Instruction Storage exception. "Never" generated on the 860. */
113 STD_EXCEPTION(0x400, InstStorage, UnknownException)
115 /* External Interrupt exception. */
116 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
118 /* Alignment exception. */
121 EXCEPTION_PROLOG(SRR0, SRR1)
126 addi r3,r1,STACK_FRAME_OVERHEAD
127 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
129 /* Program check exception */
132 EXCEPTION_PROLOG(SRR0, SRR1)
133 addi r3,r1,STACK_FRAME_OVERHEAD
134 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
137 /* No FPU on MPC8xx. This exception is not supposed to happen.
139 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
141 /* I guess we could implement decrementer, and may have
142 * to someday for timekeeping.
144 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
145 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
146 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
147 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
148 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
150 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
151 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
154 * On the MPC8xx, this is a software emulation interrupt. It
155 * occurs for all unimplemented and illegal instructions.
157 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
159 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
160 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
161 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
162 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
164 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
165 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
166 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
167 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
168 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
169 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
170 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
172 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
173 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
174 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
175 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
177 .globl _end_of_vectors
183 /* disable everything */
192 /* init the L2 cache */
193 addis r3, r0, L2_INIT@h
194 ori r3, r3, L2_INIT@l
198 #if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
201 * dssall instruction, gas doesn't have it yet
202 * ...for altivec, data stream stop all this probably
203 * isn't needed unless we warm (software) reboot U-Boot
208 /* invalidate the L2 cache */
209 bl l2cache_invalidate
212 #ifdef CONFIG_SYS_BOARD_ASM_INIT
218 * Calculate absolute address in FLASH and jump there
219 *------------------------------------------------------*/
220 lis r3, CONFIG_SYS_MONITOR_BASE@h
221 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
222 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
227 /* let the C-code set up the rest */
229 /* Be careful to keep code relocatable ! */
230 /*------------------------------------------------------*/
232 /* perform low-level init */
233 /* sdram init, galileo init, etc */
234 /* r3: NHR bit from HID0 */
241 * Cache must be enabled here for stack-in-cache trick.
242 * This means we need to enable the BATS.
244 * 1) for the EVB, original gt regs need to be mapped
245 * 2) need to have an IBAT for the 0xf region,
246 * we are running there!
247 * Cache should be turned on after BATs, since by default
248 * everything is write-through.
249 * The init-mem BAT can be reused after reloc. The old
250 * gt-regs BAT can be reused after board_init_f calls
251 * board_early_init_f (EVB only).
253 #if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
254 /* enable address translation */
258 /* enable and invalidate the data cache */
262 #ifdef CONFIG_SYS_INIT_RAM_LOCK
267 /* set up the stack pointer in our newly created
269 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
270 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
272 li r0, 0 /* Make room for stack frame header and */
273 stwu r0, -4(r1) /* clear final stack frame so that */
274 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
276 GET_GOT /* initialize GOT access */
278 /* run low-level CPU init code (from Flash) */
282 /* run 1st part of board init code (from Flash) */
286 /* NOTREACHED - board_init_f() does not return */
288 .globl invalidate_bats
290 /* invalidate BATs */
295 #ifdef CONFIG_HIGH_BATS
306 #ifdef CONFIG_HIGH_BATS
316 /* setup_bats - set them up to some initial state */
322 addis r4, r0, CONFIG_SYS_IBAT0L@h
323 ori r4, r4, CONFIG_SYS_IBAT0L@l
324 addis r3, r0, CONFIG_SYS_IBAT0U@h
325 ori r3, r3, CONFIG_SYS_IBAT0U@l
331 addis r4, r0, CONFIG_SYS_DBAT0L@h
332 ori r4, r4, CONFIG_SYS_DBAT0L@l
333 addis r3, r0, CONFIG_SYS_DBAT0U@h
334 ori r3, r3, CONFIG_SYS_DBAT0U@l
340 addis r4, r0, CONFIG_SYS_IBAT1L@h
341 ori r4, r4, CONFIG_SYS_IBAT1L@l
342 addis r3, r0, CONFIG_SYS_IBAT1U@h
343 ori r3, r3, CONFIG_SYS_IBAT1U@l
349 addis r4, r0, CONFIG_SYS_DBAT1L@h
350 ori r4, r4, CONFIG_SYS_DBAT1L@l
351 addis r3, r0, CONFIG_SYS_DBAT1U@h
352 ori r3, r3, CONFIG_SYS_DBAT1U@l
358 addis r4, r0, CONFIG_SYS_IBAT2L@h
359 ori r4, r4, CONFIG_SYS_IBAT2L@l
360 addis r3, r0, CONFIG_SYS_IBAT2U@h
361 ori r3, r3, CONFIG_SYS_IBAT2U@l
367 addis r4, r0, CONFIG_SYS_DBAT2L@h
368 ori r4, r4, CONFIG_SYS_DBAT2L@l
369 addis r3, r0, CONFIG_SYS_DBAT2U@h
370 ori r3, r3, CONFIG_SYS_DBAT2U@l
376 addis r4, r0, CONFIG_SYS_IBAT3L@h
377 ori r4, r4, CONFIG_SYS_IBAT3L@l
378 addis r3, r0, CONFIG_SYS_IBAT3U@h
379 ori r3, r3, CONFIG_SYS_IBAT3U@l
385 addis r4, r0, CONFIG_SYS_DBAT3L@h
386 ori r4, r4, CONFIG_SYS_DBAT3L@l
387 addis r3, r0, CONFIG_SYS_DBAT3U@h
388 ori r3, r3, CONFIG_SYS_DBAT3U@l
393 #ifdef CONFIG_HIGH_BATS
395 addis r4, r0, CONFIG_SYS_IBAT4L@h
396 ori r4, r4, CONFIG_SYS_IBAT4L@l
397 addis r3, r0, CONFIG_SYS_IBAT4U@h
398 ori r3, r3, CONFIG_SYS_IBAT4U@l
404 addis r4, r0, CONFIG_SYS_DBAT4L@h
405 ori r4, r4, CONFIG_SYS_DBAT4L@l
406 addis r3, r0, CONFIG_SYS_DBAT4U@h
407 ori r3, r3, CONFIG_SYS_DBAT4U@l
413 addis r4, r0, CONFIG_SYS_IBAT5L@h
414 ori r4, r4, CONFIG_SYS_IBAT5L@l
415 addis r3, r0, CONFIG_SYS_IBAT5U@h
416 ori r3, r3, CONFIG_SYS_IBAT5U@l
422 addis r4, r0, CONFIG_SYS_DBAT5L@h
423 ori r4, r4, CONFIG_SYS_DBAT5L@l
424 addis r3, r0, CONFIG_SYS_DBAT5U@h
425 ori r3, r3, CONFIG_SYS_DBAT5U@l
431 addis r4, r0, CONFIG_SYS_IBAT6L@h
432 ori r4, r4, CONFIG_SYS_IBAT6L@l
433 addis r3, r0, CONFIG_SYS_IBAT6U@h
434 ori r3, r3, CONFIG_SYS_IBAT6U@l
440 addis r4, r0, CONFIG_SYS_DBAT6L@h
441 ori r4, r4, CONFIG_SYS_DBAT6L@l
442 addis r3, r0, CONFIG_SYS_DBAT6U@h
443 ori r3, r3, CONFIG_SYS_DBAT6U@l
449 addis r4, r0, CONFIG_SYS_IBAT7L@h
450 ori r4, r4, CONFIG_SYS_IBAT7L@l
451 addis r3, r0, CONFIG_SYS_IBAT7U@h
452 ori r3, r3, CONFIG_SYS_IBAT7U@l
458 addis r4, r0, CONFIG_SYS_DBAT7L@h
459 ori r4, r4, CONFIG_SYS_DBAT7L@l
460 addis r3, r0, CONFIG_SYS_DBAT7U@h
461 ori r3, r3, CONFIG_SYS_DBAT7U@l
467 /* bats are done, now invalidate the TLBs */
470 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
483 .globl enable_addr_trans
485 /* enable address translation */
487 ori r5, r5, (MSR_IR | MSR_DR)
492 .globl disable_addr_trans
494 /* disable address translation */
497 andi. r0, r3, (MSR_IR | MSR_DR)
505 * This code finishes saving the registers to the exception frame
506 * and jumps to the appropriate handler for the exception.
507 * Register r21 is pointer into trap frame, r1 has new stack pointer.
509 .globl transfer_to_handler
520 andi. r24,r23,0x3f00 /* get vector offset */
524 mtspr SPRG2,r22 /* r1 is now kernel sp */
525 lwz r24,0(r23) /* virtual address of handler */
526 lwz r23,4(r23) /* where to go when done */
531 rfi /* jump to handler, enable MMU */
534 mfmsr r28 /* Disable interrupts */
538 SYNC /* Some chip revs need this... */
553 lwz r2,_NIP(r1) /* Restore environment */
572 /*-----------------------------------------------------------------------*/
574 * void relocate_code (addr_sp, gd, addr_moni)
576 * This "function" does not return, instead it continues in RAM
577 * after relocating the monitor code.
581 * r5 = length in bytes
586 mr r1, r3 /* Set new stack pointer */
587 mr r9, r4 /* Save copy of Global Data pointer */
588 mr r10, r5 /* Save copy of Destination Address */
591 mr r3, r5 /* Destination Address */
592 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
593 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
594 lwz r5, GOT(__init_end)
596 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
601 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
607 /* First our own GOT */
609 /* then the one used by the C code */
616 bl board_relocate_rom
618 mr r3, r10 /* Destination Address */
619 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
620 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
621 lwz r5, GOT(__init_end)
623 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
628 beq cr1,4f /* In place copy is not necessary */
629 beq 7f /* Protect against 0 count */
648 * Now flush the cache: note that we must start from a cache aligned
649 * address. Otherwise we might miss one cache line.
653 beq 7f /* Always flush prefetch queue in any case */
661 sync /* Wait for all dcbst to complete on bus */
667 7: sync /* Wait for all icbi to complete on bus */
671 * We are done. Do not return, instead branch to second part of board
672 * initialization, now running from RAM.
674 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
683 * Relocation Function, r12 point to got2+0x8000
685 * Adjust got2 pointers, no need to check for 0, this code
686 * already puts a few entries in the table.
688 li r0,__got2_entries@sectoff@l
689 la r3,GOT(_GOT2_TABLE_)
690 lwz r11,GOT(_GOT2_TABLE_)
702 * Now adjust the fixups and the pointers to the fixups
703 * in case we need to move ourselves again.
705 li r0,__fixup_entries@sectoff@l
706 lwz r3,GOT(_FIXUP_TABLE_)
722 * Now clear BSS segment
724 lwz r3,GOT(__bss_start)
737 mr r3, r10 /* Destination Address */
738 #if defined(CONFIG_DB64360) || \
739 defined(CONFIG_DB64460) || \
740 defined(CONFIG_CPCI750) || \
741 defined(CONFIG_PPMC7XX) || \
743 mr r4, r9 /* Use RAM copy of the global data */
747 /* not reached - end relocate_code */
748 /*-----------------------------------------------------------------------*/
751 * Copy exception vector code to low memory
754 * r7: source address, r8: end address, r9: target address
758 mflr r4 /* save link register */
761 lwz r8, GOT(_end_of_vectors)
763 li r9, 0x100 /* reset vector always at 0x100 */
766 bgelr /* return if r7>=r8 - just in case */
776 * relocate `hdlr' and `int_return' entries
778 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
779 li r8, Alignment - _start + EXC_OFF_SYS_RESET
782 addi r7, r7, 0x100 /* next exception vector */
786 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
789 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
792 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
793 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
796 addi r7, r7, 0x100 /* next exception vector */
800 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
801 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
804 addi r7, r7, 0x100 /* next exception vector */
808 /* enable execptions from RAM vectors */
814 mtlr r4 /* restore link register */
817 #ifdef CONFIG_SYS_INIT_RAM_LOCK
819 /* Allocate Initial RAM in data cache.
821 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
822 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
823 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
824 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
831 /* Lock the data cache */
839 .globl unlock_ram_in_cache
841 /* invalidate the INIT_RAM section */
842 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
843 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
844 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
845 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
850 sync /* Wait for all icbi to complete on bus */
853 /* Unlock the data cache and invalidate it */