2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2001 Josh Huber <huber@mclx.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /* U-Boot - Startup Code for PowerPC based Embedded Boards
29 * The processor starts at 0xfff00100 and the code is executed
30 * from flash. The code is organized to be at an other address
31 * in memory, but as long we don't jump around before relocating.
32 * board_init lies at a quite high address and when the cpu has
33 * jumped there, everything is ok.
37 #include <timestamp.h>
40 #include <ppc_asm.tmpl>
43 #include <asm/cache.h>
45 #include <asm/u-boot.h>
47 #if !defined(CONFIG_DB64360) && \
48 !defined(CONFIG_DB64460) && \
49 !defined(CONFIG_CPCI750) && \
51 #include <galileo/gt64260R.h>
54 #ifndef CONFIG_IDENT_STRING
55 #define CONFIG_IDENT_STRING ""
58 /* We don't want the MMU yet.
61 /* Machine Check and Recoverable Interr. */
62 #define MSR_KERNEL ( MSR_ME | MSR_RI )
65 * Set up GOT: Global Offset Table
67 * Use r12 to access the GOT
70 GOT_ENTRY(_GOT2_TABLE_)
71 GOT_ENTRY(_FIXUP_TABLE_)
74 GOT_ENTRY(_start_of_vectors)
75 GOT_ENTRY(_end_of_vectors)
76 GOT_ENTRY(transfer_to_handler)
80 GOT_ENTRY(__bss_start)
84 * r3 - 1st arg to board_init(): IMMP pointer
85 * r4 - 2nd arg to board_init(): boot flag
88 .long 0x27051956 /* U-Boot Magic Number */
92 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
93 .ascii CONFIG_IDENT_STRING, "\0"
100 /* the boot code is located below the exception table */
102 .globl _start_of_vectors
106 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
108 /* Data Storage exception. "Never" generated on the 860. */
109 STD_EXCEPTION(0x300, DataStorage, UnknownException)
111 /* Instruction Storage exception. "Never" generated on the 860. */
112 STD_EXCEPTION(0x400, InstStorage, UnknownException)
114 /* External Interrupt exception. */
115 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
117 /* Alignment exception. */
120 EXCEPTION_PROLOG(SRR0, SRR1)
125 addi r3,r1,STACK_FRAME_OVERHEAD
126 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
128 /* Program check exception */
131 EXCEPTION_PROLOG(SRR0, SRR1)
132 addi r3,r1,STACK_FRAME_OVERHEAD
133 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
136 /* No FPU on MPC8xx. This exception is not supposed to happen.
138 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
140 /* I guess we could implement decrementer, and may have
141 * to someday for timekeeping.
143 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
144 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
145 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
146 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
147 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
149 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
150 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
153 * On the MPC8xx, this is a software emulation interrupt. It
154 * occurs for all unimplemented and illegal instructions.
156 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
158 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
159 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
160 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
161 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
163 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
164 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
165 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
166 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
167 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
168 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
169 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
171 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
172 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
173 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
174 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
176 .globl _end_of_vectors
182 /* disable everything */
191 /* init the L2 cache */
192 addis r3, r0, L2_INIT@h
193 ori r3, r3, L2_INIT@l
197 #if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
200 * dssall instruction, gas doesn't have it yet
201 * ...for altivec, data stream stop all this probably
202 * isn't needed unless we warm (software) reboot U-Boot
207 /* invalidate the L2 cache */
208 bl l2cache_invalidate
211 #ifdef CONFIG_SYS_BOARD_ASM_INIT
217 * Calculate absolute address in FLASH and jump there
218 *------------------------------------------------------*/
219 lis r3, CONFIG_SYS_MONITOR_BASE@h
220 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
221 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
226 /* let the C-code set up the rest */
228 /* Be careful to keep code relocatable ! */
229 /*------------------------------------------------------*/
231 /* perform low-level init */
232 /* sdram init, galileo init, etc */
233 /* r3: NHR bit from HID0 */
240 * Cache must be enabled here for stack-in-cache trick.
241 * This means we need to enable the BATS.
243 * 1) for the EVB, original gt regs need to be mapped
244 * 2) need to have an IBAT for the 0xf region,
245 * we are running there!
246 * Cache should be turned on after BATs, since by default
247 * everything is write-through.
248 * The init-mem BAT can be reused after reloc. The old
249 * gt-regs BAT can be reused after board_init_f calls
250 * board_early_init_f (EVB only).
252 #if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
253 /* enable address translation */
257 /* enable and invalidate the data cache */
261 #ifdef CONFIG_SYS_INIT_RAM_LOCK
266 /* set up the stack pointer in our newly created
268 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
269 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
271 li r0, 0 /* Make room for stack frame header and */
272 stwu r0, -4(r1) /* clear final stack frame so that */
273 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
275 GET_GOT /* initialize GOT access */
277 /* run low-level CPU init code (from Flash) */
281 /* run 1st part of board init code (from Flash) */
285 /* NOTREACHED - board_init_f() does not return */
287 .globl invalidate_bats
289 /* invalidate BATs */
294 #ifdef CONFIG_HIGH_BATS
305 #ifdef CONFIG_HIGH_BATS
315 /* setup_bats - set them up to some initial state */
321 addis r4, r0, CONFIG_SYS_IBAT0L@h
322 ori r4, r4, CONFIG_SYS_IBAT0L@l
323 addis r3, r0, CONFIG_SYS_IBAT0U@h
324 ori r3, r3, CONFIG_SYS_IBAT0U@l
330 addis r4, r0, CONFIG_SYS_DBAT0L@h
331 ori r4, r4, CONFIG_SYS_DBAT0L@l
332 addis r3, r0, CONFIG_SYS_DBAT0U@h
333 ori r3, r3, CONFIG_SYS_DBAT0U@l
339 addis r4, r0, CONFIG_SYS_IBAT1L@h
340 ori r4, r4, CONFIG_SYS_IBAT1L@l
341 addis r3, r0, CONFIG_SYS_IBAT1U@h
342 ori r3, r3, CONFIG_SYS_IBAT1U@l
348 addis r4, r0, CONFIG_SYS_DBAT1L@h
349 ori r4, r4, CONFIG_SYS_DBAT1L@l
350 addis r3, r0, CONFIG_SYS_DBAT1U@h
351 ori r3, r3, CONFIG_SYS_DBAT1U@l
357 addis r4, r0, CONFIG_SYS_IBAT2L@h
358 ori r4, r4, CONFIG_SYS_IBAT2L@l
359 addis r3, r0, CONFIG_SYS_IBAT2U@h
360 ori r3, r3, CONFIG_SYS_IBAT2U@l
366 addis r4, r0, CONFIG_SYS_DBAT2L@h
367 ori r4, r4, CONFIG_SYS_DBAT2L@l
368 addis r3, r0, CONFIG_SYS_DBAT2U@h
369 ori r3, r3, CONFIG_SYS_DBAT2U@l
375 addis r4, r0, CONFIG_SYS_IBAT3L@h
376 ori r4, r4, CONFIG_SYS_IBAT3L@l
377 addis r3, r0, CONFIG_SYS_IBAT3U@h
378 ori r3, r3, CONFIG_SYS_IBAT3U@l
384 addis r4, r0, CONFIG_SYS_DBAT3L@h
385 ori r4, r4, CONFIG_SYS_DBAT3L@l
386 addis r3, r0, CONFIG_SYS_DBAT3U@h
387 ori r3, r3, CONFIG_SYS_DBAT3U@l
392 #ifdef CONFIG_HIGH_BATS
394 addis r4, r0, CONFIG_SYS_IBAT4L@h
395 ori r4, r4, CONFIG_SYS_IBAT4L@l
396 addis r3, r0, CONFIG_SYS_IBAT4U@h
397 ori r3, r3, CONFIG_SYS_IBAT4U@l
403 addis r4, r0, CONFIG_SYS_DBAT4L@h
404 ori r4, r4, CONFIG_SYS_DBAT4L@l
405 addis r3, r0, CONFIG_SYS_DBAT4U@h
406 ori r3, r3, CONFIG_SYS_DBAT4U@l
412 addis r4, r0, CONFIG_SYS_IBAT5L@h
413 ori r4, r4, CONFIG_SYS_IBAT5L@l
414 addis r3, r0, CONFIG_SYS_IBAT5U@h
415 ori r3, r3, CONFIG_SYS_IBAT5U@l
421 addis r4, r0, CONFIG_SYS_DBAT5L@h
422 ori r4, r4, CONFIG_SYS_DBAT5L@l
423 addis r3, r0, CONFIG_SYS_DBAT5U@h
424 ori r3, r3, CONFIG_SYS_DBAT5U@l
430 addis r4, r0, CONFIG_SYS_IBAT6L@h
431 ori r4, r4, CONFIG_SYS_IBAT6L@l
432 addis r3, r0, CONFIG_SYS_IBAT6U@h
433 ori r3, r3, CONFIG_SYS_IBAT6U@l
439 addis r4, r0, CONFIG_SYS_DBAT6L@h
440 ori r4, r4, CONFIG_SYS_DBAT6L@l
441 addis r3, r0, CONFIG_SYS_DBAT6U@h
442 ori r3, r3, CONFIG_SYS_DBAT6U@l
448 addis r4, r0, CONFIG_SYS_IBAT7L@h
449 ori r4, r4, CONFIG_SYS_IBAT7L@l
450 addis r3, r0, CONFIG_SYS_IBAT7U@h
451 ori r3, r3, CONFIG_SYS_IBAT7U@l
457 addis r4, r0, CONFIG_SYS_DBAT7L@h
458 ori r4, r4, CONFIG_SYS_DBAT7L@l
459 addis r3, r0, CONFIG_SYS_DBAT7U@h
460 ori r3, r3, CONFIG_SYS_DBAT7U@l
466 /* bats are done, now invalidate the TLBs */
469 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
482 .globl enable_addr_trans
484 /* enable address translation */
486 ori r5, r5, (MSR_IR | MSR_DR)
491 .globl disable_addr_trans
493 /* disable address translation */
496 andi. r0, r3, (MSR_IR | MSR_DR)
504 * This code finishes saving the registers to the exception frame
505 * and jumps to the appropriate handler for the exception.
506 * Register r21 is pointer into trap frame, r1 has new stack pointer.
508 .globl transfer_to_handler
519 andi. r24,r23,0x3f00 /* get vector offset */
523 mtspr SPRG2,r22 /* r1 is now kernel sp */
524 lwz r24,0(r23) /* virtual address of handler */
525 lwz r23,4(r23) /* where to go when done */
530 rfi /* jump to handler, enable MMU */
533 mfmsr r28 /* Disable interrupts */
537 SYNC /* Some chip revs need this... */
552 lwz r2,_NIP(r1) /* Restore environment */
571 /*-----------------------------------------------------------------------*/
573 * void relocate_code (addr_sp, gd, addr_moni)
575 * This "function" does not return, instead it continues in RAM
576 * after relocating the monitor code.
580 * r5 = length in bytes
585 mr r1, r3 /* Set new stack pointer */
586 mr r9, r4 /* Save copy of Global Data pointer */
587 mr r10, r5 /* Save copy of Destination Address */
590 mr r3, r5 /* Destination Address */
591 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
592 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
593 lwz r5, GOT(__init_end)
595 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
600 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
606 /* First our own GOT */
608 /* then the one used by the C code */
615 bl board_relocate_rom
617 mr r3, r10 /* Destination Address */
618 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
619 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
620 lwz r5, GOT(__init_end)
622 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
627 beq cr1,4f /* In place copy is not necessary */
628 beq 7f /* Protect against 0 count */
647 * Now flush the cache: note that we must start from a cache aligned
648 * address. Otherwise we might miss one cache line.
652 beq 7f /* Always flush prefetch queue in any case */
660 sync /* Wait for all dcbst to complete on bus */
666 7: sync /* Wait for all icbi to complete on bus */
670 * We are done. Do not return, instead branch to second part of board
671 * initialization, now running from RAM.
673 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
682 * Relocation Function, r12 point to got2+0x8000
684 * Adjust got2 pointers, no need to check for 0, this code
685 * already puts a few entries in the table.
687 li r0,__got2_entries@sectoff@l
688 la r3,GOT(_GOT2_TABLE_)
689 lwz r11,GOT(_GOT2_TABLE_)
701 * Now adjust the fixups and the pointers to the fixups
702 * in case we need to move ourselves again.
704 li r0,__fixup_entries@sectoff@l
705 lwz r3,GOT(_FIXUP_TABLE_)
721 * Now clear BSS segment
723 lwz r3,GOT(__bss_start)
736 mr r3, r10 /* Destination Address */
737 #if defined(CONFIG_DB64360) || \
738 defined(CONFIG_DB64460) || \
739 defined(CONFIG_CPCI750) || \
740 defined(CONFIG_PPMC7XX) || \
742 mr r4, r9 /* Use RAM copy of the global data */
746 /* not reached - end relocate_code */
747 /*-----------------------------------------------------------------------*/
750 * Copy exception vector code to low memory
753 * r7: source address, r8: end address, r9: target address
757 mflr r4 /* save link register */
760 lwz r8, GOT(_end_of_vectors)
762 li r9, 0x100 /* reset vector always at 0x100 */
765 bgelr /* return if r7>=r8 - just in case */
775 * relocate `hdlr' and `int_return' entries
777 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
778 li r8, Alignment - _start + EXC_OFF_SYS_RESET
781 addi r7, r7, 0x100 /* next exception vector */
785 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
788 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
791 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
792 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
795 addi r7, r7, 0x100 /* next exception vector */
799 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
800 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
803 addi r7, r7, 0x100 /* next exception vector */
807 /* enable execptions from RAM vectors */
813 mtlr r4 /* restore link register */
816 #ifdef CONFIG_SYS_INIT_RAM_LOCK
818 /* Allocate Initial RAM in data cache.
820 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
821 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
822 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
823 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
830 /* Lock the data cache */
838 .globl unlock_ram_in_cache
840 /* invalidate the INIT_RAM section */
841 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
842 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
843 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
844 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
849 sync /* Wait for all icbi to complete on bus */
852 /* Unlock the data cache and invalidate it */