2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2001 Josh Huber <huber@mclx.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /* U-Boot - Startup Code for PowerPC based Embedded Boards
29 * The processor starts at 0xfff00100 and the code is executed
30 * from flash. The code is organized to be at an other address
31 * in memory, but as long we don't jump around before relocating.
32 * board_init lies at a quite high address and when the cpu has
33 * jumped there, everything is ok.
37 #include <timestamp.h>
40 #include <ppc_asm.tmpl>
43 #include <asm/cache.h>
46 #if !defined(CONFIG_DB64360) && \
47 !defined(CONFIG_DB64460) && \
48 !defined(CONFIG_CPCI750) && \
50 #include <galileo/gt64260R.h>
53 #ifndef CONFIG_IDENT_STRING
54 #define CONFIG_IDENT_STRING ""
57 /* We don't want the MMU yet.
60 /* Machine Check and Recoverable Interr. */
61 #define MSR_KERNEL ( MSR_ME | MSR_RI )
64 * Set up GOT: Global Offset Table
66 * Use r12 to access the GOT
69 GOT_ENTRY(_GOT2_TABLE_)
70 GOT_ENTRY(_FIXUP_TABLE_)
73 GOT_ENTRY(_start_of_vectors)
74 GOT_ENTRY(_end_of_vectors)
75 GOT_ENTRY(transfer_to_handler)
79 GOT_ENTRY(__bss_start)
83 * r3 - 1st arg to board_init(): IMMP pointer
84 * r4 - 2nd arg to board_init(): boot flag
87 .long 0x27051956 /* U-Boot Magic Number */
91 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
92 .ascii CONFIG_IDENT_STRING, "\0"
99 /* the boot code is located below the exception table */
101 .globl _start_of_vectors
105 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
107 /* Data Storage exception. "Never" generated on the 860. */
108 STD_EXCEPTION(0x300, DataStorage, UnknownException)
110 /* Instruction Storage exception. "Never" generated on the 860. */
111 STD_EXCEPTION(0x400, InstStorage, UnknownException)
113 /* External Interrupt exception. */
114 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
116 /* Alignment exception. */
119 EXCEPTION_PROLOG(SRR0, SRR1)
124 addi r3,r1,STACK_FRAME_OVERHEAD
125 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
127 /* Program check exception */
130 EXCEPTION_PROLOG(SRR0, SRR1)
131 addi r3,r1,STACK_FRAME_OVERHEAD
132 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
135 /* No FPU on MPC8xx. This exception is not supposed to happen.
137 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
139 /* I guess we could implement decrementer, and may have
140 * to someday for timekeeping.
142 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
143 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
144 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
145 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
146 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
148 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
149 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
152 * On the MPC8xx, this is a software emulation interrupt. It
153 * occurs for all unimplemented and illegal instructions.
155 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
157 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
158 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
159 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
160 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
162 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
163 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
164 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
165 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
166 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
167 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
168 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
170 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
171 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
172 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
173 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
175 .globl _end_of_vectors
181 /* disable everything */
190 /* init the L2 cache */
191 addis r3, r0, L2_INIT@h
192 ori r3, r3, L2_INIT@l
196 #if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
199 * dssall instruction, gas doesn't have it yet
200 * ...for altivec, data stream stop all this probably
201 * isn't needed unless we warm (software) reboot U-Boot
206 /* invalidate the L2 cache */
207 bl l2cache_invalidate
210 #ifdef CONFIG_SYS_BOARD_ASM_INIT
216 * Calculate absolute address in FLASH and jump there
217 *------------------------------------------------------*/
218 lis r3, CONFIG_SYS_MONITOR_BASE@h
219 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
220 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
225 /* let the C-code set up the rest */
227 /* Be careful to keep code relocatable ! */
228 /*------------------------------------------------------*/
230 /* perform low-level init */
231 /* sdram init, galileo init, etc */
232 /* r3: NHR bit from HID0 */
239 * Cache must be enabled here for stack-in-cache trick.
240 * This means we need to enable the BATS.
242 * 1) for the EVB, original gt regs need to be mapped
243 * 2) need to have an IBAT for the 0xf region,
244 * we are running there!
245 * Cache should be turned on after BATs, since by default
246 * everything is write-through.
247 * The init-mem BAT can be reused after reloc. The old
248 * gt-regs BAT can be reused after board_init_f calls
249 * board_early_init_f (EVB only).
251 #if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
252 /* enable address translation */
256 /* enable and invalidate the data cache */
260 #ifdef CONFIG_SYS_INIT_RAM_LOCK
265 /* set up the stack pointer in our newly created
267 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
268 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
270 li r0, 0 /* Make room for stack frame header and */
271 stwu r0, -4(r1) /* clear final stack frame so that */
272 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
274 GET_GOT /* initialize GOT access */
276 /* run low-level CPU init code (from Flash) */
280 /* run 1st part of board init code (from Flash) */
284 /* NOTREACHED - board_init_f() does not return */
286 .globl invalidate_bats
288 /* invalidate BATs */
293 #ifdef CONFIG_HIGH_BATS
304 #ifdef CONFIG_HIGH_BATS
314 /* setup_bats - set them up to some initial state */
320 addis r4, r0, CONFIG_SYS_IBAT0L@h
321 ori r4, r4, CONFIG_SYS_IBAT0L@l
322 addis r3, r0, CONFIG_SYS_IBAT0U@h
323 ori r3, r3, CONFIG_SYS_IBAT0U@l
329 addis r4, r0, CONFIG_SYS_DBAT0L@h
330 ori r4, r4, CONFIG_SYS_DBAT0L@l
331 addis r3, r0, CONFIG_SYS_DBAT0U@h
332 ori r3, r3, CONFIG_SYS_DBAT0U@l
338 addis r4, r0, CONFIG_SYS_IBAT1L@h
339 ori r4, r4, CONFIG_SYS_IBAT1L@l
340 addis r3, r0, CONFIG_SYS_IBAT1U@h
341 ori r3, r3, CONFIG_SYS_IBAT1U@l
347 addis r4, r0, CONFIG_SYS_DBAT1L@h
348 ori r4, r4, CONFIG_SYS_DBAT1L@l
349 addis r3, r0, CONFIG_SYS_DBAT1U@h
350 ori r3, r3, CONFIG_SYS_DBAT1U@l
356 addis r4, r0, CONFIG_SYS_IBAT2L@h
357 ori r4, r4, CONFIG_SYS_IBAT2L@l
358 addis r3, r0, CONFIG_SYS_IBAT2U@h
359 ori r3, r3, CONFIG_SYS_IBAT2U@l
365 addis r4, r0, CONFIG_SYS_DBAT2L@h
366 ori r4, r4, CONFIG_SYS_DBAT2L@l
367 addis r3, r0, CONFIG_SYS_DBAT2U@h
368 ori r3, r3, CONFIG_SYS_DBAT2U@l
374 addis r4, r0, CONFIG_SYS_IBAT3L@h
375 ori r4, r4, CONFIG_SYS_IBAT3L@l
376 addis r3, r0, CONFIG_SYS_IBAT3U@h
377 ori r3, r3, CONFIG_SYS_IBAT3U@l
383 addis r4, r0, CONFIG_SYS_DBAT3L@h
384 ori r4, r4, CONFIG_SYS_DBAT3L@l
385 addis r3, r0, CONFIG_SYS_DBAT3U@h
386 ori r3, r3, CONFIG_SYS_DBAT3U@l
391 #ifdef CONFIG_HIGH_BATS
393 addis r4, r0, CONFIG_SYS_IBAT4L@h
394 ori r4, r4, CONFIG_SYS_IBAT4L@l
395 addis r3, r0, CONFIG_SYS_IBAT4U@h
396 ori r3, r3, CONFIG_SYS_IBAT4U@l
402 addis r4, r0, CONFIG_SYS_DBAT4L@h
403 ori r4, r4, CONFIG_SYS_DBAT4L@l
404 addis r3, r0, CONFIG_SYS_DBAT4U@h
405 ori r3, r3, CONFIG_SYS_DBAT4U@l
411 addis r4, r0, CONFIG_SYS_IBAT5L@h
412 ori r4, r4, CONFIG_SYS_IBAT5L@l
413 addis r3, r0, CONFIG_SYS_IBAT5U@h
414 ori r3, r3, CONFIG_SYS_IBAT5U@l
420 addis r4, r0, CONFIG_SYS_DBAT5L@h
421 ori r4, r4, CONFIG_SYS_DBAT5L@l
422 addis r3, r0, CONFIG_SYS_DBAT5U@h
423 ori r3, r3, CONFIG_SYS_DBAT5U@l
429 addis r4, r0, CONFIG_SYS_IBAT6L@h
430 ori r4, r4, CONFIG_SYS_IBAT6L@l
431 addis r3, r0, CONFIG_SYS_IBAT6U@h
432 ori r3, r3, CONFIG_SYS_IBAT6U@l
438 addis r4, r0, CONFIG_SYS_DBAT6L@h
439 ori r4, r4, CONFIG_SYS_DBAT6L@l
440 addis r3, r0, CONFIG_SYS_DBAT6U@h
441 ori r3, r3, CONFIG_SYS_DBAT6U@l
447 addis r4, r0, CONFIG_SYS_IBAT7L@h
448 ori r4, r4, CONFIG_SYS_IBAT7L@l
449 addis r3, r0, CONFIG_SYS_IBAT7U@h
450 ori r3, r3, CONFIG_SYS_IBAT7U@l
456 addis r4, r0, CONFIG_SYS_DBAT7L@h
457 ori r4, r4, CONFIG_SYS_DBAT7L@l
458 addis r3, r0, CONFIG_SYS_DBAT7U@h
459 ori r3, r3, CONFIG_SYS_DBAT7U@l
465 /* bats are done, now invalidate the TLBs */
468 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
481 .globl enable_addr_trans
483 /* enable address translation */
485 ori r5, r5, (MSR_IR | MSR_DR)
490 .globl disable_addr_trans
492 /* disable address translation */
495 andi. r0, r3, (MSR_IR | MSR_DR)
503 * This code finishes saving the registers to the exception frame
504 * and jumps to the appropriate handler for the exception.
505 * Register r21 is pointer into trap frame, r1 has new stack pointer.
507 .globl transfer_to_handler
518 andi. r24,r23,0x3f00 /* get vector offset */
522 mtspr SPRG2,r22 /* r1 is now kernel sp */
523 lwz r24,0(r23) /* virtual address of handler */
524 lwz r23,4(r23) /* where to go when done */
529 rfi /* jump to handler, enable MMU */
532 mfmsr r28 /* Disable interrupts */
536 SYNC /* Some chip revs need this... */
551 lwz r2,_NIP(r1) /* Restore environment */
570 /*-----------------------------------------------------------------------*/
572 * void relocate_code (addr_sp, gd, addr_moni)
574 * This "function" does not return, instead it continues in RAM
575 * after relocating the monitor code.
579 * r5 = length in bytes
584 mr r1, r3 /* Set new stack pointer */
585 mr r9, r4 /* Save copy of Global Data pointer */
586 mr r10, r5 /* Save copy of Destination Address */
589 mr r3, r5 /* Destination Address */
590 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
591 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
592 lwz r5, GOT(__init_end)
594 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
599 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
605 /* First our own GOT */
607 /* then the one used by the C code */
614 bl board_relocate_rom
616 mr r3, r10 /* Destination Address */
617 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
618 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
619 lwz r5, GOT(__init_end)
621 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
626 beq cr1,4f /* In place copy is not necessary */
627 beq 7f /* Protect against 0 count */
646 * Now flush the cache: note that we must start from a cache aligned
647 * address. Otherwise we might miss one cache line.
651 beq 7f /* Always flush prefetch queue in any case */
659 sync /* Wait for all dcbst to complete on bus */
665 7: sync /* Wait for all icbi to complete on bus */
669 * We are done. Do not return, instead branch to second part of board
670 * initialization, now running from RAM.
672 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
681 * Relocation Function, r12 point to got2+0x8000
683 * Adjust got2 pointers, no need to check for 0, this code
684 * already puts a few entries in the table.
686 li r0,__got2_entries@sectoff@l
687 la r3,GOT(_GOT2_TABLE_)
688 lwz r11,GOT(_GOT2_TABLE_)
700 * Now adjust the fixups and the pointers to the fixups
701 * in case we need to move ourselves again.
703 li r0,__fixup_entries@sectoff@l
704 lwz r3,GOT(_FIXUP_TABLE_)
718 * Now clear BSS segment
720 lwz r3,GOT(__bss_start)
733 mr r3, r10 /* Destination Address */
734 #if defined(CONFIG_DB64360) || \
735 defined(CONFIG_DB64460) || \
736 defined(CONFIG_CPCI750) || \
737 defined(CONFIG_PPMC7XX) || \
739 mr r4, r9 /* Use RAM copy of the global data */
743 /* not reached - end relocate_code */
744 /*-----------------------------------------------------------------------*/
747 * Copy exception vector code to low memory
750 * r7: source address, r8: end address, r9: target address
754 mflr r4 /* save link register */
757 lwz r8, GOT(_end_of_vectors)
759 li r9, 0x100 /* reset vector always at 0x100 */
762 bgelr /* return if r7>=r8 - just in case */
772 * relocate `hdlr' and `int_return' entries
774 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
775 li r8, Alignment - _start + EXC_OFF_SYS_RESET
778 addi r7, r7, 0x100 /* next exception vector */
782 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
785 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
788 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
789 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
792 addi r7, r7, 0x100 /* next exception vector */
796 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
797 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
800 addi r7, r7, 0x100 /* next exception vector */
804 /* enable execptions from RAM vectors */
810 mtlr r4 /* restore link register */
813 #ifdef CONFIG_SYS_INIT_RAM_LOCK
815 /* Allocate Initial RAM in data cache.
817 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
818 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
819 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
820 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
827 /* Lock the data cache */
835 .globl unlock_ram_in_cache
837 /* invalidate the INIT_RAM section */
838 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
839 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
840 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
841 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
846 sync /* Wait for all icbi to complete on bus */
849 /* Unlock the data cache and invalidate it */