3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
35 * more modifications by
36 * Josh Huber <huber@mclx.com>
37 * added support for the 74xx series of cpus
38 * added support for the 7xx series of cpus
39 * made the code a little less hard-coded, and more auto-detectish
45 #include <asm/cache.h>
47 #if defined(CONFIG_OF_LIBFDT)
49 #include <fdt_support.h>
52 DECLARE_GLOBAL_DATA_PTR;
62 switch (PVR_VER(pvr)) {
69 if (((pvr >> 8) & 0xff) == 0x01) {
70 type = CPU_750CX; /* old CX (80100 and 8010x?)*/
71 } else if (((pvr >> 8) & 0xff) == 0x22) {
72 type = CPU_750CX; /* CX (82201,82202) and CXe (82214) */
73 } else if (((pvr >> 8) & 0xff) == 0x33) {
74 type = CPU_750CX; /* CXe (83311) */
75 } else if (((pvr >> 12) & 0xF) == 0x3) {
119 /* ------------------------------------------------------------------------- */
121 #if !defined(CONFIG_BAB7xx)
124 uint type = get_cpu_type();
125 uint pvr = get_pvr();
126 ulong clock = gd->cpu_clk;
134 printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"",
184 printf("Unknown CPU -- PVR: 0x%08x\n", pvr);
188 printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF);
190 printf (" @ %s MHz\n", strmhz(buf, clock));
195 /* these two functions are unimplemented currently [josh] */
197 /* -------------------------------------------------------------------- */
206 /* -------------------------------------------------------------------- */
215 /* -------------------------------------------------------------------- */
218 soft_restart(unsigned long addr)
220 /* SRR0 has system reset vector, SRR1 has default MSR value */
221 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
223 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
224 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
225 __asm__ __volatile__ ("mtspr 27, 4");
226 __asm__ __volatile__ ("rfi");
228 while(1); /* not reached */
232 #if !defined(CONFIG_PCIPPC2) && \
233 !defined(CONFIG_BAB7xx) && \
234 !defined(CONFIG_ELPPC) && \
235 !defined(CONFIG_PPMC7XX)
236 /* no generic way to do board reset. simply call soft_reset. */
238 do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
241 /* flush and disable I/D cache */
242 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
243 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
244 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
245 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
246 __asm__ __volatile__ ("sync");
247 __asm__ __volatile__ ("mtspr 1008, 4");
248 __asm__ __volatile__ ("isync");
249 __asm__ __volatile__ ("sync");
250 __asm__ __volatile__ ("mtspr 1008, 5");
251 __asm__ __volatile__ ("isync");
252 __asm__ __volatile__ ("sync");
254 #ifdef CONFIG_SYS_RESET_ADDRESS
255 addr = CONFIG_SYS_RESET_ADDRESS;
258 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
259 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
260 * address. Better pick an address known to be invalid on your
261 * system and assign it to CONFIG_SYS_RESET_ADDRESS.
263 addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
266 while(1); /* not reached */
270 /* ------------------------------------------------------------------------- */
273 * For the 7400 the TB clock runs at 1/4 the cpu bus speed.
275 #ifndef CONFIG_SYS_BUS_CLK
276 #define CONFIG_SYS_BUS_CLK gd->bus_clk
279 unsigned long get_tbclk(void)
281 return CONFIG_SYS_BUS_CLK / 4;
284 /* ------------------------------------------------------------------------- */
286 #if defined(CONFIG_WATCHDOG)
287 #if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
293 #endif /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */
294 #endif /* CONFIG_WATCHDOG */
296 /* ------------------------------------------------------------------------- */
298 #ifdef CONFIG_OF_LIBFDT
299 void ft_cpu_setup(void *blob, bd_t *bd)
301 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
302 "timebase-frequency", bd->bi_busfreq / 4, 1);
303 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
304 "bus-frequency", bd->bi_busfreq, 1);
305 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
306 "clock-frequency", bd->bi_intfreq, 1);
308 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
310 fdt_fixup_ethernet(blob);
313 /* ------------------------------------------------------------------------- */