arch/powerpc/boot/dts/mpc8377_mds.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * MPC8377E MDS Device Tree Source
   4  *
   5  * Copyright 2007 Freescale Semiconductor Inc.
   6  */
   7
   8 /dts-v1/;
   9
  10 / {
  11         model = "fsl,mpc8377emds";
  12         compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         aliases {
  17                 ethernet0 = &enet0;
  18                 ethernet1 = &enet1;
  19                 serial0 = &serial0;
  20                 serial1 = &serial1;
  21                 pci0 = &pci0;
  22                 pci1 = &pci1;
  23                 pci2 = &pci2;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 PowerPC,8377@0 {
  31                         device_type = "cpu";
  32                         reg = <0x0>;
  33                         d-cache-line-size = <32>;
  34                         i-cache-line-size = <32>;
  35                         d-cache-size = <32768>;
  36                         i-cache-size = <32768>;
  37                         timebase-frequency = <0>;
  38                         bus-frequency = <0>;
  39                         clock-frequency = <0>;
  40                 };
  41         };
  42
  43         memory {
  44                 device_type = "memory";
  45                 reg = <0x00000000 0x20000000>;  // 512MB at 0
  46         };
  47
  48         localbus@e0005000 {
  49                 #address-cells = <2>;
  50                 #size-cells = <1>;
  51                 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
  52                 reg = <0xe0005000 0x1000>;
  53                 interrupts = <77 0x8>;
  54                 interrupt-parent = <&ipic>;
  55
  56                 // booting from NOR flash
  57                 ranges = <0 0x0 0xfe000000 0x02000000
  58                           1 0x0 0xf8000000 0x00008000
  59                           3 0x0 0xe0600000 0x00008000>;
  60
  61                 flash@0,0 {
  62                         #address-cells = <1>;
  63                         #size-cells = <1>;
  64                         compatible = "cfi-flash";
  65                         reg = <0 0x0 0x2000000>;
  66                         bank-width = <2>;
  67                         device-width = <1>;
  68
  69                         u-boot@0 {
  70                                 reg = <0x0 0x100000>;
  71                                 read-only;
  72                         };
  73
  74                         fs@100000 {
  75                                 reg = <0x100000 0x800000>;
  76                         };
  77
  78                         kernel@1d00000 {
  79                                 reg = <0x1d00000 0x200000>;
  80                         };
  81
  82                         dtb@1f00000 {
  83                                 reg = <0x1f00000 0x100000>;
  84                         };
  85                 };
  86
  87                 bcsr@1,0 {
  88                         reg = <1 0x0 0x8000>;
  89                         compatible = "fsl,mpc837xmds-bcsr";
  90                 };
  91
  92                 nand@3,0 {
  93                         #address-cells = <1>;
  94                         #size-cells = <1>;
  95                         compatible = "fsl,mpc8377-fcm-nand",
  96                                      "fsl,elbc-fcm-nand";
  97                         reg = <3 0x0 0x8000>;
  98
  99                         u-boot@0 {
 100                                 reg = <0x0 0x100000>;
 101                                 read-only;
 102                         };
 103
 104                         kernel@100000 {
 105                                 reg = <0x100000 0x300000>;
 106                         };
 107
 108                         fs@400000 {
 109                                 reg = <0x400000 0x1c00000>;
 110                         };
 111                 };
 112         };
 113
 114         soc@e0000000 {
 115                 #address-cells = <1>;
 116                 #size-cells = <1>;
 117                 device_type = "soc";
 118                 compatible = "simple-bus";
 119                 ranges = <0x0 0xe0000000 0x00100000>;
 120                 reg = <0xe0000000 0x00000200>;
 121                 bus-frequency = <0>;
 122
 123                 wdt@200 {
 124                         compatible = "mpc83xx_wdt";
 125                         reg = <0x200 0x100>;
 126                 };
 127
 128                 sleep-nexus {
 129                         #address-cells = <1>;
 130                         #size-cells = <1>;
 131                         compatible = "simple-bus";
 132                         sleep = <&pmc 0x0c000000>;
 133                         ranges;
 134
 135                         i2c@3000 {
 136                                 #address-cells = <1>;
 137                                 #size-cells = <0>;
 138                                 cell-index = <0>;
 139                                 compatible = "fsl-i2c";
 140                                 reg = <0x3000 0x100>;
 141                                 interrupts = <14 0x8>;
 142                                 interrupt-parent = <&ipic>;
 143                                 dfsrr;
 144
 145                                 rtc@68 {
 146                                         compatible = "dallas,ds1374";
 147                                         reg = <0x68>;
 148                                         interrupts = <19 0x8>;
 149                                         interrupt-parent = <&ipic>;
 150                                 };
 151                         };
 152
 153                         sdhci@2e000 {
 154                                 compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
 155                                 reg = <0x2e000 0x1000>;
 156                                 interrupts = <42 0x8>;
 157                                 interrupt-parent = <&ipic>;
 158                                 sdhci,wp-inverted;
 159                                 /* Filled in by U-Boot */
 160                                 clock-frequency = <0>;
 161                         };
 162                 };
 163
 164                 i2c@3100 {
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         cell-index = <1>;
 168                         compatible = "fsl-i2c";
 169                         reg = <0x3100 0x100>;
 170                         interrupts = <15 0x8>;
 171                         interrupt-parent = <&ipic>;
 172                         dfsrr;
 173                 };
 174
 175                 spi@7000 {
 176                         cell-index = <0>;
 177                         compatible = "fsl,spi";
 178                         reg = <0x7000 0x1000>;
 179                         interrupts = <16 0x8>;
 180                         interrupt-parent = <&ipic>;
 181                         mode = "cpu";
 182                 };
 183
 184                 usb@23000 {
 185                         compatible = "fsl-usb2-dr";
 186                         reg = <0x23000 0x1000>;
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         interrupt-parent = <&ipic>;
 190                         interrupts = <38 0x8>;
 191                         dr_mode = "host";
 192                         phy_type = "ulpi";
 193                         sleep = <&pmc 0x00c00000>;
 194                 };
 195
 196                 enet0: ethernet@24000 {
 197                         #address-cells = <1>;
 198                         #size-cells = <1>;
 199                         cell-index = <0>;
 200                         device_type = "network";
 201                         model = "eTSEC";
 202                         compatible = "gianfar";
 203                         reg = <0x24000 0x1000>;
 204                         ranges = <0x0 0x24000 0x1000>;
 205                         local-mac-address = [ 00 00 00 00 00 00 ];
 206                         interrupts = <32 0x8 33 0x8 34 0x8>;
 207                         phy-connection-type = "mii";
 208                         interrupt-parent = <&ipic>;
 209                         tbi-handle = <&tbi0>;
 210                         phy-handle = <&phy2>;
 211                         sleep = <&pmc 0xc0000000>;
 212                         fsl,magic-packet;
 213
 214                         mdio@520 {
 215                                 #address-cells = <1>;
 216                                 #size-cells = <0>;
 217                                 compatible = "fsl,gianfar-mdio";
 218                                 reg = <0x520 0x20>;
 219
 220                                 phy2: ethernet-phy@2 {
 221                                         interrupt-parent = <&ipic>;
 222                                         interrupts = <17 0x8>;
 223                                         reg = <0x2>;
 224                                 };
 225
 226                                 phy3: ethernet-phy@3 {
 227                                         interrupt-parent = <&ipic>;
 228                                         interrupts = <18 0x8>;
 229                                         reg = <0x3>;
 230                                 };
 231
 232                                 tbi0: tbi-phy@11 {
 233                                         reg = <0x11>;
 234                                         device_type = "tbi-phy";
 235                                 };
 236                         };
 237                 };
 238
 239                 enet1: ethernet@25000 {
 240                         #address-cells = <1>;
 241                         #size-cells = <1>;
 242                         cell-index = <1>;
 243                         device_type = "network";
 244                         model = "eTSEC";
 245                         compatible = "gianfar";
 246                         reg = <0x25000 0x1000>;
 247                         ranges = <0x0 0x25000 0x1000>;
 248                         local-mac-address = [ 00 00 00 00 00 00 ];
 249                         interrupts = <35 0x8 36 0x8 37 0x8>;
 250                         phy-connection-type = "mii";
 251                         interrupt-parent = <&ipic>;
 252                         tbi-handle = <&tbi1>;
 253                         phy-handle = <&phy3>;
 254                         sleep = <&pmc 0x30000000>;
 255                         fsl,magic-packet;
 256
 257                         mdio@520 {
 258                                 #address-cells = <1>;
 259                                 #size-cells = <0>;
 260                                 compatible = "fsl,gianfar-tbi";
 261                                 reg = <0x520 0x20>;
 262
 263                                 tbi1: tbi-phy@11 {
 264                                         reg = <0x11>;
 265                                         device_type = "tbi-phy";
 266                                 };
 267                         };
 268                 };
 269
 270                 serial0: serial@4500 {
 271                         cell-index = <0>;
 272                         device_type = "serial";
 273                         compatible = "fsl,ns16550", "ns16550";
 274                         reg = <0x4500 0x100>;
 275                         clock-frequency = <0>;
 276                         interrupts = <9 0x8>;
 277                         interrupt-parent = <&ipic>;
 278                 };
 279
 280                 serial1: serial@4600 {
 281                         cell-index = <1>;
 282                         device_type = "serial";
 283                         compatible = "fsl,ns16550", "ns16550";
 284                         reg = <0x4600 0x100>;
 285                         clock-frequency = <0>;
 286                         interrupts = <10 0x8>;
 287                         interrupt-parent = <&ipic>;
 288                 };
 289
 290                 dma@82a8 {
 291                         #address-cells = <1>;
 292                         #size-cells = <1>;
 293                         compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
 294                         reg = <0x82a8 4>;
 295                         ranges = <0 0x8100 0x1a8>;
 296                         interrupt-parent = <&ipic>;
 297                         interrupts = <0x47 8>;
 298                         cell-index = <0>;
 299                         dma-channel@0 {
 300                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 301                                 reg = <0 0x80>;
 302                                 cell-index = <0>;
 303                                 interrupt-parent = <&ipic>;
 304                                 interrupts = <0x47 8>;
 305                         };
 306                         dma-channel@80 {
 307                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 308                                 reg = <0x80 0x80>;
 309                                 cell-index = <1>;
 310                                 interrupt-parent = <&ipic>;
 311                                 interrupts = <0x47 8>;
 312                         };
 313                         dma-channel@100 {
 314                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 315                                 reg = <0x100 0x80>;
 316                                 cell-index = <2>;
 317                                 interrupt-parent = <&ipic>;
 318                                 interrupts = <0x47 8>;
 319                         };
 320                         dma-channel@180 {
 321                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 322                                 reg = <0x180 0x28>;
 323                                 cell-index = <3>;
 324                                 interrupt-parent = <&ipic>;
 325                                 interrupts = <0x47 8>;
 326                         };
 327                 };
 328
 329                 crypto@30000 {
 330                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
 331                                      "fsl,sec2.1", "fsl,sec2.0";
 332                         reg = <0x30000 0x10000>;
 333                         interrupts = <11 0x8>;
 334                         interrupt-parent = <&ipic>;
 335                         fsl,num-channels = <4>;
 336                         fsl,channel-fifo-len = <24>;
 337                         fsl,exec-units-mask = <0x9fe>;
 338                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 339                         sleep = <&pmc 0x03000000>;
 340                 };
 341
 342                 sata@18000 {
 343                         compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
 344                         reg = <0x18000 0x1000>;
 345                         interrupts = <44 0x8>;
 346                         interrupt-parent = <&ipic>;
 347                         sleep = <&pmc 0x000000c0>;
 348                 };
 349
 350                 sata@19000 {
 351                         compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
 352                         reg = <0x19000 0x1000>;
 353                         interrupts = <45 0x8>;
 354                         interrupt-parent = <&ipic>;
 355                         sleep = <&pmc 0x00000030>;
 356                 };
 357
 358                 /* IPIC
 359                  * interrupts cell = <intr #, sense>
 360                  * sense values match linux IORESOURCE_IRQ_* defines:
 361                  * sense == 8: Level, low assertion
 362                  * sense == 2: Edge, high-to-low change
 363                  */
 364                 ipic: pic@700 {
 365                         compatible = "fsl,ipic";
 366                         interrupt-controller;
 367                         #address-cells = <0>;
 368                         #interrupt-cells = <2>;
 369                         reg = <0x700 0x100>;
 370                 };
 371
 372                 pmc: power@b00 {
 373                         compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
 374                         reg = <0xb00 0x100 0xa00 0x100>;
 375                         interrupts = <80 0x8>;
 376                         interrupt-parent = <&ipic>;
 377                 };
 378         };
 379
 380         pci0: pci@e0008500 {
 381                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 382                 interrupt-map = <
 383
 384                                 /* IDSEL 0x11 */
 385                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
 386                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
 387                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
 388                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
 389
 390                                 /* IDSEL 0x12 */
 391                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
 392                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
 393                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
 394                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
 395
 396                                 /* IDSEL 0x13 */
 397                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
 398                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
 399                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
 400                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
 401
 402                                 /* IDSEL 0x15 */
 403                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
 404                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
 405                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
 406                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
 407
 408                                 /* IDSEL 0x16 */
 409                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
 410                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
 411                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
 412                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
 413
 414                                 /* IDSEL 0x17 */
 415                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
 416                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
 417                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
 418                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
 419
 420                                 /* IDSEL 0x18 */
 421                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
 422                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
 423                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
 424                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 425                 interrupt-parent = <&ipic>;
 426                 interrupts = <66 0x8>;
 427                 bus-range = <0x0 0x0>;
 428                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 429                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 430                           0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
 431                 sleep = <&pmc 0x00010000>;
 432                 clock-frequency = <0>;
 433                 #interrupt-cells = <1>;
 434                 #size-cells = <2>;
 435                 #address-cells = <3>;
 436                 reg = <0xe0008500 0x100         /* internal registers */
 437                        0xe0008300 0x8>;         /* config space access registers */
 438                 compatible = "fsl,mpc8349-pci";
 439                 device_type = "pci";
 440         };
 441
 442         pci1: pcie@e0009000 {
 443                 #address-cells = <3>;
 444                 #size-cells = <2>;
 445                 #interrupt-cells = <1>;
 446                 device_type = "pci";
 447                 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
 448                 reg = <0xe0009000 0x00001000>;
 449                 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
 450                           0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
 451                 bus-range = <0 255>;
 452                 interrupt-map-mask = <0xf800 0 0 7>;
 453                 interrupt-map = <0 0 0 1 &ipic 1 8
 454                                  0 0 0 2 &ipic 1 8
 455                                  0 0 0 3 &ipic 1 8
 456                                  0 0 0 4 &ipic 1 8>;
 457                 sleep = <&pmc 0x00300000>;
 458                 clock-frequency = <0>;
 459
 460                 pcie@0 {
 461                         #address-cells = <3>;
 462                         #size-cells = <2>;
 463                         device_type = "pci";
 464                         reg = <0 0 0 0 0>;
 465                         ranges = <0x02000000 0 0xa8000000
 466                                   0x02000000 0 0xa8000000
 467                                   0 0x10000000
 468                                   0x01000000 0 0x00000000
 469                                   0x01000000 0 0x00000000
 470                                   0 0x00800000>;
 471                 };
 472         };
 473
 474         pci2: pcie@e000a000 {
 475                 #address-cells = <3>;
 476                 #size-cells = <2>;
 477                 #interrupt-cells = <1>;
 478                 device_type = "pci";
 479                 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
 480                 reg = <0xe000a000 0x00001000>;
 481                 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
 482                           0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
 483                 bus-range = <0 255>;
 484                 interrupt-map-mask = <0xf800 0 0 7>;
 485                 interrupt-map = <0 0 0 1 &ipic 2 8
 486                                  0 0 0 2 &ipic 2 8
 487                                  0 0 0 3 &ipic 2 8
 488                                  0 0 0 4 &ipic 2 8>;
 489                 sleep = <&pmc 0x000c0000>;
 490                 clock-frequency = <0>;
 491
 492                 pcie@0 {
 493                         #address-cells = <3>;
 494                         #size-cells = <2>;
 495                         device_type = "pci";
 496                         reg = <0 0 0 0 0>;
 497                         ranges = <0x02000000 0 0xc8000000
 498                                   0x02000000 0 0xc8000000
 499                                   0 0x10000000
 500                                   0x01000000 0 0x00000000
 501                                   0x01000000 0 0x00000000
 502                                   0 0x00800000>;
 503                 };
 504         };
 505 };