arch/powerpc/boot/dts/mpc832x_mds.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * MPC8323E EMDS Device Tree Source
   4  *
   5  * Copyright 2006 Freescale Semiconductor Inc.
   6  *
   7
   8  * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
   9  * this:
  10  *
  11  * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
  12  * 2) Solder a wire from U61-21 to P19A-23.  P19 is a grid of pins on the board
  13  *    next to the serial ports.
  14  * 3) Solder a wire from U61-22 to P19K-22.
  15  *
  16  * Note that there's a typo in the schematic.  The board labels the last column
  17  * of pins "P19K", but in the schematic, that column is called "P19J".  So if
  18  * you're going by the schematic, the pin is called "P19J-K22".
  19  */
  20
  21 /dts-v1/;
  22
  23 / {
  24         model = "MPC8323EMDS";
  25         compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
  26         #address-cells = <1>;
  27         #size-cells = <1>;
  28
  29         aliases {
  30                 ethernet0 = &enet0;
  31                 ethernet1 = &enet1;
  32                 serial0 = &serial0;
  33                 serial1 = &serial1;
  34                 pci0 = &pci0;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 PowerPC,8323@0 {
  42                         device_type = "cpu";
  43                         reg = <0x0>;
  44                         d-cache-line-size = <32>;       // 32 bytes
  45                         i-cache-line-size = <32>;       // 32 bytes
  46                         d-cache-size = <16384>;         // L1, 16K
  47                         i-cache-size = <16384>;         // L1, 16K
  48                         timebase-frequency = <0>;
  49                         bus-frequency = <0>;
  50                         clock-frequency = <0>;
  51                 };
  52         };
  53
  54         memory {
  55                 device_type = "memory";
  56                 reg = <0x00000000 0x08000000>;
  57         };
  58
  59         bcsr@f8000000 {
  60                 compatible = "fsl,mpc8323mds-bcsr";
  61                 reg = <0xf8000000 0x8000>;
  62         };
  63
  64         soc8323@e0000000 {
  65                 #address-cells = <1>;
  66                 #size-cells = <1>;
  67                 device_type = "soc";
  68                 compatible = "simple-bus";
  69                 ranges = <0x0 0xe0000000 0x00100000>;
  70                 reg = <0xe0000000 0x00000200>;
  71                 bus-frequency = <132000000>;
  72
  73                 wdt@200 {
  74                         device_type = "watchdog";
  75                         compatible = "mpc83xx_wdt";
  76                         reg = <0x200 0x100>;
  77                 };
  78
  79                 pmc: power@b00 {
  80                         compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
  81                         reg = <0xb00 0x100 0xa00 0x100>;
  82                         interrupts = <80 0x8>;
  83                         interrupt-parent = <&ipic>;
  84                 };
  85
  86                 i2c@3000 {
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                         cell-index = <0>;
  90                         compatible = "fsl-i2c";
  91                         reg = <0x3000 0x100>;
  92                         interrupts = <14 0x8>;
  93                         interrupt-parent = <&ipic>;
  94                         dfsrr;
  95
  96                         rtc@68 {
  97                                 compatible = "dallas,ds1374";
  98                                 reg = <0x68>;
  99                         };
 100                 };
 101
 102                 serial0: serial@4500 {
 103                         cell-index = <0>;
 104                         device_type = "serial";
 105                         compatible = "fsl,ns16550", "ns16550";
 106                         reg = <0x4500 0x100>;
 107                         clock-frequency = <0>;
 108                         interrupts = <9 0x8>;
 109                         interrupt-parent = <&ipic>;
 110                 };
 111
 112                 serial1: serial@4600 {
 113                         cell-index = <1>;
 114                         device_type = "serial";
 115                         compatible = "fsl,ns16550", "ns16550";
 116                         reg = <0x4600 0x100>;
 117                         clock-frequency = <0>;
 118                         interrupts = <10 0x8>;
 119                         interrupt-parent = <&ipic>;
 120                 };
 121
 122                 dma@82a8 {
 123                         #address-cells = <1>;
 124                         #size-cells = <1>;
 125                         compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
 126                         reg = <0x82a8 4>;
 127                         ranges = <0 0x8100 0x1a8>;
 128                         interrupt-parent = <&ipic>;
 129                         interrupts = <71 8>;
 130                         cell-index = <0>;
 131                         dma-channel@0 {
 132                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 133                                 reg = <0 0x80>;
 134                                 cell-index = <0>;
 135                                 interrupt-parent = <&ipic>;
 136                                 interrupts = <71 8>;
 137                         };
 138                         dma-channel@80 {
 139                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 140                                 reg = <0x80 0x80>;
 141                                 cell-index = <1>;
 142                                 interrupt-parent = <&ipic>;
 143                                 interrupts = <71 8>;
 144                         };
 145                         dma-channel@100 {
 146                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 147                                 reg = <0x100 0x80>;
 148                                 cell-index = <2>;
 149                                 interrupt-parent = <&ipic>;
 150                                 interrupts = <71 8>;
 151                         };
 152                         dma-channel@180 {
 153                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
 154                                 reg = <0x180 0x28>;
 155                                 cell-index = <3>;
 156                                 interrupt-parent = <&ipic>;
 157                                 interrupts = <71 8>;
 158                         };
 159                 };
 160
 161                 crypto@30000 {
 162                         compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
 163                         reg = <0x30000 0x10000>;
 164                         interrupts = <11 0x8>;
 165                         interrupt-parent = <&ipic>;
 166                         fsl,num-channels = <1>;
 167                         fsl,channel-fifo-len = <24>;
 168                         fsl,exec-units-mask = <0x4c>;
 169                         fsl,descriptor-types-mask = <0x0122003f>;
 170                         sleep = <&pmc 0x03000000>;
 171                 };
 172
 173                 ipic: pic@700 {
 174                         interrupt-controller;
 175                         #address-cells = <0>;
 176                         #interrupt-cells = <2>;
 177                         reg = <0x700 0x100>;
 178                         device_type = "ipic";
 179                 };
 180
 181                 par_io@1400 {
 182                         reg = <0x1400 0x100>;
 183                         device_type = "par_io";
 184                         num-ports = <7>;
 185
 186                         pio3: ucc_pin@3 {
 187                                 pio-map = <
 188                         /* port  pin  dir  open_drain  assignment  has_irq */
 189                                         3  4  3  0  2  0  /* MDIO */
 190                                         3  5  1  0  2  0  /* MDC */
 191                                         0 13  2  0  1  0        /* RX_CLK (CLK9) */
 192                                         3 24  2  0  1  0        /* TX_CLK (CLK10) */
 193                                         1  0  1  0  1  0        /* TxD0 */
 194                                         1  1  1  0  1  0        /* TxD1 */
 195                                         1  2  1  0  1  0        /* TxD2 */
 196                                         1  3  1  0  1  0        /* TxD3 */
 197                                         1  4  2  0  1  0        /* RxD0 */
 198                                         1  5  2  0  1  0        /* RxD1 */
 199                                         1  6  2  0  1  0        /* RxD2 */
 200                                         1  7  2  0  1  0        /* RxD3 */
 201                                         1  8  2  0  1  0        /* RX_ER */
 202                                         1  9  1  0  1  0        /* TX_ER */
 203                                         1 10  2  0  1  0        /* RX_DV */
 204                                         1 11  2  0  1  0        /* COL */
 205                                         1 12  1  0  1  0        /* TX_EN */
 206                                         1 13  2  0  1  0>;      /* CRS */
 207                         };
 208                         pio4: ucc_pin@4 {
 209                                 pio-map = <
 210                         /* port  pin  dir  open_drain  assignment  has_irq */
 211                                         3 31  2  0  1  0        /* RX_CLK (CLK7) */
 212                                         3  6  2  0  1  0        /* TX_CLK (CLK8) */
 213                                         1 18  1  0  1  0        /* TxD0 */
 214                                         1 19  1  0  1  0        /* TxD1 */
 215                                         1 20  1  0  1  0        /* TxD2 */
 216                                         1 21  1  0  1  0        /* TxD3 */
 217                                         1 22  2  0  1  0        /* RxD0 */
 218                                         1 23  2  0  1  0        /* RxD1 */
 219                                         1 24  2  0  1  0        /* RxD2 */
 220                                         1 25  2  0  1  0        /* RxD3 */
 221                                         1 26  2  0  1  0        /* RX_ER */
 222                                         1 27  1  0  1  0        /* TX_ER */
 223                                         1 28  2  0  1  0        /* RX_DV */
 224                                         1 29  2  0  1  0        /* COL */
 225                                         1 30  1  0  1  0        /* TX_EN */
 226                                         1 31  2  0  1  0>;      /* CRS */
 227                         };
 228                         pio5: ucc_pin@5 {
 229                                 pio-map = <
 230                                 /*
 231                                  *                    open       has
 232                                  *   port  pin  dir  drain  sel  irq
 233                                  */
 234                                         2    0    1      0    2    0  /* TxD5 */
 235                                         2    8    2      0    2    0  /* RxD5 */
 236
 237                                         2   29    2      0    0    0  /* CTS5 */
 238                                         2   31    1      0    2    0  /* RTS5 */
 239
 240                                         2   24    2      0    0    0  /* CD */
 241
 242                                 >;
 243                         };
 244
 245                 };
 246         };
 247
 248         qe@e0100000 {
 249                 #address-cells = <1>;
 250                 #size-cells = <1>;
 251                 device_type = "qe";
 252                 compatible = "fsl,qe";
 253                 ranges = <0x0 0xe0100000 0x00100000>;
 254                 reg = <0xe0100000 0x480>;
 255                 brg-frequency = <0>;
 256                 bus-frequency = <198000000>;
 257                 fsl,qe-num-riscs = <1>;
 258                 fsl,qe-num-snums = <28>;
 259
 260                 muram@10000 {
 261                         #address-cells = <1>;
 262                         #size-cells = <1>;
 263                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 264                         ranges = <0x0 0x00010000 0x00004000>;
 265
 266                         data-only@0 {
 267                                 compatible = "fsl,qe-muram-data",
 268                                              "fsl,cpm-muram-data";
 269                                 reg = <0x0 0x4000>;
 270                         };
 271                 };
 272
 273                 spi@4c0 {
 274                         cell-index = <0>;
 275                         compatible = "fsl,spi";
 276                         reg = <0x4c0 0x40>;
 277                         interrupts = <2>;
 278                         interrupt-parent = <&qeic>;
 279                         mode = "cpu";
 280                 };
 281
 282                 spi@500 {
 283                         cell-index = <1>;
 284                         compatible = "fsl,spi";
 285                         reg = <0x500 0x40>;
 286                         interrupts = <1>;
 287                         interrupt-parent = <&qeic>;
 288                         mode = "cpu";
 289                 };
 290
 291                 usb@6c0 {
 292                         compatible = "qe_udc";
 293                         reg = <0x6c0 0x40 0x8b00 0x100>;
 294                         interrupts = <11>;
 295                         interrupt-parent = <&qeic>;
 296                         mode = "slave";
 297                 };
 298
 299                 enet0: ucc@2200 {
 300                         device_type = "network";
 301                         compatible = "ucc_geth";
 302                         cell-index = <3>;
 303                         reg = <0x2200 0x200>;
 304                         interrupts = <34>;
 305                         interrupt-parent = <&qeic>;
 306                         local-mac-address = [ 00 00 00 00 00 00 ];
 307                         rx-clock-name = "clk9";
 308                         tx-clock-name = "clk10";
 309                         phy-handle = <&phy3>;
 310                         pio-handle = <&pio3>;
 311                 };
 312
 313                 enet1: ucc@3200 {
 314                         device_type = "network";
 315                         compatible = "ucc_geth";
 316                         cell-index = <4>;
 317                         reg = <0x3200 0x200>;
 318                         interrupts = <35>;
 319                         interrupt-parent = <&qeic>;
 320                         local-mac-address = [ 00 00 00 00 00 00 ];
 321                         rx-clock-name = "clk7";
 322                         tx-clock-name = "clk8";
 323                         phy-handle = <&phy4>;
 324                         pio-handle = <&pio4>;
 325                 };
 326
 327                 ucc@2400 {
 328                         device_type = "serial";
 329                         compatible = "ucc_uart";
 330                         cell-index = <5>;       /* The UCC number, 1-7*/
 331                         port-number = <0>;      /* Which ttyQEx device */
 332                         soft-uart;              /* We need Soft-UART */
 333                         reg = <0x2400 0x200>;
 334                         interrupts = <40>;      /* From Table 18-12 */
 335                         interrupt-parent = < &qeic >;
 336                         /*
 337                          * For Soft-UART, we need to set TX to 1X, which
 338                          * means specifying separate clock sources.
 339                          */
 340                         rx-clock-name = "brg5";
 341                         tx-clock-name = "brg6";
 342                         pio-handle = < &pio5 >;
 343                 };
 344
 345
 346                 mdio@2320 {
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349                         reg = <0x2320 0x18>;
 350                         compatible = "fsl,ucc-mdio";
 351
 352                         phy3: ethernet-phy@3 {
 353                                 interrupt-parent = <&ipic>;
 354                                 interrupts = <17 0x8>;
 355                                 reg = <0x3>;
 356                         };
 357                         phy4: ethernet-phy@4 {
 358                                 interrupt-parent = <&ipic>;
 359                                 interrupts = <18 0x8>;
 360                                 reg = <0x4>;
 361                         };
 362                 };
 363
 364                 qeic: interrupt-controller@80 {
 365                         interrupt-controller;
 366                         compatible = "fsl,qe-ic";
 367                         #address-cells = <0>;
 368                         #interrupt-cells = <1>;
 369                         reg = <0x80 0x80>;
 370                         big-endian;
 371                         interrupts = <32 0x8 33 0x8>; //high:32 low:33
 372                         interrupt-parent = <&ipic>;
 373                 };
 374         };
 375
 376         pci0: pci@e0008500 {
 377                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 378                 interrupt-map = <
 379                                 /* IDSEL 0x11 AD17 */
 380                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
 381                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
 382                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
 383                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
 384
 385                                 /* IDSEL 0x12 AD18 */
 386                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
 387                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
 388                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
 389                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
 390
 391                                 /* IDSEL 0x13 AD19 */
 392                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
 393                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
 394                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
 395                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
 396
 397                                 /* IDSEL 0x15 AD21*/
 398                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
 399                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
 400                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
 401                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
 402
 403                                 /* IDSEL 0x16 AD22*/
 404                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
 405                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
 406                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
 407                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
 408
 409                                 /* IDSEL 0x17 AD23*/
 410                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
 411                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
 412                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
 413                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
 414
 415                                 /* IDSEL 0x18 AD24*/
 416                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
 417                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
 418                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
 419                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 420                 interrupt-parent = <&ipic>;
 421                 interrupts = <66 0x8>;
 422                 bus-range = <0x0 0x0>;
 423                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 424                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 425                           0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
 426                 clock-frequency = <0>;
 427                 #interrupt-cells = <1>;
 428                 #size-cells = <2>;
 429                 #address-cells = <3>;
 430                 reg = <0xe0008500 0x100         /* internal registers */
 431                        0xe0008300 0x8>;         /* config space access registers */
 432                 compatible = "fsl,mpc8349-pci";
 433                 device_type = "pci";
 434                 sleep = <&pmc 0x00010000>;
 435         };
 436 };