arch/powerpc/boot/dts/fsl/t4240rdb.dts

   1 /*
   2  * T4240RDB Device Tree Source
   3  *
   4  * Copyright 2014 - 2015 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /include/ "t4240si-pre.dtsi"
  36
  37 / {
  38         model = "fsl,T4240RDB";
  39         compatible = "fsl,T4240RDB";
  40         #address-cells = <2>;
  41         #size-cells = <2>;
  42         interrupt-parent = <&mpic>;
  43
  44         aliases {
  45                 sgmii_phy21 = &sgmiiphy21;
  46                 sgmii_phy22 = &sgmiiphy22;
  47                 sgmii_phy23 = &sgmiiphy23;
  48                 sgmii_phy24 = &sgmiiphy24;
  49                 sgmii_phy41 = &sgmiiphy41;
  50                 sgmii_phy42 = &sgmiiphy42;
  51                 sgmii_phy43 = &sgmiiphy43;
  52                 sgmii_phy44 = &sgmiiphy44;
  53         };
  54
  55         ifc: localbus@ffe124000 {
  56                 reg = <0xf 0xfe124000 0 0x2000>;
  57                 ranges = <0 0 0xf 0xe8000000 0x08000000
  58                           2 0 0xf 0xff800000 0x00010000
  59                           3 0 0xf 0xffdf0000 0x00008000>;
  60
  61                 nor@0,0 {
  62                         #address-cells = <1>;
  63                         #size-cells = <1>;
  64                         compatible = "cfi-flash";
  65                         reg = <0x0 0x0 0x8000000>;
  66
  67                         bank-width = <2>;
  68                         device-width = <1>;
  69                 };
  70
  71                 nand@2,0 {
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         compatible = "fsl,ifc-nand";
  75                         reg = <0x2 0x0 0x10000>;
  76                 };
  77         };
  78
  79         memory {
  80                 device_type = "memory";
  81         };
  82
  83         reserved-memory {
  84                 #address-cells = <2>;
  85                 #size-cells = <2>;
  86                 ranges;
  87
  88                 bman_fbpr: bman-fbpr {
  89                         size = <0 0x1000000>;
  90                         alignment = <0 0x1000000>;
  91                 };
  92                 qman_fqd: qman-fqd {
  93                         size = <0 0x400000>;
  94                         alignment = <0 0x400000>;
  95                 };
  96                 qman_pfdr: qman-pfdr {
  97                         size = <0 0x2000000>;
  98                         alignment = <0 0x2000000>;
  99                 };
 100         };
 101
 102         dcsr: dcsr@f00000000 {
 103                 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
 104         };
 105
 106         bportals: bman-portals@ff4000000 {
 107                 ranges = <0x0 0xf 0xf4000000 0x2000000>;
 108         };
 109
 110         qportals: qman-portals@ff6000000 {
 111                 ranges = <0x0 0xf 0xf6000000 0x2000000>;
 112         };
 113
 114         soc: soc@ffe000000 {
 115                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
 116                 reg = <0xf 0xfe000000 0 0x00001000>;
 117                 spi@110000 {
 118                         flash@0 {
 119                                 #address-cells = <1>;
 120                                 #size-cells = <1>;
 121                                 compatible = "sst,sst25wf040", "jedec,spi-nor";
 122                                 reg = <0>;
 123                                 spi-max-frequency = <40000000>; /* input clock */
 124                         };
 125                 };
 126
 127                 i2c@118000 {
 128                         hwmon@2f {
 129                                 compatible = "winbond,w83793";
 130                                 reg = <0x2f>;
 131                         };
 132                         eeprom@52 {
 133                                 compatible = "atmel,24c256";
 134                                 reg = <0x52>;
 135                         };
 136                         eeprom@54 {
 137                                 compatible = "atmel,24c256";
 138                                 reg = <0x54>;
 139                         };
 140                         eeprom@56 {
 141                                 compatible = "atmel,24c256";
 142                                 reg = <0x56>;
 143                         };
 144                         rtc@68 {
 145                                 compatible = "dallas,ds1374";
 146                                 reg = <0x68>;
 147                                 interrupts = <0x1 0x1 0 0>;
 148                         };
 149                 };
 150
 151                 sdhc@114000 {
 152                         voltage-ranges = <1800 1800 3300 3300>;
 153                 };
 154
 155                 fman@400000 {
 156                         ethernet@e0000 {
 157                                 phy-handle = <&sgmiiphy21>;
 158                                 phy-connection-type = "sgmii";
 159                         };
 160
 161                         ethernet@e2000 {
 162                                 phy-handle = <&sgmiiphy22>;
 163                                 phy-connection-type = "sgmii";
 164                         };
 165
 166                         ethernet@e4000 {
 167                                 phy-handle = <&sgmiiphy23>;
 168                                 phy-connection-type = "sgmii";
 169                         };
 170
 171                         ethernet@e6000 {
 172                                 phy-handle = <&sgmiiphy24>;
 173                                 phy-connection-type = "sgmii";
 174                         };
 175
 176                         ethernet@e8000 {
 177                                 status = "disabled";
 178                         };
 179
 180                         ethernet@ea000 {
 181                                 status = "disabled";
 182                         };
 183
 184                         ethernet@f0000 {
 185                                 phy-handle = <&xfiphy1>;
 186                                 phy-connection-type = "xgmii";
 187                         };
 188
 189                         ethernet@f2000 {
 190                                 phy-handle = <&xfiphy2>;
 191                                 phy-connection-type = "xgmii";
 192                         };
 193                 };
 194
 195                 fman@500000 {
 196                         ethernet@e0000 {
 197                                 phy-handle = <&sgmiiphy41>;
 198                                 phy-connection-type = "sgmii";
 199                         };
 200
 201                         ethernet@e2000 {
 202                                 phy-handle = <&sgmiiphy42>;
 203                                 phy-connection-type = "sgmii";
 204                         };
 205
 206                         ethernet@e4000 {
 207                                 phy-handle = <&sgmiiphy43>;
 208                                 phy-connection-type = "sgmii";
 209                         };
 210
 211                         ethernet@e6000 {
 212                                 phy-handle = <&sgmiiphy44>;
 213                                 phy-connection-type = "sgmii";
 214                         };
 215
 216                         ethernet@e8000 {
 217                                 status = "disabled";
 218                         };
 219
 220                         ethernet@ea000 {
 221                                 status = "disabled";
 222                         };
 223
 224                         ethernet@f0000 {
 225                                 phy-handle = <&xfiphy3>;
 226                                 phy-connection-type = "xgmii";
 227                         };
 228
 229                         ethernet@f2000 {
 230                                 phy-handle = <&xfiphy4>;
 231                                 phy-connection-type = "xgmii";
 232                         };
 233
 234                         mdio@fc000 {
 235                                 sgmiiphy21: ethernet-phy@0 {
 236                                         reg = <0x0>;
 237                                 };
 238
 239                                 sgmiiphy22: ethernet-phy@1 {
 240                                         reg = <0x1>;
 241                                 };
 242
 243                                 sgmiiphy23: ethernet-phy@2 {
 244                                         reg = <0x2>;
 245                                 };
 246
 247                                 sgmiiphy24: ethernet-phy@3 {
 248                                         reg = <0x3>;
 249                                 };
 250
 251                                 sgmiiphy41: ethernet-phy@4 {
 252                                         reg = <0x4>;
 253                                 };
 254
 255                                 sgmiiphy42: ethernet-phy@5 {
 256                                         reg = <0x5>;
 257                                 };
 258
 259                                 sgmiiphy43: ethernet-phy@6 {
 260                                         reg = <0x6>;
 261                                 };
 262
 263                                 sgmiiphy44: ethernet-phy@7 {
 264                                         reg = <0x7>;
 265                                 };
 266                         };
 267
 268                         mdio@fd000 {
 269                                 xfiphy1: ethernet-phy@10 {
 270                                         compatible = "ethernet-phy-id13e5.1002";
 271                                         reg = <0x10>;
 272                                 };
 273
 274                                 xfiphy2: ethernet-phy@11 {
 275                                         compatible = "ethernet-phy-id13e5.1002";
 276                                         reg = <0x11>;
 277                                 };
 278
 279                                 xfiphy3: ethernet-phy@13 {
 280                                         compatible = "ethernet-phy-id13e5.1002";
 281                                         reg = <0x13>;
 282                                 };
 283
 284                                 xfiphy4: ethernet-phy@12 {
 285                                         compatible = "ethernet-phy-id13e5.1002";
 286                                         reg = <0x12>;
 287                                 };
 288                         };
 289                 };
 290         };
 291
 292         pci0: pcie@ffe240000 {
 293                 reg = <0xf 0xfe240000 0 0x10000>;
 294                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 295                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 296                 pcie@0 {
 297                         ranges = <0x02000000 0 0xe0000000
 298                                   0x02000000 0 0xe0000000
 299                                   0 0x20000000
 300
 301                                   0x01000000 0 0x00000000
 302                                   0x01000000 0 0x00000000
 303                                   0 0x00010000>;
 304                 };
 305         };
 306
 307         pci1: pcie@ffe250000 {
 308                 reg = <0xf 0xfe250000 0 0x10000>;
 309                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
 310                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
 311                 pcie@0 {
 312                         ranges = <0x02000000 0 0xe0000000
 313                                   0x02000000 0 0xe0000000
 314                                   0 0x20000000
 315
 316                                   0x01000000 0 0x00000000
 317                                   0x01000000 0 0x00000000
 318                                   0 0x00010000>;
 319                 };
 320         };
 321
 322         pci2: pcie@ffe260000 {
 323                 reg = <0xf 0xfe260000 0 0x1000>;
 324                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
 325                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
 326                 pcie@0 {
 327                         ranges = <0x02000000 0 0xe0000000
 328                                   0x02000000 0 0xe0000000
 329                                   0 0x20000000
 330
 331                                   0x01000000 0 0x00000000
 332                                   0x01000000 0 0x00000000
 333                                   0 0x00010000>;
 334                 };
 335         };
 336
 337         pci3: pcie@ffe270000 {
 338                 reg = <0xf 0xfe270000 0 0x10000>;
 339                 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
 340                           0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
 341                 pcie@0 {
 342                         ranges = <0x02000000 0 0xe0000000
 343                                   0x02000000 0 0xe0000000
 344                                   0 0x20000000
 345
 346                                   0x01000000 0 0x00000000
 347                                   0x01000000 0 0x00000000
 348                                   0 0x00010000>;
 349                 };
 350         };
 351
 352         rio: rapidio@ffe0c0000 {
 353                 reg = <0xf 0xfe0c0000 0 0x11000>;
 354
 355                 port1 {
 356                         ranges = <0 0 0xc 0x20000000 0 0x10000000>;
 357                 };
 358                 port2 {
 359                         ranges = <0 0 0xc 0x30000000 0 0x10000000>;
 360                 };
 361         };
 362 };
 363
 364 /include/ "t4240si-post.dtsi"