2 * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
3 * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/system.h>
24 void flush_dcache_range(unsigned long addr, unsigned long stop)
26 ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
29 mtspr(SPR_DCBFR, addr);
34 void invalidate_dcache_range(unsigned long addr, unsigned long stop)
36 ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
39 mtspr(SPR_DCBIR, addr);
44 static void invalidate_icache_range(unsigned long addr, unsigned long stop)
46 ulong block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16;
49 mtspr(SPR_ICBIR, addr);
54 void flush_cache(unsigned long addr, unsigned long size)
56 flush_dcache_range(addr, addr + size);
57 invalidate_icache_range(addr, addr + size);
60 int icache_status(void)
62 return mfspr(SPR_SR) & SPR_SR_ICE;
68 unsigned long cache_set_size;
69 unsigned long cache_ways;
70 unsigned long cache_block_size;
72 iccfgr = mfspr(SPR_ICCFGR);
73 cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
74 cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
75 cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
77 return cache_set_size * cache_ways * cache_block_size;
80 int dcache_status(void)
82 return mfspr(SPR_SR) & SPR_SR_DCE;
88 unsigned long cache_set_size;
89 unsigned long cache_ways;
90 unsigned long cache_block_size;
92 dccfgr = mfspr(SPR_DCCFGR);
93 cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
94 cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
95 cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
97 return cache_set_size * cache_ways * cache_block_size;
100 void dcache_enable(void)
102 mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
103 asm volatile("l.nop");
104 asm volatile("l.nop");
105 asm volatile("l.nop");
106 asm volatile("l.nop");
107 asm volatile("l.nop");
108 asm volatile("l.nop");
109 asm volatile("l.nop");
110 asm volatile("l.nop");
113 void dcache_disable(void)
115 mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE);
118 void icache_enable(void)
120 mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE);
121 asm volatile("l.nop");
122 asm volatile("l.nop");
123 asm volatile("l.nop");
124 asm volatile("l.nop");
125 asm volatile("l.nop");
126 asm volatile("l.nop");
127 asm volatile("l.nop");
128 asm volatile("l.nop");
131 void icache_disable(void)
133 mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);
138 if (mfspr(SPR_UPR) & SPR_UPR_ICP) {
140 invalidate_icache_range(0, checkicache());
144 if (mfspr(SPR_UPR) & SPR_UPR_DCP) {
146 invalidate_dcache_range(0, checkdcache());