arch/nios2/dts/10m50_devboard.dts

   1 /*
   2  *  Copyright (C) 2015 Altera Corporation
   3  *
   4  * This file is generated by sopc2dts.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /dts-v1/;
  10
  11 / {
  12         model = "Altera NiosII Max10";
  13         compatible = "altr,niosii-max10";
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu: cpu@0 {
  22                         u-boot,dm-pre-reloc;
  23                         device_type = "cpu";
  24                         compatible = "altr,nios2-1.1";
  25                         reg = <0x00000000>;
  26                         interrupt-controller;
  27                         #interrupt-cells = <1>;
  28                         altr,exception-addr = <0xc8000120>;
  29                         altr,fast-tlb-miss-addr = <0xc0000100>;
  30                         altr,has-div = <1>;
  31                         altr,has-initda = <1>;
  32                         altr,has-mmu = <1>;
  33                         altr,has-mul = <1>;
  34                         altr,implementation = "fast";
  35                         altr,pid-num-bits = <8>;
  36                         altr,reset-addr = <0xd4000000>;
  37                         altr,tlb-num-entries = <256>;
  38                         altr,tlb-num-ways = <16>;
  39                         altr,tlb-ptr-sz = <8>;
  40                         clock-frequency = <75000000>;
  41                         dcache-line-size = <32>;
  42                         dcache-size = <32768>;
  43                         icache-line-size = <32>;
  44                         icache-size = <32768>;
  45                 };
  46         };
  47
  48         memory {
  49                 device_type = "memory";
  50                 reg = <0x08000000 0x08000000>,
  51                         <0x00000000 0x00000400>;
  52         };
  53
  54         sopc0: sopc@0 {
  55                 device_type = "soc";
  56                 ranges;
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 compatible = "altr,avalon", "simple-bus";
  60                 bus-frequency = <75000000>;
  61
  62                 jtag_uart: serial@18001530 {
  63                         compatible = "altr,juart-1.0";
  64                         reg = <0x18001530 0x00000008>;
  65                         interrupt-parent = <&cpu>;
  66                         interrupts = <7>;
  67                 };
  68
  69                 a_16550_uart_0: serial@18001600 {
  70                         compatible = "altr,16550-FIFO32", "ns16550a";
  71                         reg = <0x18001600 0x00000200>;
  72                         interrupt-parent = <&cpu>;
  73                         interrupts = <1>;
  74                         auto-flow-control = <1>;
  75                         clock-frequency = <50000000>;
  76                         fifo-size = <32>;
  77                         reg-io-width = <4>;
  78                         reg-shift = <2>;
  79                 };
  80
  81                 ext_flash: quadspi@0x180014a0 {
  82                         compatible = "altr,quadspi-1.0";
  83                         reg = <0x180014a0 0x00000020>,
  84                                 <0x14000000 0x04000000>;
  85                         reg-names = "avl_csr", "avl_mem";
  86                         interrupt-parent = <&cpu>;
  87                         interrupts = <4>;
  88                         #address-cells = <1>;
  89                         #size-cells = <0>;
  90                         flash0: nor0@0 {
  91                                 compatible = "micron,n25q512a";
  92                                 #address-cells = <1>;
  93                                 #size-cells = <1>;
  94                         };
  95                 };
  96
  97                 sysid: sysid@18001528 {
  98                         compatible = "altr,sysid-1.0";
  99                         reg = <0x18001528 0x00000008>;
 100                 };
 101
 102                 rgmii_0_eth_tse_0: ethernet@400 {
 103                         compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0";
 104                         reg = <0x00000400 0x00000400>,
 105                                 <0x00000820 0x00000020>,
 106                                 <0x00000800 0x00000020>,
 107                                 <0x000008c0 0x00000008>,
 108                                 <0x00000840 0x00000020>,
 109                                 <0x00000860 0x00000020>;
 110                         reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp",
 111                                   "tx_csr", "tx_desc";
 112                         interrupt-parent = <&cpu>;
 113                         interrupts = <2 3>;
 114                         interrupt-names = "rx_irq", "tx_irq";
 115                         rx-fifo-depth = <8192>;
 116                         tx-fifo-depth = <8192>;
 117                         address-bits = <48>;
 118                         max-frame-size = <1518>;
 119                         local-mac-address = [00 00 00 00 00 00];
 120                         altr,has-supplementary-unicast;
 121                         altr,enable-sup-addr = <1>;
 122                         altr,has-hash-multicast-filter;
 123                         altr,enable-hash = <1>;
 124                         phy-mode = "rgmii-id";
 125                         phy-handle = <&phy0>;
 126                         rgmii_0_eth_tse_0_mdio: mdio {
 127                                 compatible = "altr,tse-mdio";
 128                                 #address-cells = <1>;
 129                                 #size-cells = <0>;
 130                                 phy0: ethernet-phy@0 {
 131                                         reg = <0>;
 132                                         device_type = "ethernet-phy";
 133                                 };
 134                         };
 135                 };
 136
 137                 enet_pll: clock@0 {
 138                         compatible = "altr,pll-1.0";
 139                         #clock-cells = <1>;
 140
 141                         enet_pll_c0: enet_pll_c0 {
 142                                 compatible = "fixed-clock";
 143                                 #clock-cells = <0>;
 144                                 clock-frequency = <125000000>;
 145                                 clock-output-names = "enet_pll-c0";
 146                         };
 147
 148                         enet_pll_c1: enet_pll_c1 {
 149                                 compatible = "fixed-clock";
 150                                 #clock-cells = <0>;
 151                                 clock-frequency = <25000000>;
 152                                 clock-output-names = "enet_pll-c1";
 153                         };
 154
 155                         enet_pll_c2: enet_pll_c2 {
 156                                 compatible = "fixed-clock";
 157                                 #clock-cells = <0>;
 158                                 clock-frequency = <2500000>;
 159                                 clock-output-names = "enet_pll-c2";
 160                         };
 161                 };
 162
 163                 sys_pll: clock@1 {
 164                         compatible = "altr,pll-1.0";
 165                         #clock-cells = <1>;
 166
 167                         sys_pll_c0: sys_pll_c0 {
 168                                 compatible = "fixed-clock";
 169                                 #clock-cells = <0>;
 170                                 clock-frequency = <100000000>;
 171                                 clock-output-names = "sys_pll-c0";
 172                         };
 173
 174                         sys_pll_c1: sys_pll_c1 {
 175                                 compatible = "fixed-clock";
 176                                 #clock-cells = <0>;
 177                                 clock-frequency = <50000000>;
 178                                 clock-output-names = "sys_pll-c1";
 179                         };
 180
 181                         sys_pll_c2: sys_pll_c2 {
 182                                 compatible = "fixed-clock";
 183                                 #clock-cells = <0>;
 184                                 clock-frequency = <75000000>;
 185                                 clock-output-names = "sys_pll-c2";
 186                         };
 187                 };
 188
 189                 sys_clk_timer: timer@18001440 {
 190                         compatible = "altr,timer-1.0";
 191                         reg = <0x18001440 0x00000020>;
 192                         interrupt-parent = <&cpu>;
 193                         interrupts = <0>;
 194                         clock-frequency = <75000000>;
 195                 };
 196
 197                 led_pio: gpio@180014d0 {
 198                         compatible = "altr,pio-1.0";
 199                         reg = <0x180014d0 0x00000010>;
 200                         altr,gpio-bank-width = <4>;
 201                         resetvalue = <15>;
 202                         #gpio-cells = <2>;
 203                         gpio-controller;
 204                         gpio-bank-name = "led";
 205                 };
 206
 207                 uart_0: serial@0x18001420 {
 208                         compatible = "altr,uart-1.0";
 209                         reg = <0x18001420 0x00000020>;
 210                         interrupt-parent = <&cpu>;
 211                         interrupts = <1>;
 212                         clock-frequency = <75000000>;
 213                         current-speed = <115200>;
 214                 };
 215
 216                 button_pio: gpio@180014c0 {
 217                         compatible = "altr,pio-1.0";
 218                         reg = <0x180014c0 0x00000010>;
 219                         interrupt-parent = <&cpu>;
 220                         interrupts = <6>;
 221                         altr,gpio-bank-width = <3>;
 222                         altr,interrupt-type = <2>;
 223                         edge_type = <1>;
 224                         level_trigger = <0>;
 225                         resetvalue = <0>;
 226                         #gpio-cells = <2>;
 227                         gpio-controller;
 228                         gpio-bank-name = "button";
 229                 };
 230
 231                 sys_clk_timer_1: timer@880 {
 232                         compatible = "altr,timer-1.0";
 233                         reg = <0x00000880 0x00000020>;
 234                         interrupt-parent = <&cpu>;
 235                         interrupts = <5>;
 236                         clock-frequency = <75000000>;
 237                 };
 238
 239                 fpga_leds: leds {
 240                         compatible = "gpio-leds";
 241
 242                         led_fpga0: fpga0 {
 243                                 label = "fpga_led0";
 244                                 gpios = <&led_pio 0 1>;
 245                         };
 246
 247                         led_fpga1: fpga1 {
 248                                 label = "fpga_led1";
 249                                 gpios = <&led_pio 1 1>;
 250                         };
 251
 252                         led_fpga2: fpga2 {
 253                                 label = "fpga_led2";
 254                                 gpios = <&led_pio 2 1>;
 255                         };
 256
 257                         led_fpga3: fpga3 {
 258                                 label = "fpga_led3";
 259                                 gpios = <&led_pio 3 1>;
 260                         };
 261                 };
 262         };
 263
 264         chosen {
 265                 bootargs = "debug console=ttyS0,115200";
 266                 stdout-path = &a_16550_uart_0;
 267         };
 268 };