1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
4 * Scott McNutt <smcnutt@psyent.com>
7 #include <asm-offsets.h>
12 * icache and dcache configuration used only for start.S.
13 * the values are chosen so that it will work for all configuration.
15 #define ICACHE_LINE_SIZE 32 /* fixed 32 */
16 #define ICACHE_SIZE_MAX 0x10000 /* 64k max */
17 #define DCACHE_LINE_SIZE_MIN 4 /* 4, 16, 32 */
18 #define DCACHE_SIZE_MAX 0x10000 /* 64k max */
22 .global _start, _except_start, _except_end
25 wrctl status, r0 /* Disable interrupts */
27 * ICACHE INIT -- only the icache line at the reset address
28 * is invalidated at reset. So the init must stay within
29 * the cache line size (8 words). If GERMS is used, we'll
30 * just be invalidating the cache a second time. If cache
31 * is not implemented initi behaves as nop.
33 ori r4, r0, %lo(ICACHE_LINE_SIZE)
34 movhi r5, %hi(ICACHE_SIZE_MAX)
35 ori r5, r5, %lo(ICACHE_SIZE_MAX)
39 br _except_end /* Skip the tramp */
42 * EXCEPTION TRAMPOLINE -- the following gets copied
43 * to the exception address (below), but is otherwise at the
44 * default exception vector offset (0x0020).
47 movhi et, %hi(_exception)
48 ori et, et, %lo(_exception)
53 * INTERRUPTS -- for now, all interrupts masked and globally
56 wrctl ienable, r0 /* All disabled */
59 * DCACHE INIT -- if dcache not implemented, initd behaves as
62 ori r4, r0, %lo(DCACHE_LINE_SIZE_MIN)
63 movhi r5, %hi(DCACHE_SIZE_MAX)
64 ori r5, r5, %lo(DCACHE_SIZE_MAX)
71 * RELOCATE CODE, DATA & COMMAND TABLE -- the following code
72 * assumes code, data and the command table are all
73 * contiguous. This lets us relocate everything as a single
74 * block. Make sure the linker script matches this ;-)
77 _cur: movhi r5, %hi(_cur - _start)
78 ori r5, r5, %lo(_cur - _start)
79 sub r4, r4, r5 /* r4 <- cur _start */
82 ori r5, r5, %lo(_start) /* r5 <- linked _start */
83 mov sp, r5 /* initial stack below u-boot code */
86 movhi r6, %hi(CONFIG_SYS_MONITOR_LEN)
87 ori r6, r6, %lo(CONFIG_SYS_MONITOR_LEN)
96 /* JUMP TO RELOC ADDR */
98 ori r4, r4, %lo(_reloc)
102 /* STACK INIT -- zero top two words for call back chain. */
108 #ifdef CONFIG_DEBUG_UART
109 /* Set up the debug UART */
110 movhi r2, %hi(debug_uart_init@h)
111 ori r2, r2, %lo(debug_uart_init@h)
115 /* Allocate and initialize reserved area, update SP */
117 movhi r2, %hi(board_init_f_alloc_reserve@h)
118 ori r2, r2, %lo(board_init_f_alloc_reserve@h)
122 movhi r2, %hi(board_init_f_init_reserve@h)
123 ori r2, r2, %lo(board_init_f_init_reserve@h)
126 /* Update frame-pointer */
129 /* Call board_init_f -- never returns */
131 movhi r2, %hi(board_init_f@h)
132 ori r2, r2, %lo(board_init_f@h)
136 * NEVER RETURNS -- but branch to the _start just
142 * relocate_code -- Nios2 handles the relocation above. But
143 * the generic board code monkeys with the heap, stack, etc.
144 * (it makes some assumptions that may not be appropriate
145 * for Nios). Nevertheless, we capitulate here.
147 * We'll call the board_init_r from here since this isn't
148 * supposed to return.
150 * void relocate_code(ulong sp, gd_t *global_data,
152 * __attribute__ ((noreturn));
155 .global relocate_code
158 mov sp, r4 /* Set the new sp */
162 * ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent
163 * and between __bss_start and __bss_end.
165 movhi r5, %hi(__bss_start)
166 ori r5, r5, %lo(__bss_start)
167 movhi r6, %hi(__bss_end)
168 ori r6, r6, %lo(__bss_end)
176 movhi r8, %hi(board_init_r@h)
177 ori r8, r8, %lo(board_init_r@h)