2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/macro.h>
15 #include <generated/asm-offsets.h>
18 * parameters for the SDRAM controller
20 #define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
21 #define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
22 #define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
23 #define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
24 #define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
25 #define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
27 #define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
28 #define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
29 #define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
30 #define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
32 #define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
33 #define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
37 * for Orca and Emerald
39 #define BOARD_ID_REG 0x104
40 #define BOARD_ID_FAMILY_MASK 0xfff000
41 #define BOARD_ID_FAMILY_V5 0x556000
42 #define BOARD_ID_FAMILY_K7 0x74b000
45 * parameters for the static memory controller
47 #define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
48 #define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
50 #define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
51 #define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
54 * parameters for the ahbc controller
56 #define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
57 #define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
60 * for Orca and Emerald
62 #define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
63 #define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
66 * parameters for the pmu controoler
68 #define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
71 * numeric 7 segment display
74 write32 CONFIG_DEBUG_LED, \num
78 * Waiting for SDRAM to set up
81 li $r0, CONFIG_FTSDMC021_BASE
83 lwi $r1, [$r0+FTSDMC021_CR2]
87 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
98 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
111 * There are 2 bank connected to FTSMC020 on AG101
112 * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
113 * we need to set onboard SDRAM before remap and relocation.
118 * for Orca and Emerald
119 * disable write protection and reset bank size
121 li $r0, SMC_BANK0_CR_A
128 li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
130 li $r4, BOARD_ID_FAMILY_MASK
132 li $r4, BOARD_ID_FAMILY_K7
134 beqz $r4, use_flash_16bit_boot
138 use_flash_32bit_boot:
145 use_flash_16bit_boot:
156 * config AHB Controller
161 * config PMU controller
163 /* ftpmu010_dlldis_disable, must do it in lowleve_init */
165 setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
168 * config SDRAM controller
171 write32 SDMC_TP1_A, SDMC_TP1_D ! 0x00011312
173 write32 SDMC_TP2_A, SDMC_TP2_D ! 0x00480180
175 write32 SDMC_CR1_A, SDMC_CR1_D ! 0x00002326
178 write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC ! 0x00000010
182 write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR ! 0x00000004
186 write32 SDMC_CR2_A, FTSDMC021_CR2_IREF ! 0x00000008
195 #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
202 #endif /* __NDS32_N1213_43U1H__ */
208 write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001100
209 write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001140
211 /* clear empty BSR registers */
213 li $r4, CONFIG_FTSDMC021_BASE
215 swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
216 swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
218 #ifdef CONFIG_MEM_REMAP
220 * Copy ROM code to SDRAM base for memory remap layout.
221 * This is not the real relocation, the real relocation is the function
222 * relocate_code() is start.S which supports the systems is memory
226 * Doing memory remap is essential for preparing some non-OS or RTOS
229 * This is also a must on ADP-AG101 board.
230 * The reason is because the ROM/FLASH circuit on PCB board.
231 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
232 * ROM/FLASH is used to boot.
234 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
235 * and the FLASH is connected to BANK1.
236 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
237 * and the FLASH is connected to BANK0.
238 * It will occur problem when doing flash probing if the flash is at
239 * BANK0 (0x00000000) while memory remapping was skipped.
241 * Other board like ADP-AG101P may not enable this since there is only
242 * a FLASH connected to bank0.
246 * for Orca and Emerald
247 * read sdram base address automatically
256 la $r1, relo_base /* get $pc or $lp */
258 sethi $r6, hi20(_end)
259 ori $r6, $r6, lo12(_end)
268 * MEM remap bit is operational
269 * - use it to map writeable memory at 0x00000000, in place of flash
270 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
271 * - after remap: flash/rom 0x80000000, sdram: 0x00000000
274 write32 SDMC_B0_BSR_A, 0x00001000
275 write32 SDMC_B1_BSR_A, 0x00001040
276 setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
279 * for Orca and Emerald
280 * extend sdram size from 256MB to 2GB
291 * for Orca and Emerald
292 * extend rom base from 256MB to 2GB
301 #endif /* #ifdef CONFIG_MEM_REMAP */
308 * Some of Andes CPU version support FPU coprocessor, if so,
309 * and toolchain support FPU instruction set, we should enable it.
311 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
313 mfsr $r0, $CPU_VER /* enable FPU if it exists */
316 beqz $r0, 1f /* skip if no COP */
317 mfsr $r0, $FUCOP_EXIST
319 beqz $r0, 1f /* skip if no FPU */
329 li $r8, (CONFIG_DEBUG_LED)
332 #endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */